IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005 2573

A 3.1- to 8.2-GHz Zero-IF Receiver and DirectFrequency Synthesizer in 0.18-�m SiGe BiCMOS for

Mode-2 MB-OFDM UWB CommunicationAly Ismail and Asad A. Abidi, Fellow, IEEE

Abstract—A direct conversion receiver for ultra-wideband(UWB) applications operates for 3.1 to 8.2 GHz and gives a noisefigure of 3.3 to 4.1 dB and a conversion gain of 52 dB. The chipincludes the RF receive chain and a 16-GHz quadrature VCOto generate seven carrier frequencies from 3.4 to 7.9 GHz. Thecircuit was fabricated in a 0.18- m SiGe BiCMOS process andconsumes 88 mA from a 2.7-V supply.

Index Terms—Amplifier noise, direct frequency synthesizer,low-noise amplifier, noise figure, SiGe amplifier, spurs, spursanalysis, ultra-wideband, wideband matching.

I. INTRODUCTION

ULTRA-WIDE-BAND (UWB) systems have recentlyreceived a great deal of interest due to their potential for

high-speed wireless communication [1]–[3]. As part of IEEEP802.15, multiband orthogonal frequency division multiplexing(MB-OFDM) with fast frequency hopping is proposed as ameans of high bit-rate wireless communication in the UWBspectrum. In mode-2 devices, the spectrum is divided into528-MHz bands spanning 3.1–8.2 GHz, as shown in Fig. 1.

The receiver front-end of such a system should have high lin-earity and a wideband local oscillator (LO) capable of frequencyhopping in less than 9 ns. These features must be obtained atmoderate power consumption and, to minimize cost, on a singlechip. Compared to narrowband receivers, MB-OFDM poses anew set of challenges. The main ones are summarized below.

1) A wideband input impedance matching is required thatspans 3 to 8 GHz. The low-noise amplifier (LNA) at thefront-end of the receiver should provide a reasonably lownoise figure and high gain at low current consumption.This is very difficult to achieve using conventional nar-rowband LNAs or resistive feedback amplifiers [4].

2) When receiving one channel, signals in other channelsenter the receiver and appear as blockers. As a result, inaddition to in-band linearity constraints, the widebandreceiver is vulnerable to cross-band compression. Whilein-band compression is mitigated with automatic gaincontrol, the cascaded receive chain should be sufficiently

Manuscript received April 26, 2005; revised July 15, 2005.A. Ismail is with the Integrated Circuits and Systems Laboratory, Electrical

Engineering Department, University of California, Los Angeles, CA 90095USA. He is also with Newport Media, Inc., Lake Forest, CA 92630 USA(e-mail: aly.ismail@newportmediainc.com).

A. A. Abidi is with the Integrated Circuits and Systems Laboratory ElectricalEngineering Department University of California, Los Angeles, CA 90095 USA(e-mail: abidi@icsl.ucla.edu).

Digital Object Identifier 10.1109/JSSC.2005.857423

Fig. 1. UWB allocated spectrum for mode-2 MB-OFDM devices consistingof seven frequency channels.

Fig. 2. Cross-band compression of the signal in channel no. 2 due to interfererin channel no. 5.

linear to prevent cross-band compression. This problem isillustrated in Fig. 2. Suppose the receiver is in maximumgain mode since the in-band signal (band 2) is weak. Astrong interferer (band 5) desensitizes the receive chainand degrades the desired signal gain. In the extreme casewhen all the out-of-band channels are at their peak level,the largest signal driving the LNA is 8.4 dB higher thanin the single-band case. This penalizes the widebandreceiver with about five times larger signals than is thecase in narrowband systems such as GSM or WCDMA,where the 1-dB compression point is usually set by thelargest close-in interferer specified by the blocker profile.

3) Coexistence with other bands in 3–8 GHz gives rise tonew linearity constraints that do not exist in narrowbandreceivers. For instance, in narrowband systems, harmonicdistortion due to second-order nonlinearity is unimportantsince it lies out of band. However, in this wideband re-ceiver, second-order distortion from channel 1 falls intochannel 5.

4) The receiver needs a channel-select filter with a highcutoff frequency of 264 MHz. It is particularly difficult torealize an active filter with poles in this frequency rangethat also satisfies the stringent dynamic range withoutconsuming a high current.

5) The receiver needs an agile wideband frequency synthe-sizer spanning 3.4 to 7.9 GHz.

6) Wideband systems use complex modulation schemes,whose crowded constellations place greater demands

0018-9200/$20.00 © 2005 IEEE

2574 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 3. LO spurs down-convert the adjacent channels to DC and overlappingthe desired signal.

on gain balance between the and channels, and onquadrature accuracy of LO phases.

7) Frequency spurs on the LO signal, even ones that are faraway, can down-convert in-band signals to the same fre-quency as the wanted band, as shown in Fig. 3. In ourrealization, it is much more difficult to meet the specifi-cations on low LO spurs than the specifications on lowphase noise.

In a frequency-hopping direct-conversion receiver, imperfec-tions and mismatches in the RF chain result in undesired sig-nals at DC as well as a fixed-pattern noise at the hopping fre-quency. Fixed-pattern noise arises from varying DC offset dueto LO self-mixing as the receiver hops across channels. Thispaper only addresses the offset that lies at DC. The cancellationof the modulated DC offset at the hopping frequency is assumedto be handled by digital calibration after the ADC.

This paper describes a fully integrated SiGe MB-OFDM re-ceiver. Sections II and III explain the proposed architecture andits rationale. The circuit design of the various building blocks iscovered in Section IV. Finally, the experimental results and thelayout issues are presented in Section V.

II. RECEIVER ARCHITECTURE

Among the many ways to architect a receiver for widebandchannels, direct conversion should be considered first sincemixer and baseband flicker noise have a minor effect, and staticDC offset can be removed with a small sacrifice of informationbandwidth. In the proposed architecture shown in Fig. 4, asingle RF chain receives the signal and a single frequencysynthesizer generates the required LO. Multiple LNAs to coverthe wideband [5] or several LO generators [6] are not needed,simplifying the overall receiver and eliminating potentialproblems such as harmonic pulling that arise between multipleVCOs on a chip.

The RF input comprising many bands is amplified bya common-wideband LNA and then down-converted in acommon mixer. At the output of the mixer, the wanted bandcentered at 0 Hz is low-pass filtered to attenuate adjacentchannels, followed by variable gain amplification and A/D con-version. The RF SAW prefilter eliminates strong out-of-bandinterferers in cellular PCS bands. A notch in the 5-GHz NIIbands may be necessary to relax receiver dynamic range.

The many channels at the input of the receive chain forceuse of an RF front end with low gain compared for instanceto the front-end of a narrowband GSM receiver, where thereare only one or two close-in interferers. Therefore, the channel-

Fig. 4. Block diagram of the fabricated receiver chip.

select filter which follows the mixer should have a very lowinput-referred noise, which in an active filter means high currentconsumption. We show that in this instance when the passbandis 264 MHz wide, a passive LC low-pass filter is feasible. Thiswould not be practical in a narrowband receiver, where the filtercomponents would be so large as to totally dominate the chip.

Unless an extraordinarily high reference frequency isused with the concomitant high power dissipation, no usualphase-locked loop (PLL) can be sufficiently wideband to en-able frequency hopping and settling in less than 9 ns. Instead,seven discrete LO frequencies obeying the simple relation-ship MHz, can be obtained from theclassic direct frequency synthesizer [7]. This synthesizes allthe required frequencies at once with a combination of a singlefixed-frequency oscillator, frequency dividers, and single-side-band (SSB) mixers or bandpass filters. Frequency tuning is thena matter of selecting the desired frequency with a switch, andhop time is limited only by the settling of parasitic capacitanceat the switch output.

Direct frequency synthesis invokes its own challenges in de-sign and implementation that are sufficiently important and un-familiar to the general reader to deserve a section of their own.

III. DIRECT FREQUENCY SYNTHESIZER

Any zero-IF receiver needs quadrature phases at every LOfrequency. A direct frequency synthesizer could generate asingle phase at every frequency, from which balanced quadra-ture phases could be derived using a passive RC polyphasefilter [8]. However, this is not practical here because multiplepolyphase filters are required to cover the very wide frequencyband, and at these high frequencies, the parasitic capacitancesof the resistors are likely to induce unacceptable errors inquadrature. A reliable way to create quadrature is by restrictingall frequency division in the synthesizer to emitter-coupledlogic (ECL) divide-by-2s, which inherently produce balancedquadrature outputs. In fact, starting from a nonquadratureinput, exact quadrature can be obtained after two stages ofdivide-by-2.

The main question is: What is the lowest frequency oscillatorthat can deliver all seven LO frequencies if only divide-by-2 cir-cuits are combined with the fewest possible SSB mixers to addor subtract frequencies? The ILOG CPLEX software was usedto solve this integer programming problem. It was found thatthe lowest fixed oscillator frequency required is 16.896 GHz,and Table I gives the plan of division and frequency addition or

ISMAIL AND ABIDI: A 3.1- TO 8.2-GHZ ZERO-IF RECEIVER AND DIRECT FREQUENCY SYNTHESIZER 2575

TABLE IPLAN OF HARDWARE-OPTIMUM DIRECT FREQUENCY SYNTHESIZER.

FRACTIONS SHOW FREQUENCY DIVISION AFTER SSB MIXING

subtraction given by the optimizer. Let us consider an exampleto understand this table. To generate 3.96 GHz (f2), the oscil-lator frequency is divided by 4 and by 32, then the two dividedoutputs are combined in an SSB mixer that selects the differ-ence frequency, and the mixer’s output is again divided by 2(this is what the table entry 0.5 means). Rows with three entriesmean that two SSB mixers are required. As these are linear com-binations, the operations are commutative and order does notmatter. From Table I, we can see that to synthesize all seven fre-quencies needs six divide-by-2s, two SSB mixers, and a switcharrangement.

Although this is optimum in the sense of using the leasthardware, the pattern of spurs associated with this frequencyplan must be investigated. In the circuit of Fig. 5, imperfectionsin SSB mixers that, together with VCO and divider imper-fections, create spurs in the frequency synthesizer’s outputspectrum. In PLL-based frequency synthesizers by contrast, asingle VCO is steered to the frequency of interest, and spursonly arise from well-understood loop imperfections such asreference feedthrough. In narrowband receivers, a high ref-erence frequency and fractional- synthesis can push thesespurs far away so that they do not down-convert adjacent strongchannels.

Unless the frequency plan is chosen carefully, the spurs in adirect frequency synthesizer can be in-band and large, raisingthe likelihood that they will down-convert adjacent bands ontothe desired band to create cochannel interference. The followingconsiderations guide the choice of a good frequency plan.

1) The sum or difference between frequencies should be cre-ated at high frequencies; that is, the entries in Table Ishould lie, as much as possible, in columns to the left.Spurs that arise will thus be positioned far away, as ex-plained below.

2) The table entries should be small; that is, division shouldtake place, as much as possible, after SSB mixing. Thislowers spur levels, as explained in Appendix I.

There can be many sources of spurs, but when SSB mixers areinvolved, they arise from gain imbalance in the two branches,quadrature inaccuracy and DC offsets. Residual tones appear atthe unwanted sideband and leakage spurs at one or both inputfrequencies. In analyzing a mixer used in the frequency synthe-sizer, we should bear in mind that both its inputs are large am-plitude, unlike the receive mixer whose one input is very small

Fig. 5. Details of components in frequency synthesizer and their connections.Phase error in QVCO, and gain mismatches in SSB mixer cause sidebandleakage at SSB output.

and the other is large. When driven by large inputs, the double-balanced mixer is indistinguishable from an ECL XOR gate.

Gain imbalance between two mixers arises mainly from mis-matched tail currents (Fig. 11). Also, phase inaccuracy in thequadrature VCO (QVCO) arises from mismatched tail currentsas well (details in Section IV). Offset arises from any sourcethat upsets the 50% duty cycle of the commutating and commu-tated waveforms in the mixer. The large output amplitude of theVCO tapped across an inductor (offset-free) will easily over-whelm the few millivolt offset of a bipolar junction transistor(BJT) differential pair, and in the following divider chain thesquare waveforms will easily preserve a 50% duty cycle, evenwith offsets of a few millivolts in the differential pair. There-fore, we expect DC offset to be a small problem, and we willassume that quadrature error and gain imbalance contribute al-most equally to the unwanted sideband.

Let us take the example from Table I of synthesizing4.488 GHz. This involves an SSB mixer that selects the sumfrequency 8.448 0.528 GHz which is then divided by 2. How-ever, due to the errors described above, there also appears atthe mixer output a spur at 8.448 0.528 GHz that is 1.056 GHzaway from the wanted frequency. The wanted sum frequencyand the unwanted spur at the difference frequency are nowdivided by 2. As shown in Appendix I, division by 2 resultsin a main tone at 4.488 GHz, accompanied by two spurs at adistance of 1.056 GHz. The spur separation is unchangedbut division lowers the spur amplitude by 2 (6 dB). The spur

2576 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

TABLE IIPLAN OF REALIZED FREQUENCY SYNTHESIZER. ONE SPUR FALLS

BETWEEN TWO UWB CHANNELS, ALL OTHERS ARE FAR AWAY

at the difference frequency lies at 3.432 GHz, at the centerof channel 1. Similarly, synthesizing 3.432 GHz results in aspur at 4.488 GHz, which is the center of channel 3. This isundesirable. Ideally, none of the synthesizer spurs should fallin-band; preferably, they should all lie out of band, or at worstin between channels.

Table II shows the frequency plan of the synthesizer imple-mented in this paper. In this revised plan, nonzero coefficientsthat are involved in SSB mixing are pushed into columns tothe left. The coefficient size is scaled down to obtain the samefinal frequency. This is good, because for every division by 2after mixing, the spur levels go down by 6 dB. However, thiscannot be done for every synthesized frequency: three of theseven frequencies follow the same plan as in Table I. The anal-ysis shows that now no spur falls in the center of other chan-nels. In fact, there is only one spur that lies in the UWB bandat 6.6 GHz arising from the synthesis of 4.488 GHz. This, how-ever, lies exactly in the middle of two adjacent channels wherethe signal spectral energy is at a minimum. Also, it is suppressedby 12 dB because of two divide-by-2s after the mixer. Synthesisof 6.864 GHz gives rise to a spur at 6.864 GHz, whose ef-fect is to add a small amount of the mirror image spectrum ofthe channel of interest to itself. However, this spur experiencesthree divide-by-2s after the mixer, which suppress it by 18 dBrelative to the wanted tone. In this frequency plan, the closestother spur is at least 2.1 GHz away, which is twice the distancecompared to the plan in Table I.

The direct frequency synthesizer implementing Table II usestwo more dividers than the hardware-optimal Table I. This is asmall price to pay for more acceptable spurs.

In Tables I and II, spurs fall in the 5-GHz NII band. The RFpreselect filter must notch the NII band to prevent receiver over-load and false down-conversion by spurs.

The frequency synthesizer (Fig. 6) uses switched buffers asmultiplexers. Every one of the multiple inputs to the buffersproduces a legitimate LO frequency at the synthesizer output.However, all except one of the inputs must be switched off atany given time. The buffer should isolate the disconnected in-puts sufficiently to prevent spurs at unwanted channel frequen-cies from appearing at the output.

All quadrature phases are directly available via a divide-by-2.As mixer M1 produces a constant output frequency, the coupledGilbert cells drive an LC resonator tuned at that frequency tolower spurs. Mixer M2 produces a variable frequency output soits load is an LCR bandpass filter.

Fig. 6. Direct frequency synthesizer creating the seven carrier frequencies.

IV. RF AND IF CIRCUITS

A. Wideband LNA

The wideband LNA (Fig. 7) consists of an inductively de-generated common-emitter amplifier stage. Wideband inputimpedance matching is achieved by embedding the inductivelydegenerated LNA into an LC ladder filter [5]. The amplifierin [9] is used here to obtain a sub-3-dB noise figure from3 to 8 GHz and voltage gain of 21 dB at 10 mA. When cascadedwith the mixer, the coupling capacitor is chosen to lower thecapacitive loading on the LNA of the mixer input capacitance(400 fF). This capacitive division results in 5 dB loss.

A current steering transistor shunts the common-base cas-code transistor to step down the LNA gain by 15 dB. The gainstep does not disturb the input impedance matching. A low-frequency loop via an opamp eliminates the need of a currentmirror and maintains constant LNA transconductance for accu-rate input impedance matching. A further advantage is that thelow impedance to ground at the transistor base shunts any lowfrequency base current modulation at beat frequencies betweenblockers [9]. A large resistor and a moderate capacitancefilter out low frequency noise in the bias circuit; in the presenceof strong blockers, this noise can fold on top of the signal fre-quency to degrade noise figure.

B. Down-Conversion Mixer and Channel-Select Filter

Transconductor nonlinearity, switch nonlinearity, andRF-to-LO coupling degrade the IP2 and IP3 of the down-con-

ISMAIL AND ABIDI: A 3.1- TO 8.2-GHZ ZERO-IF RECEIVER AND DIRECT FREQUENCY SYNTHESIZER 2577

Fig. 7. Wideband LNA circuit.

Fig. 8. Down-conversion mixer/channel-select filter.

version mixer [10], [11]. To meet the specifications for overallreceiver nonlinearity, these mixer characteristics impose anupper limit on LNA gain. The single-ended LNA is followedby a single-balanced mixer (Fig. 8). To improve mixer linearityuniformly across the band, we use a resistively degeneratedtransistor as the RF transconductor. A low-frequency loop (notshown in Fig. 8) senses the common-mode voltage at the mixeroutput to set the bias current. IM2 terms due to narrowbandinterferers appear around DC as bias modulations and aresuppressed by this loop.

The mixer load resistance is low enough that it can terminatean on-chip passive ladder channel-select filter realized with Lsand Cs of reasonable values [12], as shown in Fig. 8. This is afifth-order elliptic low-pass filter. Conventional wisdom holdsthat high-order on-chip passive realizations of baseband filters

Fig. 9. VGA circuit.

are too wasteful of area, but with 264-MHz cutoff, the compo-nents are physically small. Inductors dominate the area and arefabricated on the 8- cm substrate as series-stacked spirals in3- m-thick metal-5 and 1.5- m-thick metal-4. Grounded 6-pFcapacitors shunt the LO feedthrough present in every single-bal-anced mixer as well as common-mode LO harmonics that wouldotherwise degrade mixer linearity.

C. Baseband VGA

As the filter demonstrates, even baseband circuits in a UWBreceiver are wideband by usual standards. The VGA circuitshown in Fig. 9 has a bandwidth of 300 MHz and uses a Gilbertmultiplier cell with the control voltage applied to the upperdifferential pairs. Capacitive coupling of the filter output formsa lower cut-off frequency of 5 kHz. Emitter followers bufferthe output of the VGA to drive the output pads. The differentialvoltage is generated by a translinear circuit toobtain a dB-linear gain characteristic versus control voltage.The VGA achieves a peak gain of 35 dB and a gain range of29 dB. As the filter has already attenuated out-of-band signals,the linearity of the VGA is relaxed substantially and need onlybe enough to handle the dynamic range of an OFDM waveform.The circuit draws 1.6 mA.

The DC offset at the output of the mixer resulting from mis-matches and LO self-mixing is small enough not to affect outputvoltage headroom. The high-pass section notches out only thestatic offset at DC, while dynamic offset that appears as fixed-pattern noise at the repetition rate of the hopping pattern passesthrough and must be dealt with by other means.

D. Quadrature VCO

The VCO shown in Fig. 10 consists of two coupled oscil-lator cores with fully integrated LC resonators. Each resonanttank consists of two 120 pH integrated spiral inductors and twop-n junction varactors, each laid out as six fingers of 20 m1.4 m. The VCO tail current sources are carefully laid out forgood matching, as this mainly determines quadrature accuracy.Special attention should be given to the layout of the tail cur-rent transistors and resistors to improve physical matching. Par-asitic inductances of interconnects were very carefully modeled

2578 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 10. Quadrature VCO circuit.

Fig. 11. SSB mixer (MX2) circuit (only one mixer core is shown).

as part of the tank. To further improve phase accuracy, the cou-pling current was chosen as large as the bias current andequals 5 mA. The QVCO draws 20 mA.

E. Mixers in Frequency Synthesizer

The SSB mixer used in the frequency synthesizer consistsof two Gilbert multiplier-based mixer cores whose outputs areadded together as currents. Fig. 11 shows the simplified circuitschematic of one mixer.

Spurs appear at the output of the SSB mixers in two differentways. First, and most significant, is the mismatch between tailcurrents in the and mixers. The tail current in a mixer drivenas an ECL XOR gate sets the amplitude of the binary output,thus mixer gain. This has been discussed in an earlier section.However, spurs will also appear because of currents flowingin the mixer circuit’s capacitances at unwanted, or unexpected,frequencies.

Appendix II contains the spurs analysis for an SSB mixer,taking into account commutation harmonics and currents

Fig. 12. Digitally controlled switched buffers used to change the carrierfrequency.

flowing in parasitic capacitances. Although some capacitivecurrent is always present in every mixer, in this case theyare large because of the high frequencies involved (8 GHz inmixer MX1 and 16 GHz in MX2). The analysis suggests apreferred way to drive the mixer. As capacitive current riseswith frequency, the higher of the two input frequencies shouldbe applied to the upper differential pairs where it creates equalcurrents in the two matched tail capacitances; after commuta-tion these currents appear at the output as common mode. Thelesser input frequency induces a smaller capacitive current, andtherefore a lower spur at the unwanted sideband.

F. Switched Buffers and Frequency Dividers

The switched buffer multiplexer consists of multiple differ-ential pairs that share a common load, whose tail current is ac-tivated one at a time with switches (Fig. 12). The differentialsignals to be switch selected are applied to each pair, and MOSswitches activate one selected pair. As mentioned previously,pairs that are off must isolate the continuously present inputsignal from the common output, otherwise signal leakage willcreate a small tone at exactly an LO frequency that selects someother channel. Cascode BJTs improve isolation from the inputsto the outputs by 15 dB. In simulation, a differential pair bufferthat is switched off isolates the input by 70 dB. Spurs as low as

70 dBc are acceptable.The time required for the output amplitude to settle in re-

sponse to a step switchover from one pair to another determineshow quickly the LO frequency can hop. Measurements showthat this is as short as a few nanoseconds, limited by the RC set-tling time at the common load and the collector capacitances offour differential pairs in parallel.

Fig. 13 shows the highest frequency divide-by-2 circuit thatclocks at 16 GHz. Two identical circuits driven by reversedclock phases create balanced outputs in quadrature at the dividedfrequency (Fig. 5). The outputs are capacitively coupled to theinput of the next divider.

ISMAIL AND ABIDI: A 3.1- TO 8.2-GHZ ZERO-IF RECEIVER AND DIRECT FREQUENCY SYNTHESIZER 2579

Fig. 13. 16-GHz divide-by-2 circuit.

Fig. 14. Die microphotograph of the complete receiver chip.

V. EXPERIMENTAL RESULTS

A receiver prototype is fabricated in a 0.18- m SiGeBiCMOS (Jazz Semiconductor). The chip consumes an area of2 3.5 mm of which the VCO and LO generator take almosthalf (Fig. 14). All the on-chip spiral inductors in the VCO andthe SSB mixers, as shown in Fig. 15, are wound in the samedirection to suppress the conversion of common-mode straymagnetic fields into undesired differential signals.

The input was contacted with Picoprobe G-S-G RF probe anda multicontact wedge containing 12 probes for biasing, digitalcontrol words, and baseband outputs.

Maximum receiver gain is 52 dB with only 0.7-dB rippleacross all UWB channels (Table III). The cascade noise figureis 3.3 dB at 3.1 GHz, rising to 4.1 dB at 8 GHz. When themaximum single-tone blocker of 10 dBm is present, the cas-cade noise figure degrades by only 0.5 dB at 3.4 GHz. Fig. 16shows input measured and simulated , which remains below

10 dB from 2.2 to 8 GHz.To verify the frequency settling, the LO output waveform

across the largest hop was captured in the time domain usingan Agilent Infinium 54855A oscilloscope (Fig. 17). The LOfrequency switches from 4488 to 6336 MHz in 3 ns, which is wellwithin the 9-ns channel switch time specified in the MB-OFDMproposal. Fig. 18 shows the receiver’s frequency response, de-termined by the channel-select filter. Fig. 19 shows the measured

Fig. 15. Die microphotograph showing the winding of the spiral inductors atthe output of one of the SSB mixers.

TABLE IIISUMMARY OF MEASUREMENTS

Fig. 16. Measured S versus frequency at the input of the wideband LNA.

versus simulated LO phase noise at 3960 MHz. Fig. 20 shows themeasured spectrum of the frequency synthesizer when channelno. 3 (4488 MHz) is selected. The spurs are 2.112 GHz away

2580 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 17. Measured output frequency synthesizer in the time domain capturedon digitizing oscilloscope, showing the frequency switching from 4488 to6336 MHz. Parasitic AM due to single-ended buffer.

Fig. 18. Measured versus simulated normalized frequency response of thecascaded receive chain.

Fig. 19. Measured versus simulated phase of the output of the frequencysynthesizer when channel no. 2 (3960 MHz) is selected.

from the carrier, confirming the calculations in Table II. The spurlevel at all seven synthesized frequencies is less than 40 dBc.

The analysis in Appendixes I and II is used to work backwardto deduce what gain and phase mismatch in the SSB mixer mightbe responsible for the measured spurs. If we assume that both ofthese sources of error are uncorrelated and contribute equally,then the gain error (rms) is about 11% and the quadrature phaseerror (rms) is about 6 . These are larger than what was expected,and it was discovered later that element matching was muchpoorer than what it should be on this newly developed IC process.

Overall gain is measured with a down-converted tone at250 MHz. The cascaded gain changes by about 29 dB whenthe VGA control voltage is swept from 0.5 to 2.5 V, as shownin Fig. 21. Together with the 15-dB gain step in the LNA, theoverall gain control range is 44 dB. The output DC offset is also

Fig. 20. Measured spectrum of the output of frequency synthesizer whenchannel no. 3 (4488 MHz) is selected.

Fig. 21. Measured VGA control range when the gain control voltage is sweptfrom 0.5 to 2.5 V.

Fig. 22. Measured standard deviation of the output DC offset when the gaincontrol voltage is swept from 0.5 to 2.5 V.

measured as the VGA gain is swept. Fig. 22 plots the standarddeviation of offset across seven different chips over the gaincontrol range. Table III summarizes key receiver characteristics.It should be noted that the and imbalance in this table is thefinal value in receive path down-conversion mixers, after im-provements in quadrature phase and amplitude balance accruingfrom multiple divisions-by-2 in the frequency synthesizer.

VI. CONCLUSION

A fully integrated direct conversion receiver for MB-OFDMsystems has been implemented in 0.18- m SiGe process. Thecircuit employs a common-wideband LNA, down-conversionmixer, band select filter, and VGA. The frequency synthesizeruses a 16-GHz VCO to generate the seven carrier frequenciesrequired by mode-2 devices. Table III summarizes receiver

ISMAIL AND ABIDI: A 3.1- TO 8.2-GHZ ZERO-IF RECEIVER AND DIRECT FREQUENCY SYNTHESIZER 2581

Fig. 23. Decomposing a spur into equivalent AM and PM sidebands.

performance. What is notable is the uniformity of noise figureand linearity across a very wide band. Operating from a 2.7-Vsupply, the receive signal path consumes a total of 22 mA, thequadrature VCO consumes 20 mA, and the remaining LO gen-erator blocks consume 46 mA. This design approach enabled ahighly integrated solution to the emerging MB-OFDM UWBtechnology with a low-power consumption.

APPENDIX ISPURS AFTER DIVISION-BY-2 IN FREQUENCY

In Fig. 23, consider two tones at and applied to theclock input of a D-flip-flop, which is part of a frequency di-vide-by-2 circuit. We assume that is the frequency of in-terest and is an unwanted spur of small relative amplitude

. Using linear superposition, the single tonecan be decomposed into equal amplitude modulation (AM) andphase modulation (PM) sidebands, each of amplitude , sym-metrically disposed around at frequencies .

Now, the flip-flop is a limiting regenerative circuit that is sen-sitive only to the threshold crossing of the input (we assumethe differential threshold is zero), but does not respond to fluc-tuations in input amplitude. Therefore, the flip-flop only reactsto the input PM sidebands. While superposition does not applyin the flip-flop to voltage levels, it does apply to AM and PM,which in some sense are orthogonal to one another.

The flip-flop output toggles whenever the differential clockinput crosses zero with, say, positive slope. This is most clearlyseen in the time-domain input and output waveforms (Fig. 24).The output waveform tracks every other zero crossing of theinput, thus also its deviations in time. However, relative to theoutput frequency, of , this corresponds to half the deviationin phase. Thus, the relative level of the output PM sidebands ishalf, that is, . However, the rate or relative frequency of PM re-mainsunchanged.Thus, thesidebandsare locatedat .

In summary, when large and small tones are applied to theinput of a divide-by-2, the large tone is divided and and for eachsmall input tone is surrounded by two output spurs that are sym-metrically disposed around the large tone at the same frequencyoffset as the single input spur but at ( 12 dB) the inputspur’s relative amplitude. Further frequency division-by-2 pre-serves the spur separation but lowers the relative levels by 6 dB.

In an SSB mixer followed by frequency division, gain mis-match in the and mixers and errors from quadrature phases

Fig. 24. Voltage waveforms at the output of a divide-by-2 circuit when aphase-modulated signal is applied to its input.

createa small unwantedsideband, which appears like aspur to thewanted sideband. This is the input to the divider. The precedinganalysis tells us what appears at the output of the divider.

APPENDIX IISPURS AT SSB MIXER DUE TO PARASITIC CAPACITANCES

At input frequencies as high as 16 GHz, currents flowing in themixer’sparasiticcapacitances thatarenormallyneglectedcanbe-come important. Let us take a look at the currents in the capaci-tances to ground at the coupled emitters of each differential pairin the double balanced mixer (Fig. 25). At high frequencies, theinput voltage waveforms resemble large sinusoids at frequencies

and . For input amplitudes larger than mV, thecommon emitter voltage is a full-wave rectified version of the dif-ferential input at a fundamental frequency of and , andsmall harmonics. This induces capacitive currents to ground.

To the capacitive current at its tail, the lower differential pairacts like a single-balanced mixer, producing a differential outputcurrent at the sum and difference with its input frequency. Onthe other hand, in the upper cross-coupled differential pairs, thecapacitive currents are the same at both tail nodes, and after com-mutation and cross-coupling they produce only a common-moderesponse. In short, only the currents in the lower differentialpair’s tail capacitance induce a differential output at the mixer.

Consider the lower differential pairs in each of the twomixers connected in an SSB arrangement. Suppose theirtail capacitance is and the differential input to one is

and to the other it is . The currents inducedin the tail capacitances after rectification are proportional to

and . Commutationby the differential pair’s input produces a difference frequencywaveform proportional to , which is the samein both mixers. Let us remind ourselves that in the absenceof significant capacitive currents, the only commutation in adouble balanced mixer is that of the differential current in thelower pair by the differential voltage driving the upper pair.Here we are describing a commutation of capacitive currentsby the input voltage at the lower pair followed by a secondcommutation by the input voltages at the upper pair.

2582 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Fig. 25. Parasitic capacitances in the SSB mixer result in a spur at the undesired sideband.

Suppose the upper pairs in the two mixers are switched bydifferential waveforms and and the commutatedcurrents are added to select one sideband—it does not matterwhich one, as we shall see. Then the differential capacitive cur-rent emerging from the lower pairs is commutated by the upperpairs and added to produce

The capacitive currents thus produce equal outputs at bothsidebands, the desired as well as the unwanted. The undesiredsideband is a spur arising from tail capacitance.

ACKNOWLEDGMENT

The authors thank Julan Hsu of UCLA for the use of ILOGCPLEX, and Prof. Lieven Vanderberghe for advice.

REFERENCES

[1] A. Batra, J. Balakrishnan, G. R. Aiello, J. R. Foester, and A. Dabak,“Design of a multiband OFDM system for realistic UWB channelenvironments,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, pp.2123–2138, Sep. 2004.

[2] S. Roy, J. R. Foerster, V. S. Somayazulu, and D. G. Leeper, “Ultraw-ideband radio design: The promise of high-speed, short-range wirelessconnectivity,” Proc. IEEE, vol. 92, no. 2, pp. 295–311, Feb. 2004.

[3] M. Hamalainen, V. Hovinen, R. Tesi, J. Iinatti, and M. Latva-aho, “On theUWB system coexistence with GSM900, UMTS/WCDMA, and GPS,”IEEE J. Sel. Areas Commun., vol. 20, no. 9, pp. 1712–1721, Dec. 2002.

[4] A. Bellomo, “Gain and noise considerations in RF feedback amplifier,”IEEE J. Solid-State Circuits, vol. 3, no. 3, pp. 290–294, Sep. 1968.

[5] R. Magoon, A. Molnar, J. Zachan, G. Hatcher, and W. Rhee, “Asingle-chip quad-band (850/900/1800/1900 MHz) direct conversionGSM/GPRS RF transceiver with integrated VCOs and fractional-N syn-thesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1710–1720,Dec. 2002.

[6] B. Razavi, T. Aytur, F.-R. Yang, R.-H. Yan, H.-C. Kang, C.-C. Hsu, andC.-C. Lee, “A 0.13�mCMOS UWB transceiver,” in IEEE Int. Solid-StateCircuits Conf. Dig. Tech. Papers, San Francisco, CA, 2005, pp. 216–217.

[7] J. Smith, Modern Communication Systems. New York: McGraw-Hill,1986.

[8] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixersand polyphase filters for large image rejection,” IEEE J. Solid-State Cir-cuits, vol. 36, no. 6, pp. 873–887, Jun. 2000.

[9] A. Ismail and A. Abidi, “A 3–10 GHz LNA with wideband LC laddermatching network,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.Papers, San Francisco, CA, Feb. 2004, pp. 384–385.

[10] A. Abidi, “General relations between IP2, IP3, and offsets in differentialcircuits and the effect of feedback,” IEEE Trans. Microw. Theory Tech.,vol. 51, no. 5, pp. 1610–1612, May 2003.

[11] D. Manstretta, M. Brandolini, and F. Svelto, “Second-order intermodu-lation mechanisms in CMOS downconverters,” IEEE J. Solid-State Cir-cuits, vol. 38, no. 3, pp. 394–406, Mar. 2003.

[12] H. J. Orchard, “Loss sensitivities in singly and doubly terminated filters,”IEEE Trans. Circuits Syst., vol. 26, no. 5, pp. 293–297, May 1979.

Aly Ismail received the B.Sc. (with honors) and M.S.degrees in electrical engineering from Cairo Univer-sity, Giza, Egypt, in 1998 and 2000, respectively, andis currently working toward the Ph.D. degree in elec-trical engineering at the University of California atLos Angeles (UCLA).

He joined the Integrated Circuits and Systems Lab-oratory, UCLA, as a Research Assistant in 2000. In2002, he joined Conexant Systems, Newport Beach,CA, where he worked on designing RF integrated cir-cuits for cellular systems. From 2002 to 2005, he was

with Skyworks Solutions, Irvine, CA. He is currently with Newport Media,Lake Forest, CA. He holds several U.S. and international patents in the area ofRF/analog integrated circuits. His research interests include RF and analog/dataconverters/mixed-signal circuit design for wireless systems.

Mr. Ismail received the Analog Devices Inc. (ADI) Outstanding Student De-signer Award in 2003.

Asad A. Abidi (S’75–M’80–SM’95–F’96) receivedthe B.Sc. (with honors) degree from the ImperialCollege, London, U.K., in 1976, and the M.S. andPh.D. degrees in electrical engineering from theUniversity of California, Berkeley, CA, in 1978 and1981, respectively.

From 1981 to 1984, he was with Bell Laboratories,Murray Hill, NJ, as a Member of Technical Staff atthe Advanced LSI Development Laboratory. Since1985, he has been with the Electrical EngineeringDepartment, University of California, Los Angeles

(UCLA), where he is a Professor. He was a Visiting Faculty Researcher atHewlett Packard Laboratories in 1989. His research interests are in CMOS RFdesign, data high-speed analog integrated circuit design, conversion, and othertechniques of analog signal processing.

Dr. Abidi was the Program Secretary for the IEEE International Solid-StateCircuits Conference (ISSCC) from 1984 to 1990, and the General Chairman ofthe Symposium on VLSI Circuits in 1992. He was the Secretary of the IEEESolid-State Circuits Council from 1990 to 1991. From 1992 to 1995, he wasthe Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He has received anIEEE Millennium Medal, the 1988 TRW Award for Innovative Teaching, andthe 1997 IEEE Donald G. Fink Award. He was a corecipient of the Best PaperAward at the 1995 European Solid-State Circuits Conference, the Jack KilbyBest Student Paper Award at the 1996 IEEE ISSCC, the Jack Raper Award forOutstanding Technology Directions Paper at the 1997 ISSCC, and the DesignContest Award at the 1998 Design Automation Conference, and received anHonorable Mention at the 2000 Design Automation Conference.