A 1V 14b Self-Timed Zero-Crossing-Based Incremental ΔΣ ADC[1]Class Presentation for Custom Implementation of DSP By Parinaz NaseriSpring 2013

1

ADC Architectures[4]

2

ΔΣ ADC Basics

• Over Sampling

• Quantization Noise Shaping

• Digital Filtering

• Decimation

3

Why Over Sampling?

• Choosing a higher sampling rate, or oversampling, relaxes the requirement on the sharpness of the transition band (hence, the complexity of it) at the expense of using a faster ADC. [2]

• Resolution can be improved with oversampling, however, we must over-sample by a factor of 2^2N in order to obtain a increase in resolution of N-bits.[2]

• When the sampling frequency is doubled, the signal to quantization noise is improved by 10log((2^2N)+1) dB for N-order ΔΣ-modulator.[3]

4

Noise Shaping &

Decimation• The ∑∆ modulator shapes the

quantization noise so that it lies above the passband of the digital output filter. Therefore, the ENOB is much larger than just using oversampling.[2]

• The output data rate can be reduced lower than the original over sampling rate because the bandwidth of the digital LPF on the output. The slower data rate is achieved by a process called decimation by a factor of M. This process passes every Mth bit to the output, while discarding the remainder.[2]

5

Effects of over sampling & digital filter & noise shaping & decimation[2]

First Order Sigma-delta ADC[2]

6

Incremental ΔΣ-ADC

Classical ∆Σ structures are not well suited for instrumentation and measurement (I&M) applications, in which very high absolute accuracy and linearity, and very low offset and gain errors are required, in addition to high dynamic range and signal-to-noise ratio. Incremental data converters (IDCs) which can be considered delta-sigma data converters in transient mode, are well matched to the requirements of I&M. They can provide precise high-resolution conversion with low offset and gain errors.[5]

7

Discrete-time model of a first-order bipolar incremental converter.[5]

Advantages of Asynchronous ADCs

An N bit synchronous SAR ADC which has a conversion rate of M samples/second generally needs a clock of at least (N + 1) M Hz.[6]∗Design of an asynchronous ADC which takes advantage of faster comparison cycles to perform the conversion. With clock requirement equal to the sampling rate (unlike synchronous SARs), its area and power consumption scale linearly with resolution.[6]

8

A 1V 14b Self-Timed Zero-Crossing-Based Incremental ΔΣ ADC[1]

This paper introduces a clock-free self-timed incremental ΔΣ ADC. Unlike conventional ΔΣ ADCs, it does not require a dedicated clock signal, thus saving energy and reducing system complexity. In contrast with asynchronous ΔΣ modulators, which also operate without a clock, the ΔΣ ADC described in this paper employs a discrete-time switched-capacitor loop filter and a clocked comparator, albeit self-timed, and therefore has the same noise-shaping characteristics as a conventional discrete-time

incremental ΔΣ ADC. The loop filter’s integrators employ gated current sources (GCSs) to transfer charge from their input capacitors to the integration capacitors. Like in prior zero-crossing-based designs, this charge transfer continues until the virtual-ground condition is detected by a zero-crossing detector (ZCD).[1]

9

Self-Timed Incremental ΔΣ ADC[1]

10

A 1V 14b Self-Timed Zero-Crossing-Based

Incremental ΔΣ ADC[1]A block diagram of the self-timed ADC is shown in Fig. 15.4.1. It consists of a 2nd-order switched-capacitor ΔΣ modulator controlled by an asynchronous state machine.

A conversion is initiated by an external startup signal, after which the controller generates a pair of non-overlapping clock signals φ1 and φ2 that alternately switch the integrators between sampling and charge-transfer phases. In each integrator, charge transfer is accomplished by a gated current source (GCS) until a virtual-ground condition is detected at node Vx1,2 by a ZCD. At that moment, the state machine proceeds to the next phase. Thus, the duration of clock phases φ2 (state A) and φ1 (state B) is determined by the charge-transfer time in the first and second integrator, respectively.[1]

11

Implementation details of the ZCD and the GCS and the associated timing diagram

ZCD & GCs Implementation details[1]

Timing Diagram[1]

12

Conclusion

Figure 15.4.6 summarizes the performance of the self-timed ΔΣ ADC. Its energy efficiency is comparable with the best (non-self-timed) ΔΣ modulators employing comparable zero-crossing-based circuits, while it

achieves a higher linearity.[1]

13

References

[1] Ch. Chen, Zh. Tan and M. A. P. Pertijs, ” A 1V 14b Self-Timed Zero-Crossing-Based

Incremental ΔΣ ADC,” ISSCC Dig. Tech. Papers, pp. 274-275, Feb. 2013.

[2] www.testedgeinc.com/docs/sigma_delta_adc.pdf

[3] http://en.wikipedia.org/wiki/Delta-sigma_modulation

[4] S. Louwsma, Successive Approximation ADCs, Bits and Chips Hardware Conference. Jun. 2010.

[5] J. M´arkus, Ph. Deval, V. Quiquempoix, J. Silva, and G. C. Temes, “Incremental Delta-Sigma Structures for DC Measurement,” CICC. Papers, 2006

[6] Th. Tulabandhula and Y. Mitikiri, “A 20MS/s 5.6 mW 6b asynchronous ADC in 0.6µm CMOS,” 22nd International Conference on VLSI Design Papers, 2009

14