VHDL-AMS Simulation of RF Mixed-Signal Communication Systems

Erik C. Normark

MSCAD Lab

Data Source

System

Delay

Counter, BER math

AWGN Level

Q

I

Outline

• Background and Motivation– Design of Mixed-Signal Systems– VHDL-AMS Basics– Design Tools

• Simple BPSK Model– System Design– Simulation Results

• π/4 DQPSK Model– Basic System Design– Design with Viterbi Encoding

• Summary and Conclusions

Design of Mixed Signal Systems

• Increasing demand for System-On-Chip – RF, analog, digital circuits all on one chip – Fast time-to-market issues

• Less established analog automated design process• Bottom-up design approach common• VHDL-AMS promotes multiple abstraction layers

– facilitates mixed design approach– Behavioral model refined until physical transistor-level

implementation reached– Promotes re-use of architectural code

Motivation

• Create a mixed-signal, system-level model of a high-frequency transceiver in VHDL-AMS

• Ability to measure system performanceThrough Bit-error-rate (BER) analysis

• Compare results of VHDL-AMS simulations with other available mixed-signal modeling environments.

VHDL-AMS Language Basics

• Extension of VHDL standard• Adds support for DAE’s and conservative

quantities• Supports description and simulation of analog,

digital, mixed signal, multi-physics devices• Encourages device modeling at various

architecture levels (ideal, non-linear, transistor)

Design Tools

• ADVance-MS (ADMS)– Compiler and simulator for VHDL, VHDL-

AMS, Verilog, Verilog-A, SPICE, C– Supports most of VHDL-AMS standard

• No support for file I/O, Procedural, frequency-domain noise

• Agilent ADS– Commercial RF design environment for

system-level design modeling and simulation

BPSK System

• Evaluate system performance via comparison to theoretical BER calculation

• Ideal System Architecture– Transmitter– Noisy Channel– Receiver– BER Calculation

Data Source(Random

Data)

Modulator(p /4 DQPSK)

Propagation Channel (AWGN)

Demodulator(p /4 DQPSK)

2.4GHZ

How Ideal?

• Oscillator:V==10**(A/20.0)*cos(math_2_pi*f*now + Ph);

• PA and LNA:vo == vi*10**(gain/20.0);

• Mixer:vout==v1 * v2;

BPSK : Transmitter

• Modulate data by shifting phase of oscillator between ±180o

500 MHz Uniform Random

Data

Std_logic to bi-polar(‘1’ -> +1V, ‘0’ -> -1V)

2.4GHZ

Power Amplifier

BPSK Transmitted Spectrum

BPSK : Propagation Channel

• Basic channel with variable Additive White Gaussian Noise Power

• Can expand this architecture to include delay spread

• Box-Muller transformation of two uniform, independent random variables

AWGNAnoise

A1, t 1 +

WGN Generator Process

noise_calc : process (noise_s) variable s1 : positive := seed1; variable s2 : positive := seed2; variable x1,x2 : real; -- Uniform random variables begin UNIFORM(s1,s2,x1); -- create two uniform variables UNIFORM(s1,s2,x2); -- create Gaussian variable using Box-Muller method noise_s <= SQRT(-2.0*LOG(x1))*COS(2.0*MATH_PI*x2)

after rate;end process noise_calc;

vo == 10.0**(level/20.0)*noise_s;

AWGN Testing

BPSK : Received Spectrum

BPSK : Receiver

• Normally Requires coherent detection

• Uses original oscillator from transmitter blocks to bypass this requirement

• Design verification only

2.4GHZ

Low Noise

AmplifierLPF A/D

BER Calculation

• Good estimate of system performance in the presence of noise

• Used Monte Carlo method to measure BER– Sequence of Bernoulli trials– Minimum knowledge of system required

Data Source

System

Delay

Counter, BER math

AWGN Level

BPSK : BER Calculations

Theoretical BER :

Pb : Probability of a bit error (BER)

ρb : Power level of bit (Eb/No)

1

2b bP erfc

BER : Confidence Intervals 1P y p y

α dα

0.1 1.644

0.05 1.96

0.01 2.58

2

2

41 1 1

2

: number of trials

: number of errors

dn ny

N n d

N

n

2 211

2

dt

d

e dt

BPSK : Results

Basic π/4 DQPSK System

• Ideal System and Architecture• No coherent demodulator required

– Less complex receiver implementation– Better spectral characteristics than QPSK, BPSK

• Standard for US and Japanese cell phones

BER wrapper

Data source

TransmitterRF

channelReceiver

Symbol timing recovery

BER tester

DQPSK system wrapper

π/4 DQPSK : Transmitter

Serial to two-bit Parallel

‘1’ -> +1V‘0’ -> -1V

‘1’ -> +1V ‘0’ -> -1V

Symbol Mapper (I Q Modulator)

A

B

Pulse Shaping3-pole LPF

Fc = 500MHz

Pulse Shaping3-pole LPF

Fc = 500MHz

I

Q

2.4GHZ

90º phase shift

+Power

Amplifier

1 GHz Uniform Random

Data

• Parallelize Data

• Map Symbols

• Pulse Shape

• Up-convert and amplify

Signal Constellation

• Directly map a pair of input bits onto relative phases (±π/4, ±3π/4)

Q

I

Example

Q

I

Ak Bk Δθ

0 0 π/4

1 0 3π/4

1 1 -3π/4

0 1 -π/4

00

1111

Transmit: 00 11 11 01

01

Symbol Mapping

cos( ( ))

cos( )cos( ) sin( )sin( )k c

k c c

S A t

S A t A t

cos( )

cos( ) cos( ) sin( )sin( )k

k

I A

I A A

Similarily :

sin( )

sin( )cos( ) cos( )sin( )k

k

Q A

Q A A

Symbol Mapping Code

• Uses state machine to implement:

• Initial state must be on constellation point

1 1

1 1

cos( ) sin( )

cos( ) sin( )k k k

k k k

I I Q

Q Q I

Transmitted Constellation

Transmitted Spectrum

π/4 DQPSK : Receiver

• Four Steps:– Amplify and down-convert– Filter– Demodulate and recover symbol clock– Digitize and Serialize

Low Noise

Amplifier

2.4GHZ

90º phase shift

3-pole LPF Fc = 500MHz

3-pole LPF Fc = 500MHz

I Q Demodulator

2-bit Parallel to Serial

Converter

A/D

A/D

Symbol Timing Recovery

Data Out

Received Spectrum

Received Constellation: Low Noise

Received Constellation: High Noise

IQ Demodulation

1 1

1 1

(cos( )) ( )

(sin( )) ( )k k k k k

k k k k k

sign sign Q Q I I

sign sign Q I I Q

k k

k k

If (cos 0) then A 1, else A 0

If (sin 0) then B 1, else B 0k

k

IQ Demodulator Code

-- Perform A, B recovery

Ip == Ik'delayed(Tsym);

Qp == Qk'delayed(Tsym);

Atemp == Qk*Qp+Ik*Ip;

Btemp == Ip*Qk-Ik*Qp;

• To recover parallel data, pass Atemp and Btemp through threshold detector

• Digitize, Serialize

Symbol Timing Recovery

• Squaring and adding I, Q channels produces tone at symboling frequency

• High-Q BPF isolates tone• Threshold detector creates std_logic clock at

symbol frequency – transitions in middle of bit period

• More complex : feed BPF signal through PLL – more noise-immune

I2+Q2I

QNarrow BPF

Q = 50Threshold Detector

π/4 DQPSK : Viterbi Encoder / Decoder

• Added a simple rate 3/10 Viterbi encoder– Decreases BER – Increases design size x2– Half clock rate and removal of serial to

parallel conversion

BER wrapper

Data source and encoder

TransmitterRF

channelReceiver

Symbol timing recovery

BER tester

DQPSK system wrapper

Decoder

Viterbi Encoder

• Rate 2/3 encoder (K=3)

• Operates on 3 input bits and two bits from cleared register

• Produces specific 10 output bits

• Less complex Decoder

Output Bit 1

Output Bit 0

Input Bit

Viterbi Decoder

• Implemented as state machine

• Makes decision on correct 3-bit output after 10 bits received

• Less complex but less error tolerant

• Large code size

BER with Pulse-Shaping Filters

BER With Viterbi Encoder

Summary of Results

• Basic coverage of VHDL-AMS language• BPSK design example

– Similar results to theoretical and HP-ADS– Verified noise modeling technique– Small, highly ideal model

• π/4 DQPSK design– BER closely matches Agilent ADS and theoretical curves– Increased model complexity with encoder / decoder– Verifies that complete system modeling can be easily

performed in VHDL-AMS

Extensions of Research

• Increase complexity of model to include non-linear effects in subsystems

• Add delay-spread model to propagation channel for multi-path simulation

• Continue iterative design process

Acknowledgements

Special thanks to:

Dr. Richard Shi and MSCAD Lab

RF group members Pavel Nikitin, Cherry Wakayama, Lei Yang

Questions?