Post on 02-Sep-2018
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Low r DS(on) . . . 5 Ω Typical
Avalanche Energy . . . 30 mJ
Eight Power DMOS-Transistor Outputs of150-mA Continuous Current
500-mA Typical Current-Limiting Capability
Output Clamp Voltage . . . 50 V
Low Power Consumption
description
The TPIC6B273 is a monolithic, high-voltage,medium-current, power logic octal D-type latchwith DMOS-transistor outputs designed for use insystems that require relatively high load power.The device contains a built-in voltage clamp onthe outputs for inductive transient protection.Power driver applications include relays, sole-noids, and other medium-current or high-voltageloads.
The TPIC6B273 contains eight positive-edge-triggered D-type flip-flops with a direct clear input.Each flip-flop features an open-drain powerDMOS-transistor output.
When clear (CLR) is high, information at the Dinputs meeting the setup time requirements istransferred to the DRAIN outputs on the positive-going edge of the clock (CLK) pulse. Clocktriggering occurs at a particular voltage level andis not directly related to the transition time of thepositive-going pulse. When the clock input (CLK)is at either the high or low level, the D input signalhas no effect at the output. An asynchronous CLRis provided to turn all eight DMOS-transistoroutputs off. When data is low for a given output,the DMOS-transistor output is off. When data ishigh, the DMOS-transistor output has sink-currentcapability.
Outputs are low-side, open-drain DMOStransistors with output ratings of 50 V and 150-mAcontinuous sink-current capability. Each outputprovides a 500-mA typical current limit atTC = 25°C. The current limit decreases as thejunction temperature increases for additionaldevice protection.
The TPIC6B273 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Copyright 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLRD1D2
DRAIN1DRAIN2DRAIN3DRAIN4
D3D4
GND
VCCD8D7DRAIN8DRAIN7DRAIN6DRAIN5D6D5CLK
DW OR N PACKAGE(TOP VIEW)
logic symbol †
R1
11CLK C1
DRAIN14
DRAIN25
DRAIN36
DRAIN47
DRAIN514
DRAIN615
DRAIN716
DRAIN817
CLR
† This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
INPUTS OUTPUT
LHHH
FUNCTION TABLE(each channel)
CLK D
X↑↑L
XHLX
HLH
Latched
CLR DRAIN
H = high level, L = low level, X = irrelevant
1D2
D13
D28
D39
D412
D513
D618
D719
D8
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CLK11
CLR1
C1
CLR
1DD1 2
DRAIN14
C1
CLR
1DD23
DRAIN25
C1
CLR
1DD38
DRAIN36
C1
CLR
1D9
DRAIN47
C1
CLR
1DD512
DRAIN514
C1
CLR
1DD613
DRAIN615
C1
CLR
1DD718
DRAIN716
C1
CLR
1DD819
DRAIN817
D4
10GND
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
VCC
Input
GNDGND
DRAIN
50 V
20 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unlessotherwise noted) †
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power DMOS drain-to-source voltage, VDS (see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous source-to-drain diode anode current 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed source-to-drain diode anode current (see Note 3) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . Continuous drain current, each output, all outputs on, ID, TC = 25°C 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . Peak drain current single output, IDM,TC = 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-pulse avalanche energy, EAS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avalanche current, IAS (see Note 4) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating case temperature range, TC –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.2. Each power DMOS source is internally connected to GND.3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGETC ≤ 25°C
POWER RATINGDERATING FACTORABOVE TC = 25°C
TC = 125°CPOWER RATING
DW 1389 mW 11.1 mW/°C 278 mW
N 1050 mW 10.5 mW/°C 263 mW
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, VCC 4.5 5.5 V
High-level input voltage, VIH 0.85 VCC V
Low-level input voltage, VIL 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) –500 500 mA
Setup time, D high before CLK↑ , tsu (see Figure 2) 20 ns
Hold time, D high after CLK↑ , th (see Figure 2) 20 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, TC –40 125 °C
electrical characteristics, V CC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSXDrain-to-source breakdownvoltage ID = 1 mA 50 V
VSDSource-to-drain diode forwardvoltage IF = 100 mA 0.85 1 V
IIH High-level input current VCC = 5.5 V, VI = VCC 1 µA
IIL Low-level input current VCC = 5.5 V, VI = 0 –1 µA
ICC Logic supply current VCC = 5 5 VAll outputs off 20 100
µAICC Logic supply current VCC = 5.5 VAll outputs on 150 300
µA
IN Nominal currentVDS(on) = 0.5 V, IN = ID, TC = 85°C,See Notes 5, 6, and 7
90 mA
IDSX Off state drain currentVDS = 40 V, VCC = 5.5 V 0.1 5
µAIDSX Off-state drain currentVDS = 40 V, VCC = 5.5 V, TC = 125°C 0.15 8
µA
ID = 100 mA, VCC = 4.5 V 4.2 5.7
rDS(on)Static drain-to-source on-stateresistance
ID = 100 mA,TC = 125°C
VCC = 4.5 V, See Notes 5 and 6and Figures 6 and 7
6.8 9.5 Ω
ID = 350 mA, VCC = 4.5 V 5.5 8
switching characteristics, V CC = 5 V, TC = 25°CPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from CLK 150 ns
tPHL Propagation delay time, high-to-low-level output from CLK CL = 30 pF, ID = 100 mA, 90 ns
tr Rise time, drain outputL , D ,
See Figures 1, 2, and 8 200 ns
tf Fall time, drain output 200 ns
ta Reverse-recovery-current rise time IF = 100 mA, di/dt = 20 A/µs, 100ns
trr Reverse-recovery timeF µSee Notes 5 and 6 and Figure 3 300
ns
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.5. Technique should limit TJ – TC to 10°C maximum.6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
RθJA Thermal resistance junction to ambientDW package
All 8 outputs with equal power90
°C/WRθJA Thermal resistance, junction-to-ambientN package
All 8 outputs with equal power95
°C/W
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V
VCC
DRAIN
GND
CLR
VOLTAGE WAVEFORMS
DWord
Generator(see Note A)
CLK
CLR
Output
DCLKDUT
0 V
5 V
0 V
5 V
0 V
5 V
0.5 V
24 V
11
1
10
20
4–7,14–17
ID
235 Ω
Output
CL = 30 pF (see Note B)
24 V
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
5 V
DUT
VCC CLR
DRAIN
GND
D 235 Ω
TEST CIRCUIT
SWITCHING TIMES
D
CLK
WordGenerator
(see Note A)
CLK
5 V
0 V5 V
0 V50%
Output24 V
0.5 V
90%10%
tPLH
tr
50%
90%10%
tPHL
tf
CLK
5 V
0 V50%
D5 V
0 V50% 50%
tsuth
tw
INPUT SETUP AND HOLD WAVEFORMS
CL = 30 pF (see Note B)
OutputWord
Generator(see Note A)
20
10
1
11
24 V
4–7,14–17
ID
Figure 2. Test Circuit, Switching Times, and Voltage WaveformsNOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 KHz,
ZO = 50 Ω.B. CL includes probe and jig capacitance.
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0.1 A
IF
0
IRM
ta
trr
+
–
2500 µF250 V
L = 1 mHIF
(see Note A)
RG
VGG(see Note B)
Driver
TP A
50 Ω
Circuit UnderTest
DRAIN
25 V
t1 t3
t2
TP K
TEST CIRCUITCURRENT WAVEFORM
25% of IRM
di/dt = 20 A/ µs
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to theTP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,t2 = 7 µs, and t3 = 3 µs.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
5 V 15 V
WordGenerator
(see Note A)
VCC
DRAINGND
D
10.5 Ω
200 mH
VDS
TEST CIRCUIT
CLR
DUTCLK
1
11
20
10
tw tav
IAS = 0.5 A
V(BR)DSX = 50 V
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
5 V
0 VID
4–7,14–17
MIN
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A.
Energy test is defined as EAS = IAS x V(BR)DSX x tav/2 = 30 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
2
1
10
4
0.1 0.2 10.4 2 104
0.2
0.1
0.4
I
– P
eak
Ava
lanc
he C
urre
nt –
AA
S
PEAK AVALANCHE CURRENTvs
TIME DURATION OF AVALANCHE
tav – Time Duration of Avalanche – ms
TC = 25°C
10
8
4
2
0
6
0 100 200 300 400
14
12
16
DRAIN-TO-SOURCE ON-STATE RESISTANCEvs
DRAIN CURRENT18
500 600 700ID – Drain Current – mA
VCC = 5 VSee Note A
TC = 25°C
TC = –40°C
TC = 125°C
ΩD
S(o
n)–D
rain
-to-
Sou
rce
On-
Sta
te R
esis
tanc
e –
r
Figure 5 Figure 6
VCC – Logic Supply Voltage – V
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs
LOGIC SUPPLY VOLTAGEΩD
S(o
n)–
Sta
tic D
rain
-to-
Sou
rce
On-
Sta
te R
esis
tanc
e –
r
4
3
1
04 4.5 5 5.5
5
7
8
6 6.5 7
6
2
TC = 125°C
TC = 25°C
TC = – 40°C
ID = 100 mASee Note A
Sw
itchi
ng T
ime
– ns
SWITCHING TIMEvs
CASE TEMPERATURE
–50TC – Case Temperature – °C
ID = 100 mASee Note A
200
150
100
50
250
300
tPHL
tPLH
tr
tf
–25 0 25 50 75 100 125
Figure 7 Figure 8
NOTE C: Technique should limit TJ – TC to 10°C maximum.
TPIC6B273POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
– M
axim
um C
ontin
uous
Dra
in C
urre
nt
MAXIMUM CONTINUOUSDRAIN CURRENT OF EACH OUTPUT
vsNUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
N – Number of Outputs Conducting Simultaneously
of E
ach
Out
put –
ADI
– M
axim
um P
eak
Dra
in C
urre
nt o
f Eac
h O
utpu
t – A
MAXIMUM PEAK DRAIN CURRENTOF EACH OUTPUT
vsNUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
D
N – Number of Outputs Conducting Simultaneously
I
01 2 3 4 5 6 7 8
0.15
0.05
0.4
01 2 3 4 5
0.3
0.2
0.35
0.5
6 7 8
0.45
0.25
0.1
VCC = 5 V
TC = 25°C
TC = 100°C
TC = 125°C
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
VCC = 5 VTC = 25°Cd = tw/tperiod = 1 ms/t period
d = 10%
d = 20%
d = 50%
d = 80%
Figure 9 Figure 10
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish MSL Peak Temp(3)
Op Temp (°C) Top-Side Markings(4)
Samples
TPIC6B273DW ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6B273
TPIC6B273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM TPIC6B273
TPIC6B273DWR ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6B273
TPIC6B273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM TPIC6B273
TPIC6B273N ACTIVE PDIP N 20 20 Pb-Free(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 125 TPIC6B273N
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
TPIC6B273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPIC6B273DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jan-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP10.639.97
2.65 MAX
18X 1.27
20X 0.510.31
2X11.43
TYP0.330.10
0 - 80.30.1
0.25GAGE PLANE
1.270.40
A
NOTE 3
13.012.6
B 7.67.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020ASOIC
NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.5. Reference JEDEC registration MS-013.
120
0.25 C A B
1110
PIN 1 IDAREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL ATYPICAL
SCALE 1.200
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EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAXALL AROUND
0.07 MINALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020ASOIC
SYMM
SYMM
LAND PATTERN EXAMPLESCALE:6X
1
10 11
20
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METALSOLDER MASKOPENING
NON SOLDER MASKDEFINED
SOLDER MASK DETAILS
SOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKDEFINED
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EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020ASOIC
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
SCALE:6X
IMPORTANT NOTICE
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