Post on 13-Mar-2021
A prototype named JadePix-2 comprising a matrix with 112×96 pixels has been designed
and fabricated in a 0.18 μm CMOS Image Sensor process. It contains two digital pixel structures,
both have been realized within 22 μm pitch size. The prototype operates in the rolling-shutter
mode, with processing speeds of 100ns/row and 80ns/row, respectively, for the two pixel
structures. Experimental results show the total ENC and power dissipation of the two structures
are about 29 e- with 6.5 μA/pixel, and 31 e- with 3.7 μA/pixel respectively.
ABSTRACT
Specifications of JadePix-2
Performances of the in-pixel Amp. and dynamic Latch
CONCLUSION AND PERSPECTIVES
We proposed two pixel structures with balance between high precision and circuit simplicity to guarantee
compact pixels (22 μm pitch size). Both versions operate in the rolling-shutter mode and take 100ns and 80ns,
respectively, to process one row. Experimental results show the total ENC and power dissipation of the two
structures are about 29 e- with 6.5 μA/pixel, and 31 e- with 3.7 μA/pixel respectively. The knowledge learned
from JadePix-2 will guide the design of the next generation vertex detector for CEPC and achieve the desired
high spatial resolution.
Highly compact digital pixel structures developed for the
CEPC vertex detector*
Contact: zhouyang@ihep.ac.cn
Yang ZHOU1, Yunpeng LU1, Zhigang WU1,2, Tan SHI3, Xudong JU4, Jing DONG1, Hongbo ZHU1, Qun OUYANG1,2
1State Key Laboratory of Particle Detection and Electronics, Insitute of High Energy Physics, CAS, Beijing 100049, China2University of Chinese Academy of Sciences, Beijing 100049, China3Department of Nuclear Engineering and Raiological Sciences, University of Michigan, Ann Arbor, MI, 48109, USA4ShanghaiTech University, Shanghai 201210, China
INTRODUCTION
In-pixel architecture and signal treatment
Some prototype specifications: 0.18 µm CMOS Imaging Sensor (CIS) technology;
Quadruple well, 6 metal layers process;
~ 20 μm high resistivity (≥1 kΩ•cm) epitaxial layer
112×96 square pixels with 22 µm pitch size;
3×3.3 mm2 layout size;
8 test sub-matrices for two pixel versions, D1-D4
with digital output, A1-A4 with analogue output;
8 Analogue output channels;
16 Column digital data serialized in one LVDS
output pair; 7 LVDS pairs in total.
Output data speed: 160 MHz
Pixel version 1: ~3.7 μA/pixel (power), ~31 e-
(noise), 100ns/row (operation speed);
Pixel version 2: ~6.5 μA/pixel (power), ~29.5 e-
(noise), 80ns/row (operation speed)
Equivalent Cap. of the sensing node
Figure 1: Layout (left) and architecture (right) of JadePix-2.
The proposed CEPC (Circular Electron Positron Collider) will offer the measurements of
the Higgs properties with a new level of precision. The precise determination of the charged
particle tracks and reconstruction of the primary and displaced decay vertices, impose stringent
requirements on the CEPC vertex detector, which somehow incompatible with each other, such
as high spatial resolution (<3μm), low power consumption (<50mW/cm2) and fast processing
speed (<10μs/frame). CMOS pixel sensor with pixel level discrimination represents one of the
most promising candidates. However, the complexity of in-pixel digital circuit always leads to
increased pixel size, which is disfavored to obtain high spatial resolution.
In this context, we propose two pixel structures with balance between high precision and
circuit simplicity to guarantee compact pixels, yet with satisfying high signal over noise ratio.
Both of the two structures are based on the DMAPS (Depleted Monolithic Active Pixel Sensors)
concept, employ a high-voltage (up to 10 V) biased charge collection diode, AC-coupled to a
comparator with OOS (Output Offset Storage) technique to mitigate pixel-to-pixel performance
dispersion. The main difference between the two structures concentrates on the signal
amplification stage used in the comparator.
LATCH
Out+
Out-AMP
Vref1
Vref1
Vref_latch
Vref_latch
Vref2Read
Read
Read
Read
Read
Calib
Calib
Calib
Clamp
LatchVbias
Power_on
Buff
Row_sel
Out
LATCH
Out+
Out-AMP
Vref3
Vref1
Vref_latch
Clamp
Calib
LatchVbias
AMP
RST1
Vref2 Vref2
RST2
Power_on Power_on
Buff
Row_sel
Out
Figure 3: Two pixel structures with a differential amplifier + Latch (version 1, left), and two stage Common-Source amplifier +Latch (version 2, right).
D1 D2
D3 D4
A1
A2
A3
A4
v
Seq
uen
ce
Analogue out buffer (×8)
PISO 16 in 1 (×7)
vIHEP logo
100 ns
Power_on
Latch
Read
Calib
Clamp
Sel_b
Pre_Power on A_D conversion Read_out
Pre_Power on A_D conversion time Read_out
Clock_160MHz
Next row
A_D conversion Reset & Read_out
Power_onLatch
RST1
RST2
Calib
Clamp
Sel_b
80 ns
Pixel version TN FPN
Version 1 negligible ≈ 4 e-
Version 2 negligible negligible
Input DC level: 520 mV
Gain: ~ 52
RMS of Gain distribution: ~ 15
Input DC level: 600 mV
Gain: ~ 6.9
RMS of Gain distribution: ~ 0.4
In-pixel Architecture: High-voltage biased N-well/p-epi collection node (Vbias up to 10V) AC coupled to the following electronics.
Comparators designed with the Output Offset Storage (OOS) technique;
Thresholds adjusted externally at the differential amplifier (Version 1) and at the dynamic Latch (Version 2) ;
Signal and Noise treatment:
The useful signal (amount of e- collected by the diode) is translated into a ΔV on the diode; AC coupled
structure transmit this ΔV to the following comparators where signal is amplified and digitalized; digital
signal is then stored in the Latch and output to column through a digital buffer row by row;
The offsets of the amplifiers are compensated by the combined offset cancellation technique;
Figure 4: operation timing of the pixel version 1 (left) and version 2 (right).
Figure 5: schematic of the signal transmission used for the 55Fe source test (while it was not an good option for this test)
Figure 9: Fix Pattern Noise (left) and Temporal Noise (right) of the in-pixel dynamic Latch. (test results)
Table 1: ENC of the in-pixel latch.
Figure 2: Layout of the two pixel versions, both pitch sizes are 22μm.
Differential amplifier in pixel version 1: Single-end CS Amplifier in pixel version 2:
Figure 7: Gain distribution of the in-pixel differential amplifiers;
the value includes 6.4 amplitude on the PCB and 0.8 of two-stage
source followers on the sensor.
Performances of the pixel matrix
* This study was supported by the National Key Program for S&T Research and Development (2016YFA0400400) and the National Natural Science Foundation of China (11605217)
C= 𝑄
𝑉≈ 4.9𝑓𝐹
1640 e- collection peak
- 4 stage Amp.: limit only ~ 10 mV linear response range on the sensing node; leave other situation either no gain or saturated.
- the Amp. was tuned to let the input signal ~ 1600e- in the linear response range, while no response for smaller signals and saturate for larger ones.
- Events only with S/N > 10 was recorded.
Threshold Distribution
Entries 1536
Mean 0.575
Std Dev 0.00108
0.566 0.568 0.57 0.572 0.574 0.576 0.578 0.58
Threshold [V]
0
50
100
150
200
250
300
350
400
Nu
mb
ers
pe
r e
ntr
y
Threshold Distribution
Entries 1536
Mean 0.575
Std Dev 0.00108
Temporal Noise
Entries 1536
Mean 0.0004174
Std Dev 0.0002302
0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0.004
Noise [V]
0
50
100
150
200
250
300
350
Num
bers
per
ent
ry
Temporal Noise
Entries 1536
Mean 0.0004174
Std Dev 0.0002302
Nu
m. o
f ev
ents
Figure 8: Gain distribution of the in-pixel two stages single-end CS
amplifiers; the value includes 0.8 of two-stage source followers on
the sensor.
Gainin-pixel = Mean value/(0.8*6.4) Gainin-pixel = Mean value/0.8
FPN = 1.15 mVTN = 0.1 mV
FPN = 1.08 mV TN = 0.4 mV
FPN = 53.3/52 = 1.03 mV TN= 10.27/52 ≈ 0.2 mV
Figure 10: Noise (equivalent at the sensing node) of pixel matrix version 1: FPN (left) and TN (right)
Matrix version TN FPN Total Noise
Version 1 11 e- 29 e- ~31 e-
Version 2 5.5 e- 29 e- ~29.5 e-
Figure 11: Noise (equivalent at the sensing node) of pixel matrix version 2: FPN (left) and TN (right).
Table 2: ENC of the pixel matrix.
Figure 6: Charge collection response peak of 55Fe source: the X-axis value shows
the ΔV on the sensing node while the whole 1640 e- were collected by one pixel.
Pixel level Column
level
Chip level
P+/Nwell
Nwell/ Psub
V_diode
AMP AMP NMOS-SFOutput
PMOS-SF
Set-up conditions: