New developments in silicon pixel detectors · PDF fileATLAS CMOS DEMONSTRATOR PROGRAM...

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Transcript of New developments in silicon pixel detectors · PDF fileATLAS CMOS DEMONSTRATOR PROGRAM...

  • 1/9/2019

    New developments in silicon pixel detectors

    Daniela Bortoletto

  • 1/9/2019

    FCC-ee Vertex Detector Requirements

    • Efficient tagging of heavy quarks through precise determination of displaced vertices required for many physics goals

    • Good single point resolution: σSP~3 μm − Small pixels

  • 1/9/2019

    Detector Conceptual Designs (CDR) • CLD Detector Design: Adaptation

    of the CLICdet to FCC-ee

    Daniela Bortoletto, FCC-ee Workshop 3

    • IDEA Detector Design

  • 1/9/2019

    Vertex Detector Conceptual Design

    Daniela Bortoletto, FCC-ee Workshop 4

    Vertex detector (VXD)

    • Pixel sizes 25x25 μm2 with single point

    resolution of 3 μm

    • Radius from 1.7 to 5.7 cm

    • Barrel: 3 double layers (0.6 X0 /double layer)

    • Endcap: 3 double disks (0.7 X0 /double disk )

    Low material achieved with:

    • Common support for two sensitive layers

    • 50 μm -thick sensors 0.6% X0 per double layer

    [0.2% X0/layer like CLICdet + 0.1% X0/layer (for

    ALICE-like cooling)]

  • 1/9/2019

    Vertex Detector Performance Achieved impact parameter resolution below 1 μm for high-energy muons in the barrel (well below the high momentum limit of 5 μm)

    Daniela Bortoletto, FCC-ee Workshop 5

    E. Leogrande

  • 1/9/2019

    R&D for FCC-ee Vertex Detector

    • Benefits from a

    decade of Linear

    Collider R&D and

    effort for CepC

    • But also from:

    −ALICE

    −BELLE II

    −Mu3e

    −……

    Daniela Bortoletto, FCC-ee Workshop 6

    How we perceive R&D

    FCCee

  • 1/9/2019

    R&D for FCC-ee Vertex Detector

    • Benefits from a

    decade of Linear

    Collider R&D and

    effort for CepC

    • But also from:

    −ALICE

    −BELLE II

    −Mu3e

    −…..

    Daniela Bortoletto, FCC-ee Workshop 7

    Marcel Stanitzki

    In reality there are many

    interconnections

    FCCeeFCCee

  • 1/9/2019

    Pixel Detector R&D

    • Hybrid Pixel sensors

    • Monolithic active pixel sensors (MAPS)

    − Sensor and readout electronic on the same wafer

    − Charge collection by diffusion

    − Low material

    − Low cost

    • Fully Depleted CMOS technology (DMAPS)

    − Fast Charge collection by drift (

  • 1/9/2019

    Hybrid Planar Sensors • Used in all LHC experiments allow independent optimisation of

    r/o ASIC and sensor

    • e+e- applications:

    − ultra-thin sensors with high-performance r/o ASICs

    • The CLICPix2 ASIC (Timepix/Medipix chip family)

    − 65nm CMOS Technology

    − 128x128 pixels, 25x25 µm2 (extremely fine bump bonding)

    − 5 bit TOT and 8 bit TOA for each pixels

    − Shutter based readout with data compression

    − Power Pulsing of matrix and readout block

    − Performance evaluation ongoing with sensors with active edge

    sensors produced by FBK and ADVACAM

    Daniela Bortoletto, FCC-ee Workshop 9

    VERTEX 2018, October 2018, Magdalena Munker, [email protected] 7

    CLICpix

    - Timepix/Medipix chip family

    - 65 nm CMOS technology

    - Pixel size of 25 μm x 25 μm

    - Power pulsing

    CLICpix - readout ASIC to meet requirements for the vertex detector: Image of a bumped CLICpix2 ASIC from IZM:

    CLICpix:

    - 4 bit ToT and ToA, matrix size of 64 x 64 pixels

    CLICpix2:

    - 5 bit ToT and 8 bit ToA, matrix size of 128 x 128

    pixels, improved noise isolat ion

    CLICpix planar sensor stud ies:

    - Challenge to achieve spat ial resolut ion

    requirement for 50 μm thin sensors

    - Challenge to master fine pitch bump

    bonding

    CLICpix2 planar sensor stud ies:

    - Single chip bump bonding process on

    carrier wafers by IZM, using SnAg bumps

    - Performance evaluation currently ongoing

    Cross sect ion of CLICpix bump bonded to planar sensor from IZM:

    CLICpix2

    Planar sensor

    A. Nürnberg 2016 JINST 11 C11039

    • Bumping performed by IZM using SnAg

    bumps and handle wafers ➠Challenging !

    Mathieu Benoit

  • 1/9/2019

    Hybrid: Capacitive Coupled Pixel Detectors • HV-CMOS chip providing “sensors” and

    ”amplification”

    • Capacitive coupling to r/o ASIC through a 100 nm

    glue layer deposited using flip-chip set-up

    • CCPDv3 and CLIC CCPD (25x25 µm2 pixels) in

    ams aH18 HV-CMOS

    • Proof-of-principle test-beam measurements, e.g.

    using 65 nm CLICpix r/o ASIC (25 𝝁m pitch)

    Daniela Bortoletto, FCC-ee Workshop 10

    29/05/2018Simon Spannagel - Technologies for Vertex & Tracking at CLIC14

    CLICpix2 + C3PD

    ● Two generations of active sensors (CCPDv3, C3PD)

    in AMS 180 nm HV-CMOS process,

    ● 10-1000Ωcm substrates, 25 x 25μm2 pitch

    ● First test beam measurements performed

    ● Ef iciency > 90% , σt ~7ns, σSP ~8μm

    ● Finite-element simulation of capacitive coupling

    ● Ongoing work:

    ● Evaluation of high-

    resistivity sensors for

    larger depletion zone

    ● Glue-process optimization

    25μm

    CLICpix2

    C3PD

    29/05/2018Simon Spannagel - Technologies for Vertex & Tracking at CLIC14

    CLICpix2 + C3PD

    ● Two generations of active sensors (CCPDv3, C3PD)

    in AMS 180 nm HV-CMOS process,

    ● 10-1000Ωcm substrates, 25 x 25μm2 pitch

    ● First test beam measurements performed

    ● Ef iciency > 90% , σt ~7ns, σSP ~8μm

    ● Finite-element simulation of capacitive coupling

    ● Ongoing work:

    ● Evaluation of high-

    resistivity sensors for

    larger depletion zone

    ● Glue-process optimization

    25μm

    CLICpix2

    C3PD

    Beam test results SPS AIDA Telescope

  • 1/9/2019

    3D Integrated Silicon on Insulator

    • SOI pixel technology provides Monolithic Detectors with fine resolution and high functionality CMOS .

    Daniela Bortoletto, FCC-ee Workshop 11

    • Features of SOI Pixel Detector

    − High Resistive fully depleted

    sensor (50 𝝁m~700 𝝁m thick) with low capacitance ➠Large

    S/N.

    − Full CMOS processing

    − Can be operated in wide

    temperature (1K-570K) range.

    − Based on Industry Standard

    Technology.

    Yasuo Arai

  • 1/9/2019 Daniela Bortoletto, FCC-ee Workshop 12

  • 1/9/2019

    Issues with SOI

    • CMOS electronics affected

    by Detector High Voltage.

    (Back-Gate Effect)

    • Coupling between Circuit

    signal and sense node.

    (Signal Cross Talk)

    • Oxide trapped hole induced

    by radiation will shift

    transistor threshold voltage.

    (Radiation Tolerance)

    Daniela Bortoletto, FCC-ee Workshop 14

  • 1/9/2019

    Double SOI Detector

    • Middle Si layer shields coupling between sensor and circuit.

    • It compensate E-field generated by radiation trapped holes.

    • Can be used in High radiation environment.

    • DSOI is not a standard

    process

    − Small number of

    produced wafers

    − Process issues (void,

    bending,,,)

    − Long delivery time

    Daniela Bortoletto, FCC-ee Workshop 15

  • 1/9/2019

    Double SOI Detector

    Daniela Bortoletto, FCC-ee Workshop 16

    Middle Si

    Transistor

    Middle Si

    Contact

    Metal 1

    Sensor

    Contact

    • Middle Si layer shields coupling between sensor and circuit.

    • It compensate E-field generated by radiation trapped holes.

    • Can be used in High radiation environment.

    • DSOI is not a standard

    process

    − Small number of produced

    wafers

    − Process issues (void,

    bending,,,)

    − Long delivery time

  • 1/9/2019

    Studies for ILC • Two kinds of SOIPIX-DSOI detectors used:

    − FPIX2 x 4: 8 μm square pixel detector

    − SOFIST(v.1 & 2) x 2: 20 μm square pixel detector

    • Beam tests at FNAL with 120 GeV Protons

    Daniela Bortoletto, FCC-ee Workshop 17

    Less than 1 μm Position Resolution for high-energy

    charged particle is achieved

    (K. Hara et al.,

    Development of

    Silicon-on-Insulator

    Pixel Detectors,

    Proceedings of

    Science, to be

    published)

  • 1/9/2019

    Monolithic Pixel Detector Evolution

    Daniela Bortoletto, FCC-ee Workshop 21

  • 1/9/2019

    ATLAS CMOS DEMONSTRATOR PROGRAM

    LF-MONOPIX

    Pixel with R/O logic 50 𝜇m x250 𝜇m

    ATLASPIXMUPIX

    LFOUNDRY ams TOWERJAZZ

    36.5 x36.5 𝜇m2

    36x 40

    𝜇m2

    DMAPS development important for LHCb upgrade II,

    CepC, CLIC, ILC, FCC-ee and FCC-hh

    Monolithic

    pixel sensor

    from ALICE

    to ATLAS

    Daniela Bortoletto, FCC-ee Workshop 22

    WITH SEVERAL FOUNDRIES