Efficient hybrid continuous-time/discrete-time cascade ΣΔ modulators for wideband applications

Efficient hybrid continuous-time/discrete-time cascadeΣΔ modulators for wideband applications$

J. Gerardo García-Sánchez, José M. de la Rosa n

Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), C/Américo Vespucio, 41092 Sevilla, Spain

a r t i c l e i n f o

Article history:Received 23 January 2013Received in revised form6 August 2013Accepted 29 October 2013

Keywords:Analog-to-digital convertersSigma-delta modulatorsHybrid continuous-time/discrete-timecircuit techniquesMulti-rate signal processing

a b s t r a c t

This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for theimplementation of power-efficient analog-to-digital converters in broadband wireless communicationsystems. Two alternative implementations of multi-rate cascade architectures are studied and comparedwith conventional single-rate continuous-time topologies, taking into account the impact of maincircuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In allcases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔmodulators under study, providing analytical relationships between their system-level performanceand the corresponding circuit-level error parameters. Theoretical predictions match simulation results,showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔmodulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end(discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presentedapproach.

1. Introduction

The need of increasingly higher data rates in mobile telecomsystems demands for power-efficient wideband Analog-to-DigitalConverters (ADCs). Among other ADC techniques, Sigma–DeltaModulators (ΣΔMs) implemented with Continuous-Time (CT)circuits have demonstrated to be a suited solution in theseapplications. Compared with Discrete-Time (DT) ΣΔMs – usuallyimplemented with Switched-Capacitor (SC) circuits – CT-ΣΔMsachieve faster rates with less power consumption. However, theypresent a higher sensitivity than DT-ΣΔMs to some critical circuitnonidealities, mainly, clock jitter error and circuit element toler-ances [1]. This has motivated the exploration of other alternativeslike the so-called Hybrid CT/DT ΣΔMs (H-ΣΔMs) [2–6], in whichthe front-end part of the ΣΔM is implemented with CT circuits,thus benefiting from their faster operation, embedded anti-aliasing filtering and reduced power dissipation, while keepinga higher robustness than pure CT-ΣΔMs against circuit errors.

The main drawback of H-ΣΔMs is that their sampling rate isindeed limited by the DT part of the system. This is the mainreason why reported silicon implementations of H-ΣΔMs do notreally exploit the speed advantages of using CT circuits. A possiblesolution to palliate this limitation might be using a differentsampling frequency for each part (either CT or DT) of theH-ΣΔM, i.e. using a multi-rate system [7]. This approach has beenapplied to both cascade DT- [8] and CT-ΣΔMs [9]. In both cases,the strategy was based on using a lower OverSampling Ratio (OSR)in the front-end parts of the modulator –where most of the poweris consumed – and a higher OSR in the subsequent stages or blocks– where the dynamic requirements can be relaxed. These limita-tions can be palliated in cascade H-ΣΔMs if the signal is down-sampled across the cascade, so that the CT front-end operates at ahigher clock rate than the DT back-end, thus relaxing its dynamicrequirements, and achieving the targeted specifications by prop-erly combining the different OverSampling Ratios (OSRs) in amulti-rate operation [10].

In spite of the potential benefits of the combination of multi-rate signal processing and hybrid CT/DT circuit techniques, an in-depth study of the influence of their main circuit nonideal effectson the performance of H-ΣΔMs is required to get optimizeddesigns in terms of power consumption and silicon area. Basedon the design equations derived from such a study, a systematictop-down/bottom-up design procedure can be established toreach the required ΣΔM specifications with minimized power

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☆This work has been supported by the Spanish Ministry of Economy andCompetitiveness (with support from the European Regional Development Fund)under contract TEC2010-14825/MIC.

n Corresponding author. Tel.: þ34 954466666.E-mail addresses: jggarcia@imse-cnm.csic.es (J. Gerardo García-Sánchez),

jrosa@imse-cnm.csic.es (J.M. de la Rosa).

Please cite this article as: J. Gerardo García-Sánchez, J.M. de la Rosa, Efficient hybrid continuous-time/discrete-time cascade ΣΔmodulators for wideband applications, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.10.017i

Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

dissipation and silicon area. This procedure has been applied toboth CT-ΣΔMs [1] and SC-ΣΔMs [11]. However, to the best of theauthors' knowledge, H-ΣΔMs have not been analyzed taking intoaccount the impact of their building-block errors.

This paper contributes to this topic and analyses the impactof main circuit nonidealities on the performance of two differenttypes of cascade Multi-Rate (MR) H-ΣΔMs. The first one, namedUpSampling MR H-ΣΔM (US MR H-ΣΔM), increases the OSR in theback-end stages in the cascade. The second one, referred to asDownSampling MR H-ΣΔM (DS MR H-ΣΔM), decreases the OSR inthe back-end stages. Both architectures are compared with conven-tional Single-Rate (SR) cascade CT-ΣΔMs. All the architecturesunder study are analyzed in order to obtain closed-form designequations that relate main ΣΔM performance metrics with circuit-error model parameters. These equations, which are also valid for SRH-ΣΔMs, are compared with time-domain behavioral simulations,considering diverse cases of signal bandwidths and target effectiveresolutions, showing a good agreement between theory and simu-lated performance. As a case study, the design of a fourth-order2-stage cascade DS MR Gm-C/SC ΣΔM with 4-bit quantization ispresented to demonstrate the feasibility of the presented approachto digitize signals with a 44–92 dB peak signal-to-(noiseþdistor-tion) ratio within a programmable 5–60MHz bandwidth.

The paper is organized as follows. Section 2 gives a backgroundon MR H-ΣΔMs, overviewing the conceptual topologies andbasic principles behind upsampling and downsampling strategies.Section 3 describes the modulator architectures under study,analyzing their main performance figures from an ideal point ofview. The impact of main error mechanisms is analyzed in Section4, validating the theoretical predictions with time-domain simula-tions. As an application, the presented study is applied to thesystematic high-level design of a cascade GmC/SC MR H-ΣΔMs,described in Section 5.

2. Background on multi-rate hybrid ΣΔMs

Fig. 1(a) shows the conceptual implementation of a conven-tional cascade (two-stage) MR-ΣΔM.1 For the sake of generality,multibit quantization will be assumed in all stages of the cascade,with Bi being the number of bits of the internal quantizer in the ithstage. The sampling frequency fsi of the different modulator blocks

is depicted in the figure. The most common situation in conven-tional MR-ΣΔMs is that the front-end stage operates at fs1,whereas the remaining ith stages are sampled at f si4 f s1. Thisapproach – also referred to as upsampling MR-ΣΔM [10] – benefitsfrom increasing values of OSR in the back-end stages – where thedynamic requirements are less demanding than in the front-endstages [7,9].

The operation behind the modulator in Fig. 1(a) is conceptuallythe same as in a conventional SR cascade ΣΔM. All stage outputsare combined by the Digital Cancellation Logic (DCL) – clocked atfs2 – so that ideally only the quantization error of the last stageremains and it is shaped by a Noise Transfer Function (NTF) whoseorder (L) is the sum of the orders of all stages in the cascade (Li).However, as a consequence of using several sampling frequencies,additional upsampler blocks – represented conceptually in Fig. 1(a)– are required, where r� f s2=f s1 denotes the upsampling ratio, withr41 [10].

2.1. Upsampling MR H-ΣΔMs

The concept of MR-ΣΔMs can be extended to hybrid CT/DTimplementations as conceptually depicted in Fig. 1(b) that repre-sents a cascade two-stage MR H-ΣΔM. The circuit nature (eitherCT or DT) of the different modulator blocks as well as theircorresponding sampling frequencies are highlighted. The analysisof Fig. 1(b) can be carried out by applying a DT–CT transformationto the front-end stage of Fig. 1(b). The resulting MR H-ΣΔM isequivalent to the original MR DT-ΣΔM. This CT–DT equivalencecan be guaranteed because of the DT nature of the (open) looptransfer function from the front-end quantizer output to thesampled quantizer input [12,13].

2.2. Downsampling MR H-ΣΔMs

Fig. 2 shows a conceptual block diagram of a downsampling(two-stage) cascade MR H-ΣΔM architecture proposed in [10]. Incontrast to conventional (upsampling) MR H-ΣΔMs, the back-end(DT) stage operates at a rate lower than that of the front-end (CT)stage, i.e. f s1 ¼ p � f s2 , with p41 being the downsampling ratio. Themain drawback of this approach is the aliasing caused by thedownsampling processing, what requires using an interstage Anti-Aliasing Filtering (AAF). However, as shown in [10], the operationof the AAF can be completely translated to digital domain, by usingtwo additional digital blocks, whose transfer functions are namedH1ðzÞ and H2ðzÞ.

x ADC1

DAC1 y

Second Stage (fs2)

DCL (fs2)

fs2fs2

DT Filter

Upsampler

r DCL1

First Stage (fs1)

x ADC1

DAC1 y

Second Stage (fs2)

DCL (fs2)

fs2fs2

DT Filter

CT Filter

Upsampler

r DCL1

First Stage (fs1)

Fig. 1. Conceptual block diagram of a upsampling cascade MR-ΣΔM: (a) DT scheme and (b) hybrid CT/DT scheme.

1 Two-stage cascade ΣΔMs will be considered in this paper without loss ofgenerality.

J. Gerardo García-Sánchez, J.M. de la Rosa / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎2

Therefore, the operation behind the modulator in Fig. 2 isessentially the same as in conventional cascade ΣΔMs. The maindifference is that the DCL transfer functions are designed so thatthey must remove not only the quantization error of the front-endstage E1ðzÞ, but also its aliased components. To this purpose, H1ðzÞand H2ðzÞ must be reconfigurable and programmable according tothe value of p [10]. These functions are completely implemented inthe digital domain, without any extra analog hardware required,and can be synthesized for different values of p as detailed below.

3. ΣΔM architectures under study

Fig. 3 shows the block diagram of the MR H-ΣΔMs under study,where HðsÞ ¼ 1=s and HðzÞ ¼ z�1=ð1�z�1Þ, denote the transferfunctions of the CT and DT integrators, respectively. The same loop-filter topology is used in all cases, consisting of a fourth-order cascade2-stage (2–2) architecture, where the front-end stage includes feed-forward paths to implement a Unity Signal Transfer Function (USTF).Embedded multibit quantization is considered in both stages of themodulators. Two different topologies are considered attending to thesampling rate of each stage and its circuit nature, either CT or DT.Fig. 3(a) is a conventional US MR H-ΣΔM, where the back-end stageoperates at a higher sampling frequency than the front-end stage [7],i.e. f s2 ¼ r � f s1. The opposite operation is carried out in Fig. 3(b),which corresponds to a DS MR H-ΣΔM, in which the front-end stageoperates at the highest sampling rate, i.e. f s1 ¼ p � f s2.

Both MR H-ΣΔMs in Fig. 3 are compared with the conventionalcascade SR CT-ΣΔM shown in Fig. 4, where both stages areimplemented using CT circuits and operate at the same samplingfrequency, fs.

3.1. Ideal noise transfer function

The analysis of the modulators in Fig. 3 can be carried out in theZ-domain by applying a CT-to-DT transformation to the CT stages,so that the resulting DT-ΣΔMs are equivalent to the originalΣΔMs [14]. Thus, assuming a linear model for the quantizers inFigs. 3(a) and 4(a) and Non-Return-to-Zero (NRZ) feedback DACs inthe CT stages, it can be shown that the quantization NTF at theoutput of both modulators are respectively given by [9,10]

NTFSRðzÞ ¼ ð1�z�1ÞðL1 þ L2Þ ð1Þ

NTFUSðzÞ ¼ ð1�z� rÞL1 ð1�z�1ÞL2 ð2Þwhere L1 ¼ 2 and L2 ¼ 2 stand for the order of the front-end andthe back-end stages of the modulators, respectively.

Note that the back-end (DT) stage of the DS MR H-ΣΔM shownin Fig. 3(b) operates at a lower rate than the front-end (CT) stage.Therefore, the quantization error signal, E1ðzÞ, that is fed to theback-end stage, is downsampled, thus containing aliased compo-nents at multiples of fs2. This can be expressed in the Z-domain as

E1;ALðzÞ ¼1p

∑p�1

k ¼ 0E1ðz1=pejð2πk=pÞÞ ð3Þ

Assuming a linear model for the quantizers in Fig. 3(b), it can beshown that both E1ðzÞ and its aliased error components can becompletely cancelled out if H1ðzÞ and H2ðzÞ are given by thefollowing expression [10]:

H1ðzÞ ¼H2ðzÞ ¼ ∑p�1

k ¼ 0z�k

Taking into account the above expression, it can be shown that theNTF of Fig. 3(b) can be written as

NTFDSðzÞ ¼ ð1�z�1ÞL1 ð1�z�pÞL2 ð5ÞNote from (2)–(5) that both MR H-ΣΔMs in Fig. 3 provide

identical noise-shaping provided that p¼r. As an illustration, Fig. 5plots jNTFDSðf Þj vs. the normalized frequency for different cases ofp, highlighting the variation of the notch frequency caused by themulti-rate operation.

3.2. Ideal in-band noise power

Integrating the expressions (1), (2) and (5) within the signalbandwidth, Bw, it can be shown that the In-Band Noise (IBN)power at the output of the modulators in Figs. 3 and 4 arerespectively given by [1,10]

IBNidealUS C

Δ2π2Lr2L1

12ð2Lþ1ÞOSR2Lþ12US

IBNidealDS C

Δ2π2Lp2L2

12ð2Lþ1ÞOSR2Lþ11DS

IBNidealSR C

Δ2π2L

12ð2Lþ1ÞOSR2Lþ1 ð8Þ

where Δ stands for the quantization step of the last quantizer;L� L1þL2 ¼ 4 is the loop-filter order of the ΣΔMs; OSRSR � f s=ð2BwÞ is the OSR of the SR CT-ΣΔM, and OSR2US � f s2=ð2BwÞ andOSR1DS � f s1=ð2BwÞ denote the value of the largest OSR in the USMR H-ΣΔM and DS MR H-ΣΔM, respectively. It can be noted thatthe expressions in (6) and (7) reduce to the one obtained byconventional SR CT-ΣΔMs, shown in (8), provided that r¼ p¼ 1and OSR2US ¼OSR1DS ¼OSRSR. Note also that the same ideal IBN canbe achieved by all ΣΔMs in Fig. 3, by properly choosing the valuesof r, p, OSRSR , OSR2US and OSR1DS . As an illustration, Fig. 6 depictsthe Signal-to-Noise Ratio (SNR) vs. OSR1DS for different values of rand p, showing a good agreement between theory and simulationswithin a wide resolution range.

4. Analysis of nonideal performance

The performance described above assumed that the ΣΔMs inFigs. 3 and 4 were implemented with ideal building blocks. However,in practice, the noise shaping (and consequently the effective resolu-tion) of these modulators is degraded by the action of circuit-levelerrors. This section analyses the IBN degradation caused by three ofthe most critical nonideal effects, namely, mismatch error, finite OTAdc gain and Gain-BandWidth (GBW) product. In order to perform thisanalysis, Forward-Euler (FE) SC integrators, conceptually modelled as

x ADC1

DAC1 y

Second Stage (fs2) DCL (fs1)

fs2fs2

DT Filter

CT Filter

Downsampler

First Stage (fs1)

p DCL1pH1(z)

p DCL2H2(z)

Fig. 2. Conceptual block diagram of a downsampling cascade MR H-ΣΔM [10].

J. Gerardo García-Sánchez, J.M. de la Rosa / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 3

shown in Fig. 7(a), will be used for the DT stages, while Gm-Cintegrators, considering the 1-pole OTA model depicted in Fig. 7(b),will be used for the CT blocks.

In order to analyse the impact of a given circuit error, genericallydenoted as ε, a systematic procedure similar to the one used for SCΣΔMs [11] and CT ΣΔMs [1] is followed, but in this case taking into

Fig. 3. Cascade 2–2 MR H-ΣΔMs: (a) US MR H-ΣΔM and (b) DS MR H-ΣΔM.

Fig. 4. Block diagram of a cascade 2–2 SR CT-ΣΔM.

account that different circuit dynamics are involved in H-ΣΔMs.This way, the integrator transfer functions, H(s) and H(z) inFigs. 3 and 4, are replaced by the corresponding nonideal functionsdegraded by errors, Hðz; ε!Þ and Hðs; ε!Þ, where ε! denotes a genericvector that includes all different model parameters for a given error.Thus, using a linear model for the quantizers and applying the CT-to-DT equivalence described in the previous section, the effect of circuiterrors can be propagated through the modulator in order to obtainthe nonideal expressions for NTF and IBN. This procedure that can beconceptually formulated as

Hðz; ε!Þ;Hðs; ε!Þ-NTFðz; ε!Þ-IBNðOSR;Bi; L; p; ε!Þ ð9Þ

has been followed to find out the nonideal expressions of the IBNdegraded by different errors described below.

4.1. Capacitor mismatch and time-constant error

Let us assume that the integrators in Fig. 7 have a weight errorcaused by technology process variations. In the case of SC FEintegrators, this gain error – due to capacitor mismatch and denotedas εDT – is modelled as a random deviation of the integrator's weight,i.e. the ratio between the sampling capacitor CS and the integratorcapacitor CI [11]. In the case of Gm-C realizations, integrator's weighterror, εCT, is due to random variations of the time constant, i.e. the

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−100

Normalized Frequency

(f)| (

p=1p=2p=4p=6p=1p=2p=4p=6

Fig. 5. jNTFDSðf Þj vs. normalized frequency (f =f s).

8 16 32 64

405060708090

100110120130

SimulationTheory r = p = 2

r = p = 6

r = p = 4

Fig. 6. SNR vs. OSR1DS for different values of r and p.

Fig. 7. Models used for the (a) SC Integrator and (b) Gm-C Integrator.

transconductance-capacitor product [1]. Considering the effect of εDTand εCT, H(s) and H(z) become modified as [1,11]

Hðz; εDTÞ ¼ð1�εDTÞz�1

1�z�1 ; Hðs; εCTÞ ¼ð1�εCTÞ � f s

sð10Þ

Replacing the above transfer functions in Figs. 3 and 4, andpropagating the impact of mismatch errors according to theprocedure formulated in (9), it can be shown that the IBN powerat the output of the ΣΔMs under study can be approximated by

IBNmisSR C ð1þεCTÞ2 � IBNideal

SR þ Δ21π

2L1ε2CT112ð2L1þ1ÞOSR2L1 þ1

IBNmisUSMRC ð1þεDTÞ2 � IBNideal

USMRþΔ2

1π2L1ε2CT1r

2L1 þ1

12ð2L1þ1ÞOSR2L1 þ12US

IBNmisDSMRC ð1þεDTÞ2 � IBNideal

þ Δ21π

12ð2L1þ1ÞOSR2L1 þ11DS

� ∑p�1

k ¼ 0αðkÞεCT11þ

βðkÞ2εCT12

��2

ð11Þ

where Δ1 stands for the quantization step of the front-endquantizer; εCTij denote the weight error of the j-th Gm-C integratorin the i-th stage (i,j¼1,2); and αðkÞ ¼ ð2e� j2πk=p�e� j4πk=pÞ andβðkÞ ¼ ðe� j2πk=pþe� j4πk=pÞ.

4.2. Finite OTA dc gain

Let us consider now that the integrators in Fig. 7 have a finiteOTA dc gain. This effect can be modelled as a deviation of theintegrator transfer functions given by [1,11]

Hðz;μÞC z�1

1�z�1ð1�g � μÞ; Hðs;μÞ ¼ f sμf sþs

ð12Þ

where g � CS=CI stands for the weight of the SC integrator;μ� 1=Adc, and Adc ¼ gm � Ro denotes the finite OTA dc gain of bothSC and Gm-C integrators in Fig. 7.

Thus, taking into account this effect on the integrators transferfunctions, it can be demonstrated that the IBN at the output of themodulators in Figs. 3 and 4 is given by

IBNgainSR C 1þ2Lþ1

2L�1� μ2 � OSRSR

� �2" #

� IBNidealSR

þ Δ21π

2L1 �2μ21

12 � ð2L1�1Þ � OSR2L1 �1SR

IBNgainUSMRC 1þ2Lþ1

2L�1� μ2 � OSR2US

� �2" #

� IBNidealUSMR

þ Δ21π

2L1 �2μ21r

2L1 �1

12 � ð2L1�1Þ � OSR2L1 �12US

IBNgainDSMRC 1þ2Lþ1

2L�1� μ2 � OSR1DS

� �2" #

� IBNidealDSMR

þ Δ21π

2L1 �2μ21p

2L1 �1

12 � ð2L1�1Þ � OSR2L1 �11DS

ð13Þ

where μi � 1=Adci1þ1=Adci2 and Adcij is the dc gain of the j-thintegrator in the i-th stage.

4.3. Gain-bandwidth product

Following the same procedure as in previous sections, it can befound that the IBN degradation caused by the effect of theintegrators' GBW can be modelled by replacing the expressionsof εCTij and εDTij in (11) by the following expressions:

εCTij �f s

GBWij; εDTij � e�π GBWij=f s ð14Þ

where GBWij is the value of GBW for the j-th integrator in thei-th stage.

0 10 20 30 40 50 60 70 80 90 10055

ADC11 (dB)

0 10 20 30 40 50 60 70 80 90 10035

ADC11 (dB)

Fig. 8. SNR vs. finite dc gain error for different values of r; p: (a) Bw¼20 MHz and (b) Bw¼40 MHz.

4.4. Comparative study and verification by simulations

In order to verify the theoretical expressions derived in previoussection, the ΣΔMs under study were compared and simulated usingSIMSIDES – a time-domain behavioral simulator for ΣΔMs [15]. Tomake a fair comparison, the same ideal conditions, i.e. r¼p wereassumed, and the values of OSR for each modulator were computedfrom (6)–(8), so that the same ideal IBN is achieved in all cases. The

same embedded quantizers were used in all ΣΔMs under study,considering 4-bit quantization in both stages. Two values of signalbandwidths were simulated, Bw ¼ 20;40 MHz and a 1-MHz inputtone with amplitude �7 dB below quantization full-scale range wasapplied in all cases. For the sake of simplicity, only the effect oferrors associated with the front-end (CT) integrators – which arecommon in all the ΣΔM architectures in Figs. 3 and 4 – have beentaken into account in the simulations.

200 400 600 800 1000 1200 1400 1600 1800 200055

GBW 11 (MHz)

100 200 300 400 500 600 700 800 900 100030

GBW 11 (MHz)

Fig. 9. SNR vs. GBW for different values of r; p: (a) Bw¼20 MHz and (b) Bw¼40 MHz.

−20 −15 −10 −5 0 5 10 15 2050

eCT11 (%)

−20 −15 −10 −5 0 5 10 15 2035

eCT11 (%)

Fig. 10. Effect of mismatch on SNR considering different values of r; p: (a) Bw¼20 MHz and (b) Bw¼40 MHz.

Fig. 8 shows the impact of finite dc gain error of the first Gm-Cintegrator for the ΣΔMs under study. Note that both theoreticalpredictions and simulation results are in good agreement, showingthat the DS MR H-ΣΔM is less sensitive to the impact of this error,regardless of the value of r, p and Bw.

The impact of GBW is illustrated in Fig. 9, highlighting a goodmatching between theory and simulations. The worst performanceis obtained by the US MR H-ΣΔM, while a similar degradation isroughly achieved by both DS MR H-ΣΔM and SR CT-ΣΔM. Indeed,the latter features a higher robustness against the impact of GBWin the first integrator. Finally, Fig. 10 shows the effect of circuit

element tolerances in the time constant of the front-end Gm-Cintegrator. It can be noted how both theoretical calculationsand simulations demonstrate that the DS MR H-ΣΔM achievesthe largest robustness against mismatches, getting better as both pand Bw increase.

5. Case study: a Gm-C/SC cascade 2–2 DS MR H-ΣΔM

As a case study, Fig. 11 shows a conceptual schematic of themodulator in Fig. 3(b). The front-end (CT) stage is realized using

Fig. 11. Conceptual Gm-C/SC schematic of the modulator in Fig. 3(c).

Table 1Loop filter coefficient implementation of Fig. 11.

Transconductancesgm1 ¼ 4gmu , gm2 ¼ gmu , gm3 ¼ 10gmu , gm4 ¼ 4gmu , gm5 ¼ 16gmu

CapacitancesGm-C Integ. C1 ¼ gm1=f s1, C2 ¼ gm4=f s1SC Integ. Cs1 ¼ Cs4 ¼ 0:4 pF, Cs2 ¼ Cs3 ¼ 0:1 pF, Cs5 ¼ 0:2 pF, Ci1 ¼ Ci2 ¼ 0:4 pFVoltage-to-current converters and feedback DACsR¼ 1=gm1 ¼ 3:3 kΩ, IDAC1 ¼ 4gmuVFS ¼ 300 μA, IDAC2 ¼ 2gmuVFS ¼ 150 μA

Gm-C integrators. All transconductors can be tuned in order tokeep the time constants, C=gm, unchanged over C variations.Table 1 shows the values of nominal loop filter transconductances,gmi (expressed in terms of the unitary transconductance, gmu) aswell as the capacitances, Ci, used to realize both Gm-C and SCintegrators. Note that an extra feedback branch between theoutput and the input of the front-end quantizer and two additionalD-latches are included in order to compensate for the excess loopdelay [1]. This extra branch forces modifying the loop filtercoefficients in order to obtain the ideal NTF given in (5). Theback-end (DT) stage – realized with SC circuits – is a conventionalsecond-order topology based on two feedback paths. Both stagesinclude multi-level quantizers – 3-level in the front-end stage and

5-level in the back-end stage – in order to benefit from the extralevel provided by fully differential implementation of theembedded flash ADCs.

The Full-Scale (FS) reference voltage, VFS, is 1 V. Feedback DACs inthe CT front-end stage are implemented as current steering NRZ 3-level DACs (named IDACs in Fig. 11) because of their potential high-speed operation and the convenience to interface with the Gm-Cloop filter. The output currents provided by both IDACs are alsoshown in Table 1. An additional voltage-mode 3-level DAC, namedVDAC, is required in the inter-stage path. The digital cancellationlogic is implemented as described in Section 2.

Fig. 12 shows the output spectra of the modulator in Fig. 11for different values of p, considering a sampling frequency of the

105 106 107 108−200

−160

−120

Frequency (Hz)

105 106 107 108−200

−160

−120

Frequency (Hz)

105 106 107 108−200

−160

−120

Frequency (Hz)

Fig. 12. Output spectra for (a) p¼3, (b) p¼4, and (c) p¼5.

front-end stage of f s1 ¼ 1 GHz and including thermal noise corre-sponding to gmu ¼ 75 μA=V. Ideally, the modulator is able to digitizesignals with Bw from 5 MHz to 60 MHz and an effective resolutionranging from 9 to 16 bits. According to (7), these specifications can besatisfied for OSR1A ½8;128� and p¼ ½2;3;4;5;6�. This is illustrated inFig. 13 that represents IBN vs. Bw (Fig. 13(a)) and IBN vs. OSR1 (Fig. 13(b)) for different values of p. In this case, three values of fs1 areconsidered, f s1 ¼ 1 GHz, 500 MHz and 333 MHz. The values of theGm-C integration capacitors, C1;2 are changed according to theexpressions shown in Table 1, by using a switchable bank of threeunit capacitances of value Cu¼1.2 pF. The sampling frequency of theSC back-end stage can be reconfigured through a programmableclock-phase generator, such that f s2 ¼ f s1=p. Both clock-phase gen-erators are synthesized and controlled by a single master clock –

generated by a digital PLL-based synthesizer whose reference fre-quency is fs1. This is conceptually depicted in Fig. 14, where clockphases of both CT and SC stages are shown for different values of p.Fig. 15 shows the effect of finite OTA dc gain of the Gm-C integratorsconsidering different signal bandwiths and values of p, where it canbe seen that a finite gain larger than 30dB is enough to satisfy therequired specifications. The effect of finite GBW of the front-endintegrator is illustrated in Fig. 16, considering a sampling frequency of1GHz in the CT stage. It can be noted that — depending on the valueof the signal bandwidth and p — the required GBW may vary from700MHz to 1.5GHz.

Fig. 17 illustrates the effect of circuit element tolerances in theCT part and capacitor mismatch in the DT part of the modulator, byshowing an histogram of IBN for Bw¼20 MHz and different valuesof p. In order to evaluate the impact of random circuit errors,a 250-sample Monte Carlo simulation was carried out, consideringa standard deviation of 1% in the transconductances and 5% for the

capacitors in the CT part of the circuit, while a 0.1% mismatchvariation was considered for the SC stage. Note that the effectiveresolution degradation is similar to the one obtained in conven-tional cascade ΣΔMs.

Table 2 sums up the modulator performance in terms of themaximum signal bandwidth, Bwmax, that can be handled for a givenvalue of p, fs1 and the Signal-to-(NoiseþDistortion) Ratio (SNDR).The table includes also the circuit-level performance metricsrequired to achieve this modulator performance, including bothnonideal and nonlinear effects, such as the input-referred third-order intercept point (IIP3). In the case of SC integrators, foldedcascade operational amplifiers were considered and their electricalperformance – extracted from transistor-level simulations carried

10 20 30 40 50 60

−95−90−85−80−75−70−65−60−55−50

BW (MHz)

p = 2p= 4= 5

8 16 32 64 128

−95−90−85−80−75−70−65−60−55−50

p = 5p = 6

Fig. 13. IBN for different values of p: (a) IBN vs. Bw and (b) IBN vs. OSR1.

Fig. 14. Clock phase generator. (a) Conceptual block diagram and (b) clock phasesfor different values of the multi-rate ratio.

out in Cadence Spectre – are also shown, considering a 1.2-V 90-nmCMOS technology.

The diverse range of specifications covered by the proposedmodulator is illustrated in Fig. 18 that represents SNDR vs. inputamplitude for f s1 ¼ 1 GHz and considering different values of Bwand p, taking into account all circuit nonideal and nonlinear effectslisted in Table 2. It can be noted that the modulator is able to covera wide region in the resolution-vs.-bandwidth plane.

6. Conclusions

The comparative study presented in this work has demonstratedthat reducing the clock rate in the back-end stages of multi-rate

cascade hybrid continuous-time/discrete-time ΣΔ modulatorsresults in more efficient and robust data-converter architectures,compared to those based on conventional multi-rate (upsampling)topologies. The proposed downsamplingmulti-rate architectures areindeed less sensitive to the effect of the most critical errormechanisms that affect the performance of hybrid cascade ΣΔmodulators. The presented systematic methodology has resulted inthe derivation of closed-form expressions that relate the mainperformance metrics of the modulators under study with theirmain circuit-error model parameters. The resulted expressions canbe used for the design of either single-rate or multi-rate cascadehybrid ΣΔ modulators. This has been illustrated through the high-level design of a multi-rate hybrid Gm-C/SC fourth-order cascade2–2 ΣΔ modulator, intended to digitise signals with a 5-to-60 MHz

0 10 20 30 40 50 60 70−90

Av11 (dB)

)BW=20 MHzBW=30 MHzBW=40 MHzp = 2p = 3p = 4p = 5p = 6

0 10 20 30 40 50 60 70−90

Av12 (dB)

BW=20 MHzBW=30 MHzBW=40 MHzp = 2p = 3p = 4p = 5p = 6

Fig. 15. IBN degradation caused by finite OTA dc gain in (a) 1st and (b) 2nd Gm-C integrators.

500 1000 1500 2000 2500 3000 3500 4000−90

GBW1 (MHz)

Fig. 16. IBN degradation due to GBW of the front-end Gm-C integrator.

−86 −84 −82 −80 −78 −76 −74 −72 −700

IBN (dB)

nts p = 2 p = 4 p = 6

Fig. 17. Monte Carlo simulation for f s1 ¼ 1 GHz and Bw ¼ 20 MHz.

Table 2Modulator performance summary.

Modulatorp 2 3 4 5 6 (2,6) 2fs1 1 GHz 500 MHz 333 MHzBwmax (MHz) 60 50 40 30 25 20 5 10 5SNDR (bits) 7 8.3 8.9 10 10.5 11.5 15 12.5 14.6Clock jitter (ps) 8.9 4 3 1.6 1.2 0.7 0.2 0.9 0.3

Front-end Gm-C integratorDC Gain (dB) 20 20 20 25 25 30 40 35 40GBW (GHz) 0.7 0.8 0.8 1 1.2 1.5 1.5 1.5 1.5IIP3 (dBV) 10 13 15 18 20 25 35 30 35Input swing 500 mVOutput swing 500 mV

Second Gm-C integrator and loop-filter transconductancesDC Gain (dB) 20 20 20 25 25 30 40 35 40GBW (MHz) 200 250 250 300 350 400 500 450 500IIP3 (dBV) 5 7 7 10 12 15 15 15 15Input swing 500 mVOutput swing 500 mV

SC integrators (transistor-level performance)DC gain (dB) 47gm (mA/V) 4.4Phase margin 73.41Output current (μA) 404Input parasitic cap. (pF) 0.2Out. parasitic cap. (pF) 0.1Output swing (mV) 700

−80 −70 −60 −50 −40 −30 −20 −10 0−10

Amplitude (dBFS)

Fig. 18. SNDR vs. amplitude for different values of Bw and p.

reconfigurable bandwidth, 7-to-15 bit scalable resolution and adap-tive power consumption. The analytical procedures as well as thearchitectural and circuital techniques presented in this work arebeing applied to the design of reconfigurable low-pass/band-passΣΔ RF-to-digital converters in software-defined-radio receiversintegrated in nanometer CMOS technologies.

References

[1] M. Ortmanns, F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion:Fundamentals, Performance Limits and Robust Implementations, Springer,2006.

[2] P. Morrow, et al., A 0:18 μm 102 dB-SNR Mixed CT SC Audio-Band ΔΣ ADC,IEEE ISSCC Digest of Technical Papers, February 2005, pp. 177–178.

[3] K. Nguyen, et al., A 106 dB SNR Hybrid Oversampling ADC for Digital Audio,IEEE ISSCC Digest of Technical Papers, February 2005, pp. 176–177.

[4] B. Putter, A 5th-Order CT/DT Multi-Mode ΣΔ Modulator, IEEE ISSCC Digest ofTechnical Papers, February 2007, pp. 244–245.

[5] S. Kulchycki, et al., A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascade ΣΔ modulator, IEEE J. Solid-State Circuits 43 (April)(2008) 796–804.

[6] M. Choi, et al., A 101-dB SNR hybrid delta-sigma audio ADC using postintegration time control, in: Proceedings of the 2008 IEEE Custom IntegratedCircuits Conference (CICC), 2008, pp. 89–92.

[7] F. Colodro, A. Torralba, Multirate ΣΔ modulators, IEEE Trans. Circuits Syst. II:Analog Digital Signal Process. 49 (March) (2002) 170–176.

[8] L. Bos, et al., Multirate cascaded discrete-time low-pass ΔΣ modulator forGSM/Bluetooth/UMTS, IEEE J. Solid-State Circuits 45 (June) (2010) 1198–1208.

[9] M. Ortmanns, et al., Multirate cascaded continuous-time ΣΔ modulators, in:Proceedings of the 2002 IEEE International Symposium on Circuits andSystems (ISCAS'02), May 2002, pp. 4225–4228.

[10] J.G. García-Sánchez, J.M. de la Rosa, Multirate downsampling hybrid CT/DTcascade sigma–delta modulators, IEEE Trans. Circuits Syst. I: Regular Pap. 59(2) (2012) 285–294.

[11] R. del Río, et al., CMOS Cascade ΣΔModulators for Sensors and Telecom: ErrorAnalysis and Practical Design, Springer, 2006.

[12] P. Benabes, Accurate time-domain simulation of continuous-time sigma–deltamodulators, IEEE Trans. Circuits Syst. I: Regular Pap. 56 (October) (2009)2248–2258.

[13] S. Pavan, Systematic design centering of continuous time oversamplingconverters, IEEE Trans. Circuits Syst. II: Express Briefs 57 (March) (2010)158–162.

[14] H. Kwan, et al., Design of hybrid continuous-time discrete-time delta–sigmamodulators, in: Proceedings of the 2008 IEEE International Symposium onCircuits and Systems (ISCAS'08), May 2008, pp. 1224–1227.

[15] J. Ruiz-Amaya, et al., High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models, IEEE Trans. Circuits Syst. I: Regular Pap. 51(September) (2005) 1795–1810.

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