Post on 27-Mar-2018
Jan M. RabaeyUC Berkeley EE241
EE241 - Lecture 2
Technology Scaling
Jan M. RabaeyUC Berkeley EE241
Digital GateBasic Properties
• ∆ Swing• Noise Margins⇒ Robustness• tPLH, t PHL• Power Consumption⇒ Power-Delay-Product• Area⇒ Density
Jan M. RabaeyUC Berkeley EE241
Basic CMOS Gate
CL
OutIn
Ip
In
Properties• Output levels determined by supply• Large noise margins• ∆Qin/∆Vin is small• Performance loss at low voltages
Jan M. RabaeyUC Berkeley EE241
CMOS Performance
Jan M. RabaeyUC Berkeley EE241
Power Dissipation
Jan M. RabaeyUC Berkeley EE241
Scaling Models
α: technology scaling factorε: electrical field scaling factor
Jan M. RabaeyUC Berkeley EE241
Scaling Models
Jan M. RabaeyUC Berkeley EE241
Current Scaling Scenario
[Davari95]
Note: Delays scale similarly if wp, wn and Cwire scale in the same way.
Jan M. RabaeyUC Berkeley EE241
Issues in Scaling• Reliability!
Break down, hot electron effects• Cost• Density, Speed, Power
Two Scenario’s are emerging• High speed scenario• Low power scenario
different voltage scaling trajectories
Note: Voltage cannot be scaled indiscriminately!
Jan M. RabaeyUC Berkeley EE241
High-Speed versus Low-Power Scenario’s
[Davari95]
Jan M. RabaeyUC Berkeley EE241
Scaling Guidelines for Next Decade
Jan M. RabaeyUC Berkeley EE241
More in depth ...
Jan M. RabaeyUC Berkeley EE241
Current Equationsfor Long Devices
Jan M. RabaeyUC Berkeley EE241
Limitations of Scaling Model
Mobility degradation
VelocitySaturation
Jan M. RabaeyUC Berkeley EE241
Short-Channel MOS Model
Jan M. RabaeyUC Berkeley EE241
Effect of Velocity Saturation
Jan M. RabaeyUC Berkeley EE241
Source and Drain Resistance
The High-SpeedScenario
Source and drain resistances become comparable to channel resistance
Jan M. RabaeyUC Berkeley EE241
Effect of RS
Jan M. RabaeyUC Berkeley EE241
Mean Reasons for RSD Increases
Jan M. RabaeyUC Berkeley EE241
Lightly Doped Drain (LDD) Solution
n++n+n+
n++ As
P
ProLow peak fieldalso reduces junction leakage
ConIncreased series S and D resistance
Tradeoff between performance and reliability
Jan M. RabaeyUC Berkeley EE241
Performance versus Reliability
[Davari95]
Techniques to improveS/D junctions more abrupt - reduces spreadingsilicide S/D regions
Jan M. RabaeyUC Berkeley EE241
Related: Oxide Conduction andBreakdown
Jan M. RabaeyUC Berkeley EE241
The Low-Power Scenario
Reducing VT improves performance (at lower voltages)
0.25µm CMOS delay versus threshold voltage [Davari95]
Jan M. RabaeyUC Berkeley EE241
Issues in Thresholds
Jan M. RabaeyUC Berkeley EE241
Weak Inversion - Tail Current
Jan M. RabaeyUC Berkeley EE241
Example
Jan M. RabaeyUC Berkeley EE241
Sub-threshold SlopeAs a function of channel length
Jan M. RabaeyUC Berkeley EE241
Impact of sub-threshold currents
Jan M. RabaeyUC Berkeley EE241
Threshold Variations
Jan M. RabaeyUC Berkeley EE241
Impact of Channel-Length on VT
Reason : Depletion region extends
under gate
Solution: Non-uniform channel
doping profile
[Davari95]
Jan M. RabaeyUC Berkeley EE241
Threshold Control
Solutions:multiple thresholds on a chipback gate biasing reduce subthreshold current
Delay variations due to threshold
voltage shift [Sakurai&Kuroda]
Jan M. RabaeyUC Berkeley EE241
Reducing Sub-threshold Currents
Jan M. RabaeyUC Berkeley EE241
Impact of Technology
Jan M. RabaeyUC Berkeley EE241
Bulk CMOS versus SOI
Jan M. RabaeyUC Berkeley EE241
A Rosy Future?
Jan M. RabaeyUC Berkeley EE241
Interconnect
Jan M. RabaeyUC Berkeley EE241
Scaling of Wire Properties
CV2 x3 x2 yx2
CV2/RC x3 x4 x4/y
Jan M. RabaeyUC Berkeley EE241
Advanced Wiring Scheme
Example of wiring scheme needed by future high-performance processorsto minimize delays due to wire resistance [Davari95]
Jan M. RabaeyUC Berkeley EE241
Example: Intel 0.25 micron Process
5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric