EE241 - Lecture 2 - Cho, Jun Dong ??? Sungkyunkwan...

Jan M. RabaeyUC Berkeley EE241

EE241 - Lecture 2

Technology Scaling


Digital GateBasic Properties

• ∆ Swing• Noise Margins⇒ Robustness• tPLH, t PHL• Power Consumption⇒ Power-Delay-Product• Area⇒ Density


Basic CMOS Gate

CL

OutIn

Ip

In

Properties• Output levels determined by supply• Large noise margins• ∆Qin/∆Vin is small• Performance loss at low voltages


CMOS Performance


Power Dissipation


Scaling Models

α: technology scaling factorε: electrical field scaling factor


Scaling Models


Current Scaling Scenario

[Davari95]

Note: Delays scale similarly if wp, wn and Cwire scale in the same way.


Issues in Scaling• Reliability!

Break down, hot electron effects• Cost• Density, Speed, Power

Two Scenario’s are emerging• High speed scenario• Low power scenario

different voltage scaling trajectories

Note: Voltage cannot be scaled indiscriminately!


High-Speed versus Low-Power Scenario’s

[Davari95]


Scaling Guidelines for Next Decade


More in depth ...


Current Equationsfor Long Devices


Limitations of Scaling Model

Mobility degradation

VelocitySaturation


Short-Channel MOS Model


Effect of Velocity Saturation


Source and Drain Resistance

The High-SpeedScenario

Source and drain resistances become comparable to channel resistance


Effect of RS


Mean Reasons for RSD Increases


Lightly Doped Drain (LDD) Solution

n++n+n+

n++ As

P

ProLow peak fieldalso reduces junction leakage

ConIncreased series S and D resistance

Tradeoff between performance and reliability


Performance versus Reliability

[Davari95]

Techniques to improveS/D junctions more abrupt - reduces spreadingsilicide S/D regions


Related: Oxide Conduction andBreakdown


The Low-Power Scenario

Reducing VT improves performance (at lower voltages)

0.25µm CMOS delay versus threshold voltage [Davari95]


Issues in Thresholds


Weak Inversion - Tail Current


Example


Sub-threshold SlopeAs a function of channel length


Impact of sub-threshold currents


Threshold Variations


Impact of Channel-Length on VT

Reason : Depletion region extends

under gate

Solution: Non-uniform channel

doping profile

[Davari95]


Threshold Control

Solutions:multiple thresholds on a chipback gate biasing reduce subthreshold current

Delay variations due to threshold

voltage shift [Sakurai&Kuroda]


Reducing Sub-threshold Currents


Impact of Technology


Bulk CMOS versus SOI


A Rosy Future?


Interconnect


Scaling of Wire Properties

CV2 x3 x2 yx2

CV2/RC x3 x4 x4/y


Advanced Wiring Scheme

Example of wiring scheme needed by future high-performance processorsto minimize delays due to wire resistance [Davari95]


Example: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric

EE241 - Lecture 2 - Cho, Jun Dong ??? Sungkyunkwan...

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