326 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 9, SEPTEMBER 1998

Schottky-Clamped NMOS Transistors Implementedin a Conventional 0.8-m CMOS Process

Feng-Jung Huang and Kenneth K. O,Member, IEEE

Abstract—An 0.8-�m n-channel MOSFET with a TiSi2-SiSchottky clamped drain-to-body junction (SCDR) and an n+

implanted standard source structure have been fabricated in aconventional 0.8-�m salicide CMOS process without any processmodifications. The SCDR should be useful for reducing suscepti-bility for latch-up in integrated CMOS RF power amplifiers andswitches where drain to p-substrate junctions can be forwardbiased during normal operations. Output I–V characteristics ofthe devices are the same as those of conventional MOSFET’s,while parasitic lateral n+-drain/p-substrate/n+-source bipolartransistor measurements showed significantly reduced currentgains because the Schottky barrier diode which does not injectminority carriers (electrons) to the p-substrate base clamps then+ drain-to-p-substrate guard-ring diode connected in parallel.

I. INTRODUCTION

SCHOTTKY barriers and their RF applications have beenstudied extensively [1], [2]. An insulated gate field effect

transistor using Schottky barrier contacts for source and drainwas first proposed in 1968 [3]. Recently, Schottky contacts [4]and MOS transistors using a Schottky barrier as a drain [5]were studied using foundry CMOS processes. The transistorssuffer from high drain to substrate leakage current and lowbreakdown voltages [5], [6] as well as reduced drain currents[5]. In NMOS RF amplifiers with a tuned load, especiallywhen the supply voltage is low, it is desirable for drain nodesof some transistors to swing below GND to increase theoutput power level. Unfortunately for integrated RF amplifiers,this forward-biases the p-substrate-to-n-drain junction(s) andmay trigger latch-up. A similar requirement exists for RFswitches. In this paper, a Schottky clamped drain (SCDR)n-channel MOSFET fabricated in a foundry 0.8-m SalicideCMOS process with radically reduced parasitic bipolar currentgains is described. In SCDR transistors, the parasitic n-drain/p-substrate/n-well bipolar transistor actions of CMOStechnologies will be greatly reduced since the Schottky barrierwhich does not inject minority carriers clamps the n-drain-to-p-substrate junction. This, in turn, should reduce current gainsof the parasitic drain/p-substrate/n-well transistors, and lead tosignificantly reduced latch-up susceptibility. Implementationof the structure requires simple changes to an NMOS layoutwithout any process modifications. Unlike the previous effort

Manuscript received December 19, 1997; revised May 18, 1998. Thiswork was supported by an NSF Faculty Early Career Development Award(MIP-9703214).

The authors are with the Department of Electrical and ComputerEngineering, University of Florida, Gainesville, FL 32611 USA (e-mail:fjj@tec.ufl.edu).

Publisher Item Identifier S 0741-3106(98)06627-0.

Fig. 1. A cross section of an SCDR-MOSFET.

[5], the SCDR NMOS transistor characteristics are almostcomparable to those of conventional transistors.

II. DEVICE STRUCTURE AND FABRICATION

A cross section of the device structure is shown in Fig. 1.The gate length and channel width are 0.8 and 12m,respectively. The SCDR transistors are fabricated in a foundry0.8- m Salicide CMOS process similar to those in [8] and[9]. As stated earlier, implementation of the devices requiressimple layout changes and does not require any processmodifications. A major difference between conventional andSCDR transistors is that the SCDR devices are asymmetric.On the drain side, the source–drain implantation was partiallymasked to form a TiSi-Si Schottky barrier contact and an n-type guard ring. The SCDR width is 12m and the lengthis 3.2 m (see Fig. 1) with a 1.2-m-wide n guard bandalong the polysilicon gate and a 0.8-m-wide n guard bandalong the other three edges of the Schottky clamping diode.The n guard band along the polysilicon gate acts as aconventional drain. Along with this, utilizing a conventionalsource structure preserves the normal MOS transistor charac-teristics. In addition, the n guard band/ring at edges of theSchottky clamp reduces electric fields at corners which in turnreduces the reverse leakage and raises the breakdown voltagewhile retaining normal Schottky barrier characteristics [7]. Thejunction capacitance of the SCDR should be approximately25% higher than that of the conventional junction.

III. RESULTS AND DISCUSSION

Fig. 2(a) shows output – characteristics of 0.8-mSchottky-clamped-drain and standard NMOS devices.Fig. 2(b) shows versus curves of the sametransistors. The output and turn-on characteristics of thetransistors are identical. The subthreshold slope is about100 mV/decade for both devices. Fig. 3 shows the forward

0741–3106/98$10.00 1998 IEEE

HUANG AND O: SCHOTTKY-CLAMPED NMOS TRANSISTORS 327

(a)

(b)

Fig. 2 Measured (a)IDS–VDS and (b)IDS–VGScharacteristics for conven-tional and (b) SCDR-MOS transistors.

Fig. 3. Diode characteristics of n+-drain-to-p-substrate, Schottky clampeddrain-to-p and Schottky drain-to-p junction.

and reverse characteristics of an n-drain-to-p-substratejunction, a Schottky-barrier-drain-to-p junction [5], and aSchottky-clamped n-drain-to-p-junction. Lengths and widthsof these junctions are at the minimum for implementingrespective MOSFET structures. For the Schottky barrierdrain, the reverse leakage current at a 5-V reverse bias is 270nA and the junction breakdown voltage is 6 V [5]. When theguard band is added to form an SCDR, the reverse leakagecurrent reduces to 4 nA and the junction breakdown voltage

Fig. 4. Current gain(�) versusVBE plots of drain/p-substrate/n+-sourceparasitic n-p-n bipolar transistors for conventional and SCDR-MOS transis-tors.

is increased to 14 V. These are starting to be comparable tothose of conventional n-drain-to-p-substrate junctions.

Fig. 4 shows current gain versus curves of lateraldrain/p-substrate/source parasitic structures for conventionaland SCDR transistors. This structure is characterized insteadof the drain/p-substrate/n-well parasitic structures, since thisstructure should have a higher current gain or should be aworse case. The lateral base width is 0.8m. As expected,the current gain of the SCDR transistors are significantly lessthan that of the conventional transistor. For ’s rangingfrom 0 V to 1.0 V, the current gain is substantially less thanthe unity. At ’s of 0.5 and 1.0 V, the current gains are 1.5

10 and 0.3, respectively. These in turn should greatlyreduce the latch-up susceptibility in integrated CMOS RFpower amplifiers.

IV. CONCLUSION

An n-channel MOSFET with a Schottky clamped drain hasbeen demonstrated. Fabrication of the structure requires noadditional mask or modifications of the salicide CMOS processutilized for this work. By partially masking the source–drainimplantation in the drain, a structure consisting of a TiSi-SiSchottky barrier contact and an nimplanted guard ring isformed to obtain transistor characteristics identical to thoseof conventional MOSFET’s. Using this structure, it is pos-sible to greatly reduce the parasitic bipolar effect in thelateral n -drain/p-substrate/n-well structure. This should en-able forward-biasing of drain-to-p-substrate junctions in RFpower amplifiers and switches for an increased power handlingcapability with significantly reduced latch-up susceptibility.Lastly, the reverse leakage and breakdown voltage of theSchottky clamped n-p-substrate junction are starting to beclose to those of conventional junctions.

REFERENCES

[1] B. L. Sharma, Metal-Semiconductor Schottky Barrier Junctions andTheir Applications. New York: Plenum, 1984.

[2] S. Mollenkopf and G. M. Rebeiz, “A 22 GHz MIC active re-ceiver/radiometer,”IEEE MTT-S Int. Microwave Symp. Dig., 1994,vol. 3, pp. 1347–1350.

328 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 9, SEPTEMBER 1998

[3] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect transistor using Schottky Barrier contacts as source and drain,”Proc. IEEE, vol. 56, pp. 1400–1402, 1968.

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[8] S. Penget al., “A manufacturable 2.0-micron pitch three-level-metal in-terconnect process for high performance 0.8-micron CMOS technology,”in Proc. Symp. VLSI Tech., June 1990, pp. 25–26.

[9] R. A. Chapmanet al., “A 0.8-�m CMOS technology for high perfor-mance logic applications,” inIEDM Tech. Dig., pp. 362–365, 1987.