978-1-4673-6732-5/15/$31.00 ©2015 IEE

Timing Measurement

Takeshi Chujo, Daiki HirabayasTakuya Arafune, Shohei Shibuy

Shu Sasaki, Haruo Kobayashi Division of Electronics and Informa

Gunma University, Kiryu 376-8515 J k_haruo@el.gunma-u.ac.jp

phone: 81-277-30-1788 fax: 81-277-3

Abstract— This paper describes design and i

a multi-bit delta-sigma (ΔΣ) Time-to-Digital with Data-Weighted-Averaging (DWA) algorFPGA. I/O interfacing circuits such as doublememory interfaces are very important, and thequality test is challenging. We propose here simfor measuring digital signal timing of I/O inwith high resolution and good accuracy. Wapplications of ΔΣmodulators (for fine-timing-routput, and simple circuitry) and with multi-bitshort testing time). However, the multi-bit ΔΣ Tdelay mismatches among delay cells. Then we the DWA algorithm for the delay cells in orproblem. Our experimental results showed algorithm improved the overall multi-bitΔΣ TDC

Keywords— Time-to-Digital Converter; TimAnalog FPGA; Delta-Sigma

I. INTRODUCTION

I/O interfacing circuits such as double-dmemory interfaces are very important, andhigh-quality test is challenging. [1] This simple test circuitry for measuring digital sighigh resolution and good accuracy. We focDigital Converter (TDC) applications of dmodulators (for fine-timing-resolution, digisimple circuitry) and with multi-bit architetesting time). [2]-[10]

A multi-bit ΔΣ TDC suffers from delay midelay cells, but here we propose to apply theaveraging (DWA) algorithm [8] for the delaysolve this problem. In this paper we show impmulti-bit ΔΣ TDC with DWA as a Bui(BOST) and we present experimental resultalgorithm improves the overall multi-bit ΔΣ T

II. FLASH TDC

A TDC can be used to measure digital sigarchitecture of a basic flash-type TDC is showIt consists of a delay-line using delay cells inand an array of flip-flops. The input Start sigthe delay cells, which are connected in seriessignal is connected to a D input terminal inarray. Start signal is delayed only by an inte

EE

t BOST With Multi-Bit Delta-S

shi ya

atics, Japan 0-1707

Masanobu Tsuji , RyMasafumi Watanabe, No

Sadayoshi Umeda, HideySemiconductor Technology Acad

Yokohama 222-003

Koshi Sato Hikari Science, J

implementation of Converter (TDC) rithm on analog e-data-rate (DDR) eir low-cost, high-mple test circuitry nterfacing circuits e focus on TDC resolution, digital t architecture (for TDC suffers from propose to apply

rder to solve this that the DWA

C linearity.

me Measurement;

data-rate (DDR) d their low-cost,

paper describes gnal timing with cus on Time-to-

delta-sigma (ΔΣ) ital output, and ecture (for short

ismatches among e data-weighted-

y cells in order to plementation of a ilt-Out Self-Test s that the DWA

TDC linearity.

gnal timing. The wn in Fig.1 [11]. n the signal path

gnal passes along s. And then each n the D flip-flop egral multiple of

the buffer delay τ . The state of eacthe rising edge of the Stop signaltime delay between the signals to a buffer delay. That is, the output obtained as a thermometer code (unthe time delay between Start and Sdelay is obtained as a digitalthermometer-code-to-binary encode

Fig.1 Flash-type

The flash-type TDC has the admeasure a single-event input, howthat the time resolution is determinand its circuitry is large.

III. DELTA-SIG

A. Single-bit Delta-Sigma TDC:

We consider here how to measure trepetitive digital signals (or clocks)the measurement. As shown in Figlong, the probability (or density) ofhigh. Although arbitrary digital measured with the ΔΣ TDC, it can clocks where time resolution is measurement time. The longer thefiner the time resolution is.

Fig.3 shows a single-bit ΔΣ TDCa delay element, three multiplexersa comparator. Its inputs are two CLK2 with the same frequency, difference T of their clock timing TDC output as the time difference

Sigma TDC

yoji Shiota oriaki Dobashi yuki Nakamura demic Research Center 33 Japan

Japan

ch D flip-flop is latched by . This circuit converts the certain number of steps of from the D flip- flop is

nary code) output showing Stop signals, and this time l output Dout using a er.

e TDC.

dvantage of being able to wever its disadvantages are ned by the delay value τ ,

GMA TDC

the time delay between two , and we use a ΔΣ TDC for g.2, the time delay ΔT is f the TDC output of “1” is timing signals cannot be measure the timing of two inversely proportional to measurement time is, the

C architecture. It consists of s, an analog integrator, and

clock signals CLK1 and and it measures the time edges. In this design, the

is positive when the CLK1

rising edge is earlier than CLK2 and it is neCLK1 edge is later. The number of 1’s ofoutput for a given time is proportional to thebetween CLK1 and CLK2 when CLK1 is earlnumber of 0’s is proportional to their time CLK2 is earlier.

Fig. 2 Single-bit ΔΣ TDC input and output

Fig.3 Single-bit ΔΣ TDC.

B. Multi-bit Delta-Sigma TDC: Next we desΔΣ TDC, and Fig.4 shows its architecture. Inmulti-bit ΔΣ TDC, a flash-type A/D convertarray of comparators) is used instead of a sinand its digital output is in a thermometer coformat. The same number of delay elementcomparators are used: in case of an N-bit Δcomparators and delay elements are used. Sinoutput INTout is digitized with an array offlash ADC without an encoder), its outputhermometer code format. Then the digitthermometer code is fed into select signalsmultiplexers.

Note that the integrator output INTout ifine voltage resolution with an array of chence the multi-bit ΔΣ TDC can obtain finecompared to the single-bit one for a given meIn other words, the multi-bit ΔΣ TDCmeasurement time for a given time resolutionbit one, which means lower testing cost. Howbit ΔΣ TDC may suffer from mismatches am

CLK1

CLK2

Dout0 or 1

CLK1

CLK2

Dout # of 1’s is proportional to ΔT

ΔT ΔT ΔT

ΔΣTDC

ΔTshort

long

# of 1’s

many

few

0 1 0 1 0 1 0 1

Dout0 1 0 0 0 0 1 0

0 1 1 1 1 0 1 1

egative when the f the comparator e time difference lier. Similarly the difference when

t interfaces

scribe a multi-bit n the case of the ter (precisely, an ngle comparator, ode (unary code) ts as that of the ΔΣ TDC, nce the integrator f comparators (a ut Dout is in a tal output in a s of an array of

is digitized with comparators, and e time resolution easurement time.

C takes shorter n than the single-wever, the multi-

mong delay units,

which degrades the TDC linearitymulti-bit ΔΣ ADC [7]).

Fig.4 Multi-bit Δ

C. Multi-bit Delta-Sigma TDC Withproposal of applying the DWA amulti-bit ΔΣ TDC for its linearityarea in Fig.5 shows a digital-to-timTDC, and the comparators outputs corresponding delay cells in the Dvariation among delay cells in actuanonlinearity error of the overall Tapply the DWA algorithm to the mu

The boxed area in Fig.5 shows delay cells controlled digitally (or DTC) and the outputs of the comselect the corresponding delay cells value variation among delay cellscauses the nonlinearity error of thpropose to apply the DWA algorithto noise-shape the mismatch effecFig.5 shows an operation of the selection of the delay cells whose when the flash ADC (without encod3, 4, 6, ... sequentially. In other wrotation shift of the ΣΔ TDC thermometer code as follows: 1. The first input starts at the delay c2. Next input starts at the position o

4 (the previous input) from the pcell 0.

3. Next input starts at the delay ceprevious input) from the previous

Fig.7 shows an operation example wa multi-bit ΔΣ TDC. Generalized algorithm description iwe have N delay elements (delay cecell N-1) and a pointer P(n) at time 1. Suppose that the input data C1(

(where n = 0, 1, 2, 3, 4, ...).

0 1 0

0 0 0

1 1 1 0

y (which is similar to the

Σ TDC.

h DWA: Next we show our algorithm [12]-[15] to the y improvement. The boxed

me converter (DTC) in a ΔΣ are feedback and select the

DTC. There is delay value al circuits, and it causes the

TDC. Then, we propose to ultibit ΔΣ TDC. [7]-[10]

a delay line composed of a digital-to-time converter: mparators are fed-back to in the DTC. There is delay

s in actual circuits, and it he overall TDC. Then, we hm to the multi-bit ΣΔ TDC cts among the delay cells. DWA logic; it shows the upper path is delayed by τ der) outputs are 4, 3, 2, 2, 5,

words, it performs the right comparator outputs in a

cell 0. f the delay cell 4 shifted by previous position the delay

ell 7 that shifted by 3 (the position Cell 4, and rotated.

without and with DWA for

s as follows: ell 0, delay cell 1, ..., delay n (where P(0) = 0). (n) = Cn at time n

2. Select Cn delay cells of modN(P(n)+1), modN(P(n)+2), ..modN(P(n) + Cn).

3. Set the pointer at time n+1 to P(n+1) = modN(P(n)+Cn).

The above procedure is repeated for n = 0, 1,ΔΣ operation (Fig.8), and suppresses errorsdelay cell mismatches) in DC component andhigh frequency side (Fig.9).

Fig.5. 3-bit ΔΣ TDC with DWA log

Fig.6. DWA algorithm

Fig.7. Delay cell selection without and w

, 2, ... This is the s (caused by the d pushes it in the

gic

with DWA.

Fig.8. Equivalent circuit

Fig.9. First-order noise-shapingeffects with D

IV. ANALOG FPGA IM

We have implemented the 3-bit Δanalog FPGA (Programmable Cypress Semiconductor), and its pshown in Fig.11, the core circuit emstructure. Each delay cell consists oa buffer; the value of each resistor and individually to give delay variDWA effectiveness can be evaluusage or no usage of DWA by a com

Fig.10. 3-bit ΔΣ TDC implementat

t to DWA logic.

g of delay cell mismatch

DWA.

MPLEMENTATION

ΔΣ TDC in Fig.3 using an System-on-Chip: PSoC,

hoto is shown Fig.10. As mploys pseudo differential

of a resistor, a capacitor and can be changed externally

iation intentionally so that uated. Also we can select mmand.

ion with an analog FPGA

Fig.11. Core circuit design of 3-bit ΔΣ TDC with

V. MEASUREMENT RESULT

Figures 12, 13, 14 and 15 show the measurem3-bit ΔΣ TDC with and without DWA fovariation cases. We see from them that the improves the overall multi-bit ΔΣ TDC lineari

In the analog FPGA implementation of theeach delay (τ1, τ2,…, τ7) is implemented withand capacitor. Each resistor of different value vary each delay (or cause delay mismatches)demonstrate the effectiveness of the DWA algvalues (Ω) for delays (τ1, τ2,…, τ7) in each cfollows:

Case 1 (Fig. 12) : 75, 150, 75, 75, 75,

Case 2 (Fig. 13) : 75, 75, 150, 75, 75,

Case 3 (Fig. 14) : 75, 75, 75, 150, 75,

Case 4 (Fig. 15) : 220, 75, 150, 220, 75,

The number of the TDC output data is measured data in Figs. 12 - 15.

Note that the delay value for R=75Ω is arowhen all delays are 110ns, the input range is660ns.

We see from Figs. 12-15 that the overall Tdegraded without DWA at the input of the tim

around -550ns in case 1

around -440ns in case 2

around 0ns in case 3, and

in the whole input range in case4.

However it is recovered by adopting DWA al

VI. CONCLUSION We have described multi-bit ΔΣ TDimplementation on an analog FPGA as well results for fast and high accuracy testing of thtwo clocks. We have proposed applying a DWreduce the effects of delay mismatches amongour measurement results validate the effec

an analog FPGA.

TS

ment results of the or several delay DWA algorithm ity.

3-bit ΔΣ TDC, h external resistor can be placed to ) intentionally to gorithm. Resistor case are given as

75, 75

75, 75

75, 75

150, 220

10,000 for the

ound 110ns, and s from -660ns to

TDC linearity is me difference

lgorithm.

DC design and as measurement

e timing between WA technique to g delay cells, and ctiveness of our

proposed approach. Our proposedenable fast and accurate testing, anthem as DFT, BIST or BOST for and testing.

ACKNOWLEDG

We would like to thank K. Wilkinsoof the manuscript.

REFERENC

[1] G. Roberts, F. Taenzler, M BurnSignal IC Test and Measurement,Ed. (2011).

[2] B. Young, K. Sunwoo, A. ElshazlResolution 2.1mW Second-order NConverter with 3.2ns Range inCustom Integrated Circuits, San Jo

[3] D.-W. Jee, Y.-H. Seo, H.-J. PFractional-N Digital PLL with 1IEEE VLSI Circuit Symposium, K

[4] Y. Cao, P. Leroux, W. D. Cock, M1-1 MASH ΔΣ Time-to-Digital CSolid-State Circuits Conference, S

[5] D. Hirabayashi, Y. Osawa, N. H“Phase Noise Measurement withInternational Test Conference, P(Sept. 2013).

[6] Y. Osawa, D. Hirabayashi, N. HarO. Kobayashi, “Phase Noise MeDelta-Sigma TDC”, IEEE Internatand Systems Test Workshop, Porto

[7] S. Uemori, M. Ishii, H. KobayashMatsuura, K. Niitsu, F. Abe, D. HDelta TDC Architecture forMeasurement", IEEE InternationalSystems Test Workshop, Taipei, T

[8] S. Uemori, M. Ishii, H. KobayasDelta TDC Architecture with ImpElectronic Testing: Theory and Apno. 6, pp.879-892 (Dec. 2013).

[9] T. Chujo, D. Hirabayashi, K. SaDelta-Sigma TDC BOST for TimTest Conference, Poster Session, S

[10] Y. Arakawa, Y. Oosawa, H. Ko“Linearity Improvement TechniqTDC for Timing MeasuremenWorkshop on Test and ValidatCircuits, Anaheim, CA (Sept. 2013

[11] Y. Arai, T. Baba, “A CMOS Timfor High-Energy Physics”, IEEE S(1988).

[12] R. Schreier, G. C. Temes, UndeConverters, Wiley-IEEE Press (20

[13] R. Schreier, J. Steensgaard, G. Range Trade-Off in Oversampling22, Trade-Offs in Analog CircToumazou, G. Moschytz, B. Publishers (2002).

[14] Y. Geerts, M.Steyaert, W.SansenSigma A/D Converters, Kulwer Ac

[15] H. San, H. Kobayashi, S. KawakShaping Algorithm of Multi-bit DABandpass ΔΣ AD Modulators”, IEE87-A, no. 4, pp.792-800 (April. 2

d circuits are simple but nd hence we expect to use clock timing measurement

GMENT on for English improvement

ES ns, An Introduction to Mixed- Oxford University Press, 2nd

ly, P. K. Hanumolu, “A 2.4ps Noise-shaped Time-to-Digital

n 1MHz Bandwidth,” IEEE ose (Sept. 2010) ark, J.-Y. Sim, “A 2 GHz

1b Noise Shaping ΔΣ TDC”, Kyoto (June2011). M. Steyaert, “A 1.7mW 11b 1-Converter”, IEEE International

an Francisco (Feb. 2011). Harigai, H. Kobayashi et. al., h Sigma-Delta TDC”, IEEE oster Session, Anaheim, CA

rigai, H. Kobayashi, K. Niitsu, easurement Techniques Using tional Mixed-Signals, Sensors o Alegre, Brazil (Sept. 2014). hi, Y. Doi, O. Kobayashi, T.

Hirabayashi, "Multi-bit Sigma-r Digital Signal Timing l Mixed-Signals, Sensors, and

Taiwan (May 2012). shi, et. al., “Multi-bit Sigma-proved Linearity”, Journal of pplications, Springer, vol. 29,

ato, H. Kobayashi, “Multi-bit ming Test”, IEEE International Seattle, WA (Oct. 2014). obayashi, Osamu Kobayashi,

que of Multi-bit Sigma-Delta nt”, IEEE 3rd International ion of High-Speed Analog 3) me to Digital Converter VLSI Symposium on VLSI Circuits

erstanding Delta-Sigma Data 04). Temes, “Speed vs. Dynamic

g Data Converters,” in Chapter cuit Design, edited by Ch. Gilbert, Kluwer Academic

n, Design of Multi-Bit Delta-cademic Publisher (2002). kami, N. Kuroiwa, “A Noise-AC Nonlinearities in Complex

EICE Trans. on Fundamentals, 2004).

(a) Without DWA

(b) With DWA

(c) INL with and without DWA

Fig.12. Measurement result for the 3-bit ΔΣ TDC

A

(case 1)

(a) Without D

(b) With DW

(c) INL with and wi

Fig.13. Measurement result for the 3-bit

DWA

WA

ithout DWA

t ΔΣ TDC (case 2)

(a) Without DWA

(b) With DWA

(c) INL with and without DWA

Fig.14. Measurement result for the 3-bit ΔΣ T

A

DC (case 3)

(a) Without D

(b) With DW

(c) INL with and wi

Fig.15. Measurement result for the

DWA

WA

ithout DWA

e 3-bit ΔΣ TDC (case 4)