STT-RAM Circuit Design

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STT-RAM Circuit Design MTJ Specs (Update), MTJ Sharing

description

STT-RAM Circuit Design. MTJ Specs (Update), MTJ Sharing. I-STT MTJ Specs (Jianping). UPDATED SPECS R P ≈ 744 Ω TMR ≈ 136% AP→P: 630 μ A Max (breakdown current) 387 μ A for 3ns switching 330 μ A for 5ns switching P→AP: 1.5mA Max (breakdown current) Need more device measurements - PowerPoint PPT Presentation

Transcript of STT-RAM Circuit Design

Page 1: STT-RAM  Circuit Design

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STT-RAM Circuit Design

MTJ Specs (Update),MTJ Sharing

Page 2: STT-RAM  Circuit Design

I-STT MTJ Specs (Jianping)

UPDATED SPECS– RP ≈ 744Ω

– TMR ≈ 136%– AP→P:

● 630μA Max (breakdown current)● 387μA for 3ns switching● 330μA for 5ns switching

– P→AP:● 1.5mA Max (breakdown current)● Need more device measurements

– IWRITE(P→AP)/IWRITE(AP→P): 1.5-2

– 1ns read pulse (P→AP) with 1% chance of write: 220μA● AP→P might be better

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Page 3: STT-RAM  Circuit Design

Maximum Write Currents (Thick Oxide)

Thin Oxide: 1.25nm– Max VDD = 1.0V

– LMIN = 50nm

Medium Oxide: 2.2nm– Max VDD = 1.5V

– LMIN = 100nm

– Per μm width: IMAX,MEDIUM/IMAX,LVT = 93%

Thick Oxide: 5.2nm– Max VDD = 3.3V

– LMIN = 230nm

– Per μm width: IMAX,THICK/IMAX,LVT = 73%3

Page 4: STT-RAM  Circuit Design

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MTJ Sharing

TMR Degradation(Reading)

Page 5: STT-RAM  Circuit Design

TMR Degradation

Parallel Resistance (R||)

degrades TMR

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MTJ1,1

WL<1>

MTJ1,2

MTJ1,M

SL

BL<1>

BL<2>

BL<M>

MTJ2,1

WL<2>

MTJ2,2

MTJ2,M

MTJN,1

WL<N>

MTJN,2

MTJN,M

Parasitic Parallel Resistance

||

1, all P

1 1

11 , all AP

1 1

P

P

N MR

N MR

N MTMR R

N M

Page 6: STT-RAM  Circuit Design

Effective RP and RAP

Worst case TMR’: largest RP’ and smallest RAP’

Largest RP’:

Smallest RAP’

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||

1 1' || || 1 1

1 1 1P P P P P

N M N MR R R R TMR R TMR R

N M NM N M TMR

||

1 1' || 1 || 1

1 1 1 1AP AP P P P

N M N MR R R TMR R R TMR R

N M NM N M TMR

Page 7: STT-RAM  Circuit Design

Effective TMR

Putting it all together:

Example 1kbit Arrays: TMR = 120%, M = 2, N = 16, 32-bit words: TMR’ = 4.8% TMR = 120%, M = 2, N = 8, 64-bit words: TMR’ = 9.8% TMR = 120%, M = 2, N = 4, 128-bit words: TMR’ =

20.7%7

' ''

'

1 11 1

1 1 11

11

2 1

1 1

AP P

P

P P

P

R RTMR

R

N M N MTMR R TMR R

NM N M TMR NM N M TMRN M

TMR RNM N M TMR

N M NMTMR

NM N M TMR

Page 8: STT-RAM  Circuit Design

Monte Carlo Simulations (M = 2, 3)

ERROR IN MATLAB CODE used to generate last week’s Monte Carlo plots → Not simulating the intended cases!– Fixed and reran simulations → results not so good

Ran multiple simulations with and w/o random variations in RP and TMR (based on worst case from Jianping)

– Extracted worst case TMR’ and TMR’ for 10% read error

For 128-bit words, with bit read error = 10.0%:– # error correcting bits = 36 (1/5 word)

● Probability of a word error: 1 in 6,788 reads

– # error correcting bits = 32 (1/4 word)● Probability of a word error: 1 in 3.59x106 reads

– # error correcting bits = 43 (1/3 word)● Probability of a word error: 1 in 13.2x1012 reads 8

Page 9: STT-RAM  Circuit Design

TMR’ vs. N for 1T-2MTJ (M = 2)

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2 4 6 8 10 12 14 160

10

20

30

40

50

60

70T

MR

[%

]

N

TMR = 50%TMR = 100%TMR = 150%TMR = 200%

Page 10: STT-RAM  Circuit Design

Monte Carlo Simulations: M = 2, N = 4

TMR = 120% RP = 500Ω 25k Simulations TMR’

– Worst Case = 20.7%– ~10% Read Error = 30.0%

TMR = 120%, 3σ = ±12% RP = 500Ω, 3σ = ±50Ω 25k Simulations TMR’

– Worst Case = 3.7%– ~10% Read Error = 25.4%

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200 300 400 500 600 700 8000

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

Resistance [ ]

PR

OB

RP

RAP

200 300 400 500 600 700 8000

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

Resistance [ ]

PR

OB

RP

RAP

Page 11: STT-RAM  Circuit Design

Monte Carlo Simulations: M = 2, N = 8

TMR = 120% RP = 500Ω 25k Simulations TMR’

– Worst Case = 9.8%– ~10% Read Error = 14.6%

TMR = 120%, 3σ = ±12% RP = 500Ω, 3σ = ±50Ω 25k Simulations TMR’

– Worst Case = -4.1%– ~10% Read Error =

12.4%

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200 250 300 350 400 450 500 550 600 650 7000

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Resistance [ ]

PR

OB

RP

RAP

200 250 300 350 400 450 500 550 600 650 7000

0.02

0.04

0.06

0.08

0.1

0.12

Resistance [ ]

PR

OB

RP

RAP

Page 12: STT-RAM  Circuit Design

Monte Carlo Simulations: M = 2, N = 16

TMR = 120% RP = 500Ω 25k Simulations TMR’

– Worst Case = 5.1%– ~10% Read Error =

8.5%

TMR = 120%, 3σ = ±12% RP = 500Ω, 3σ = ±50Ω 25k Simulations TMR’

– Worst Case = -10.3%– ~10% Read Error =

4.7%12

200 250 300 350 400 450 500 550 600 650 7000

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Resistance [ ]

PR

OB

RP

RAP

200 250 300 350 400 450 500 550 600 650 7000

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

Resistance [ ]

PR

OB

RP

RAP

Page 13: STT-RAM  Circuit Design

TMR’ vs. N for 1T-3MTJ (M = 3)

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2 4 6 8 10 12 14 16-30

-20

-10

0

10

20

30

40T

MR

[%

]

N

TMR = 50%TMR = 100%TMR = 150%TMR = 200%

Page 14: STT-RAM  Circuit Design

Monte Carlo Simulations: M = 3, N = 4

TMR = 120% RP = 500Ω 25k Simulations TMR’

– Worst Case = 0.0%– ~10% Read Error =

15.6%

TMR = 120%, 3σ = ±12% RP = 500Ω, 3σ = ±50Ω 25k Simulations TMR’

– Worst Case = -10.1%– ~10% Read Error =

15.9%

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200 250 300 350 400 450 500 550 6000

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Resistance [ ]

PR

OB

RP

RAP

200 250 300 350 400 450 500 550 6000

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Resistance [ ]

PR

OB

RP

RAP

Page 15: STT-RAM  Circuit Design

Monte Carlo Simulations: M = 3, N = 8

TMR = 120% RP = 500Ω 25k Simulations TMR’

– Worst Case = -11.2%– ~10% Read Error = -0.6%

TMR = 120%, 3σ = ±12% RP = 500Ω, 3σ = ±50Ω 25k Simulations TMR’

– Worst Case = -16.7%– ~10% Read Error = -

1.0%

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200 250 300 350 400 450 5000

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

Resistance [ ]

PR

OB

RP

RAP

200 250 300 350 400 450 5000

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

Resistance [ ]

PR

OB

RP

RAP

Page 16: STT-RAM  Circuit Design

Monte Carlo Simulations: M = 3, N = 16

TMR = 120% RP = 500Ω 25k Simulations TMR’

– Worst Case = -15.9%– ~10% Read Error = -11.2%

TMR = 120%, 3σ = ±12% RP = 500Ω, 3σ = ±50Ω 25k Simulations TMR’

– Worst Case = -23.4%– ~10% Read Error = -11.4%

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100 150 200 250 300 350 400 450 5000

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

Resistance [ ]

PR

OB

RP

RAP

100 150 200 250 300 350 400 450 5000

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

Resistance [ ]

PR

OB

RP

RAP

Page 17: STT-RAM  Circuit Design

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MTJ Sharing

Device IREAD/IWRITE Requirements(Writing)

Page 18: STT-RAM  Circuit Design

Defining IREAD,MAX & IWRITE,MIN

IREAD,MAX: The maximum read current such that the probability of flipping the MTJ is less than some ε (i.e. ε = 0.1% → IREAD,MAX = 200μA)

IWRITE,MIN: The minimum write current such that the probability of failing to flip the MTJ is less than some ξ (i.e. ξ = 0.1% → IWRITE,MIN = 600μA)

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0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

PR

OB

(WR

ITE

)

IWRITE

,READ AP P MAXI

,WRITE AP P MINI

,READ P AP MAXI

,WRITE P AP MINI

Page 19: STT-RAM  Circuit Design

IREAD/IWRITE for 1T-2MTJ & 1T-3MTJ

Example: 1T-2MTJ architecture

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WL<1> WL<2>

BL<1>

BL<2>

IWRITE,MIN

α∙IREAD,MAX

, ,

, ,

READ P AP MAX WRITE P AP MIN

READ AP P MAX WRITE AP P MIN

I I

I I

Page 20: STT-RAM  Circuit Design

IREAD/IWRITE for 1T-2MTJ

RP Case 1: RAP Case 1:

RP Case 2: RAP Case 2:

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“1” “0”RP RP

RP RP

“1” “0”RAP RP

RAP RP

“1” “0”RAP RAP

RAP RP

“1” “0”RP RP

RP RAP

, , ,

,

,

2

12

P P PWRITE MIN P AP READ MAX P AP READ MAX P AP

READ MAX P AP

WRITE MIN P AP

R I R I R I

I

I

, , , ,

, , , ,

,

,

1

1

11

1

P WRITE MIN P AP P READ MAX P AP P READ MAX P AP P READ MAX AP P

P WRITE MIN P AP P READ MAX P AP P READ MAX P AP P READ MAX P AP

READ MAX P AP

WRITE MIN P AP

R I R I R I R TMR I

TMRR I R I R I R I

I

I TMR

, , , ,

, , , ,

,

,

1 1 1

1 1 1

1

1

P WRITE MIN AP P P READ MAX AP P P READ MAX P AP P READ MAX AP P

P WRITE MIN AP P P READ MAX AP P P READ MAX AP P P READ MAX AP P

READ MAX P AP

WRITE MIN P AP

R TMR I R TMR I R I R TMR I

R TMR I R TMR I R I R TMR I

I

I

1

TMR

, , ,

, , ,

,

,

1 1 2

1 1 2

1

21

P WRITE MIN AP P P READ MAX AP P P READ MAX P AP

P WRITE MIN AP P P READ MAX AP P P READ MAX AP P

READ MAX P AP

WRITE MIN P AP

R TMR I R TMR I R I

R TMR I R TMR I R I

I

ITMR

Page 21: STT-RAM  Circuit Design

IREAD/IWRITE vs. TMR for 1T-2MTJ

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0 50 100 150 200 2500.25

0.3

0.35

0.4

0.45

0.5

0.55

I RE

AD/I W

RIT

E

TMR [%]

= 1.5 (P AP) = 1.5 (AP P) = 2.0 (P AP) = 2.0 (AP P)

Page 22: STT-RAM  Circuit Design

IREAD/IWRITE for 1T-3MTJ

RP Case 1: RAP Case 1:

RP Case 2: RAP Case 1:

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, , ,

,

,

1.5

11.5

P P PWRITE MIN P AP READ MAX P AP READ MAX P AP

READ MAX P AP

WRITE MIN P AP

R I R I R I

I

I

, , , ,

, , , ,

,

,

11

2

1 1

2

1111

2

P WRITE MIN P AP P READ MAX P AP P READ MAX P AP P READ MAX AP P

P WRITE MIN P AP P READ MAX P AP P READ MAX P AP P READ MAX P AP

READ MAX P AP

WRITE MIN P AP

R I R I R I R TMR I

TMRR I R I R I R I

I

I TMR

, , , ,

, , , ,

,

,

11 1 1

2

11 1 1

2

P WRITE MIN AP P P READ MAX AP P P READ MAX P AP P READ MAX AP P

P WRITE MIN AP P P READ MAX AP P P READ MAX AP P P READ MAX AP P

READ MAX P AP

WRITE MIN P AP

R TMR I R TMR I R I R TMR I

R TMR I R TMR I R I R TMR I

I

I

10.5

11 TMR

, , ,

, , ,

,

,

1 1 1.5

1 1 1.5

1

1.51

P WRITE MIN AP P P READ MAX AP P P READ MAX P AP

P WRITE MIN AP P P READ MAX AP P P READ MAX AP P

READ MAX P AP

WRITE MIN P AP

R TMR I R TMR I R I

R TMR I R TMR I R I

I

ITMR

“1” “0”RP RP

RP RP RP

“1” “0”RP RP

RP RAP RAP

“1” “0”RAP RP

RAP RP RP

“1” “0”RAP RAP

RAP RP RP

Page 23: STT-RAM  Circuit Design

IREAD/IWRITE vs. TMR for 1T-3MTJ

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0 50 100 150 200 2500.25

0.3

0.35

0.4

0.45

0.5

0.55

I RE

AD/I W

RIT

E

TMR [%]

= 1.5 (P AP) = 1.5 (AP P) = 2.0 (P AP) = 2.0 (AP P)

Page 24: STT-RAM  Circuit Design

SUMMARY

TMR Degradation (READING)– M = 2:

● Not as good as previously thought● Read circuit need to work for 25-30% TMR

– 10-12% for more wordlines

– M = 3: not really possible (negative TMR)

IREAD/IWRITE (WRITING)

– For TMR = 120%, χ = 1.5-2:● M = 2: IREAD/IWRITE > 0.36-0.43

● M = 3: IREAD/IWRITE > 0.42-0.49

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