STT-RAM Circuit Design

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STT-RAM Circuit Design Max I WRITE (Recap), MTJ Sharing Paper
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    06-Jan-2016
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STT-RAM Circuit Design. Max I WRITE (Recap), MTJ Sharing Paper. Cell Sizing. Max I WRITE for I-STT (IBM65). I-STT MTJ Specs (Jianping). For 1ns switching: R P ≈ 500 Ω TMR ≈ 120% AP→P: 380-460 μ A P→AP: 600-800 μ A I WRITE(P→AP) /I WRITE(AP→P) : 1.5-2 I READ,MAX : - PowerPoint PPT Presentation

Transcript of STT-RAM Circuit Design

  • I-STT MTJ Specs (Jianping)For 1ns switching:RP 500TMR 120%APP: 380-460APAP: 600-800AIWRITE(PAP)/IWRITE(APP): 1.5-2

    IREAD,MAX:If both the read and write pulses are on the order of a few ns, then IREAD/IWRITE 2/3.We can share access transistors! (MAYBE)Limiting factor in MTJ sharing is TMR degradation

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  • Minimum Cell Size (NN Corner)

    VBS = -0.25VNominal3745.5F2LVT3340F2

    VBS = 0.00VNominal3644F2LVT32.539.5F2

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  • Maximum Write Currents2 Cases:VDD = 1V, WL = 1VNominal voltages specified in documentationVDD & VWL is boosted (while keeping VDS, VGS < 1V)Different VBL & VSL used to write 1 & 0IWRITE(PAP)/IWRITE(APP): 1.5-2Example:VWL = 1.10VVBL = 0.00VVSL = 1.10VVBL = 0.10VVSL = 1.40VIWRITE: APP = 335APAP = 670A

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  • Simulation Results (PAP)MTJ Specs:RP = 500TMR = 120% IWRITE (P->AP) [A]

    NOMINAL VT25F2: VWL = 1.00V, VSL = 0.00V, VBL = 1.20V35F2: VWL = 1.10V, VSL = 0.10V, VBL = 1.35V50F2: VWL = 1.25V, VSL = 0.25V, VBL = 1.65VLOW VT25F2: VWL = 1.00V, VSL = 0.00V, VBL = 1.20V35F2: VWL = 1.10V, VSL = 0.10V, VBL = 1.40V50F2: VWL = 1.30V, VSL = 0.30V, VBL = 1.80V

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    SL/BL = 1V WL = 1VSL/BL | (VDS < 1V) WL | (VGS < 1V) NOMINAL VTLOW VTNOMINAL VTLOW VTSSNNFFSSNNFFSSNNFFSSNNFF25F2280.2327.2380.3333.9378.5427.4294.5345.4404.3350.0398.6453.335F2473.4537.3607.4561.0621.2684.7495.9569.0653.2599.2670.0748.850F2739.7820.5906.0867.4940.91015787.8894.11018964.410681183

  • Simulation Results (APP)MTJ Specs:RP = 500TMR = 120% IWRITE (AP->P) [A]

    NOMINAL VT25F2: VWL = 1.00V, VSL = 1.00V, VBL = 0.00V35F2: VWL = 1.10V, VSL = 1.10V, VBL = 0.00V50F2: VWL = 1.25V, VSL = 1.25V, VBL = 0.00VLOW VT25F2: VWL = 1.00V, VSL = 1.00V, VBL = 0.00V35F2: VWL = 1.10V, VSL = 1.10V, VBL = 0.00V50F2: VWL = 1.30V, VSL = 1.30V, VBL = 0.00V

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    SL/BL = 1V WL = 1VSL/BL | (VDS < 1V) WL | (VGS < 1V) NOMINAL VTLOW VTNOMINAL VTLOW VTSSNNFFSSNNFFSSNNFFSSNNFF25F2164.3187.1212.7197.8219.8243.2164.3187.1212.7197.8219.8243.235F2217.1240.8267.3260.6283.4307.1263.5289.2318.2308.7333.2358.950F2264287.9315.2315.2338.0361.9402.6431.2464.5488.5515.9545.2

  • SummaryMaximum IWRITE (LVT, FF) (PAP) :25F2: 453.3A35F2: 748.8A50F2: 1183A

    Maximum IWRITE (LVT, FF) (APP) :25F2: 243.2A35F2: 358.9A50F2: 545.2A

    35F2 LVT cell almost meets I-STT specs for 1ns switchingAPP current a little weak (can be adjusted a little higher)38-40F2 LVT cell w/ boosted voltages can safely meet Jianpings spec for 1ns switching*

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    MTJ SharingTMR Degradation(Reading)

  • TMR Degradation

    Parallel Resistance (R||) degrades TMR*

  • Effective RP and RAPWorst case TMR: largest RP and smallest RAP

    Largest RP:

    Smallest RAP*

  • Effective TMR (1)Putting it all together:

    Example 1kbit Arrays:TMR = 120%, M = 2, N = 16, 32-bit words: TMR = 4.8%TMR = 120%, M = 2, N = 8, 64-bit words:TMR = 9.8%TMR = 120%, M = 2, N = 4, 128-bit words: TMR = 20.7%*

  • TMR vs. N for 1T-2MTJ (M = 2)*

  • TMR vs. N for 1T-3MTJ (M = 3)*

  • Monte Carlo Simulations (1)Limited to M = 2

    Theoretical TMR is overly pessimisticWith error correction we can let the extreme cases fail.Example:Bit read error = 0.1%Word length = 64# error correcting bits = 4Probability of a word error: 1 in 137,763,712 reads

    M = 2, N = 4TMR = 120%, RP = 50025k SimulationsWorst Case TMRTheoretical = 20.7%Simulation = 46.2%

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  • Monte Carlo Simulations (2)

    M = 2, N = 8TMR = 120%, RP = 50025k SimulationsWorst Case TMRTheoretical = 9.8%Simulation = 20.7%

    M = 2, N = 16TMR = 120%, RP = 50025k SimulationsWorst Case TMRTheoretical = 4.8%Simulation = 10.1%

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    MTJ SharingDevice IREAD/IWRITE Requirements(Writing)

  • Defining IREAD,MAX & IWRITE,MIN IREAD,MAX: The maximum read current such that the probability of flipping the MTJ is less than some (i.e. = 0.1% IREAD,MAX = 200A)IWRITE,MIN: The minimum write current such that the probability of failing to flip the MTJ is less than some (i.e. = 0.1% IWRITE,MIN = 600A)*

  • IREAD/IWRITE for 1T-2MTJ (1)Limited to 1T-2MTJ architecture*

  • IREAD/IWRITE for 1T-2MTJ (2)

    RP Case 1:

    RAP Case 1:

    RP Case 2:

    RAP Case 2:*

  • IREAD/IWRITE vs. TMR*

  • SUMMARYCell Sizing: 35-40F2

    TMR Degradation: M = 2 (READING)Word length should be greater than 64Serious TMR degradation for N > 8Ideally:RP = 500, TMR = 120%M = 2, N = 4 1kbit arrays of 128-bit wordsTMR = 20.7%Reality: TMR 45% (ignoring worst case)Need less than 8 error correcting bits

    IREAD/IWRITE (WRITING)For TMR = 120%, = 1.5-2: IREAD/IWRITE > 0.36-0.43*

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