UCONN ENGR_ECE 4243/6243 HW11 FET-I & Solution 11152016 F. JainQUIZ 2 part B Take Home will be like Q.6. It will be given on 11/22/16

Q.1. (a) Find the work functions for n and p-type Si for the doping levels given below. Show them in relation to vacuum energy level being zero as the reference. The electron affinity of Si is qχSi = 4.15 eV. p-side: Acceptor concentration NA=1015 cm-3, n=10-5 sec. Dn=40 cm2/sec.

Effective mass: electrons me=mn=0.26mo, holes mh=mp= 0.64 mo,Junction area A=10-3 cm-2, ni (300K) =1.51010 cm-3. r(Si)=11.8, 0=8.8510-14 F/cm, s=r0. Assume all donors and acceptors are ionized at T=300 K. Eg = 1.1eV, Boltzmann Constant k= 8.65x10-5 eV/K.

n+-side: Donor concentration ND=1018 cm-3, minority hole lifetime p=210-6 sec.Minority hole diffusion coefficient Dp=12.5 cm2/sec.

(b) Compute the work function difference nSi-pSi (=nSi - pSi) and show that it is equal to the built-in voltage.

Solution Q1(a) Work function is expressed as qφnsi=qχsi+(Ec−Ei )−( Ef−E i)=4 .15+0 .55−0 .4666=4 .2334 eVEc−Ei≃Eg /2=0 .55 eVEf - Ei is obtained from the definition of intrinsic Fermi level Ei:n=ni e

(E f−Ei)/kT

, if we take natural log (ln) we get

E f−Ei=kT ln ( nni )≃kT ln( N D

ni)≃0 .0259 ln(1018

1 .5×1010 )=0 . 4666 eV

Work function of p-Si: Doping NA=1015cm-3

Intrinsic concentration pi=ni

qφ psi=qχsi+Eg/2+(E i−E fp )=4 .15+0 .55+0 . 2876=4 .9876 eV

p=pi eEi−Ef

kT =ni eEi−E f

kT or eE i−Ef

kT = pn i

Taking log (ln) we get, [ ln(e Ei−Ef

kT )=E−E f

kT ]=ln ( Pni )¿ ln( N A

ni )Ei−E f=kT ln( N A

ni)=0 .0259 ln (1015

1 . 5×1020 )=0 .2876 eV

Note Ei - Efp = qψB

Q1(b) Work function differences are negative values

= [qφp−si−qφn−si ]=[4 . 9876−4 .2334 ]=0 .7542eVV bi=φn−φ si≃0.754 V

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Same as we calculated from the well-known Vbi expression for p-n junctions.

V bi=0 . 0259 ln(1018∗1015

2 .25×1020 )=0.754V

Q.2 Compute the flat band voltage Vfb and threshold voltage VT (or VTH) for an Al-SiO2-pSi MOS capacitor having the following parameters: T=300K. Qox = 2.103 x 10-8 C/cm2 Si = 11.8

Oxide thickness = d = 1000Å (1Å = 10-8 cm), ni = 1.5x1010 cm-3

qSiO2 = electron affinity of SiO2 = 0.9 eV NA = 1016 cm-3

ox = 3.9, o = 8.854x10-14 F/cm qχSi = 4.15 eV (affinity of Si)Intrinsic Fermi level is Ei ~Eg/2, Eg (Si) = 1.1eV qAl = 4.1 eV (work function of Al).Assume Qox to be located in the SiO2 near the Si interface.

HINT set: VFB= ms – Qox/Cox ( Qox assumed to be located in SiO2 near the SiO2-Si interface).VFB= ms if there is no oxide charge. ms = m -s = Al - pSi . Find the work functions and compute ms. Solution Q.2

Evaluation of Flat Band voltage: Vfb=VFB=Flat band voltage

V FB=φms−Qox

Cox=(φAl−φ pso )−

Qox

Cox

qφ Al=4 . 1 eV and qφ psi=4 .15+0 . 55+0 .0259 ln [1016

1 .5×1010 ]=5 .0473 eV

φms=φ Al−φ psi=4 .1−5 .0473=−0 .9473Qox=2 .103×10−8 C /cm2 , and

Cox=ε sio2

ε0

dF /cm2=3 . 9×8 . 854×10−13

1000×10−8 =3 . 453×10−8 F /cm2

Thus, V FB=−0.9473−2. 103×10−8

3 . 453×10−8=−0 .9433−0 . 609= -1.552V

Evaluation of threshold voltage VTH:

V TH=V FB−Q sc

Cox+2 ψB

where

qψ B=Ei−Ef =kT ln ( N A

n i)=0 .0259 ln(1016

1. 5×1020 )=0 . 3475or 2 ψB=0 . 3473 V×2=0 .6946 V

Qsc=−qN A W m=−1 . 6×10−19×1016×3 . 01×10−5=−4 .816×10−8

C/cm2

W m=√ 2 ε si ε0 2ψB

qN A=√ 2×11. 8×8 . 854×10−14×0. 69

1 .6×10−19×1016 =√90 . 7×10−11=3 . 01×10−5 cm

2

and

Qsc

Cox=−4 . 816×10−8

3 . 453×10−8 =−1. 394V. Substituting in threshold expression, we get

V TH=V FB−Q sc

Cox+2 ψB=−1 . 552+1 . 394+0 . 6946=0. 5366 V

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New Q.3(a). The threshold voltage is altered by: Circle correct answers

Gate metal charge in the gate oxide source doping substrate doping

(b) For a given metal-oxide-pSi MOS capacitor, which one will have higher threshold? CircleAl-SiO2-psi or Au-SiO2-pSi

(c) What is the advantage in replacing gate metal by doped poly Si layer as the gate layer? Adjustment of threshold voltage, Enabling deposition of oxide for gate isolation in ICs

(d) Why in 22 nm FETs poly Si is not used and TaN or TiN metals are used?

Because of lower threshold so that devices can use VDD ~ 0.5V.

Q.4 (a) Compute the drain current for VD=0.5V and VD=2.5V at VG=2V and 4V.First, we need to find the saturation voltage VD (set) for VG=2V and for VG=4V.VD (sat) ≈ VG-VTH using Case I Approximation.

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ψB=0 .347 V

W m=√2 ε s ε 0 2ψ B

qN A=3 .01×10−5 cm

V TH≡V T=V FB−Q sc

Cox+2ψ B=−1 .557−

−qN A W m

Cox+2ψ B

¿−1. 557+1 .6×10−19×1016×3 . 01×10−5

3 .45×10−8+2×0 . 347=−1. 557+1 .396+0 .694=0 . 533V

CASE I:

ForV G=2V , V D (Sat )≃V G−V TH=2−0 .533=1 . 467VForV G=4 V ,V D ( Sat )=4−0. 533=3 .467VTherefore , for V G=2V , V D=0 .5 V is belowV D (sat ) of 1. 467V¿V D=2 .5 V >V D (sat ) of 1 . 467V

Linear regime : I D=μn CoxZL [ (V G−V TH )V D−

V D2

2 ] is OK for V D=0 .5 V

Saturation ⋯regime: I D(sat )=μn CoxZL [V D (sat )2

2 ] isOK for V D>1 . 467 V

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Given: Channel length L = 10 μm, channel width Z = 40 μm, operating temperature T = 300K, and channel mobility μn = 800 cm2/Volt×sec., Qox = 2.103 x 10-8 C/cm2, Si = 11.8, Oxide thickness = d = 1000 Å (1 Å = 10-8 cm), ni = 1.5x1010 cm-3, qSiO2

= electron affinity = 0.9 eV, NA = 1016 cm-3, ox = 3.9, qχSi = 4.15 eV, o = 8.854x10-14 F/cm, qAl = 4.1 eV

The intrinsic Fermi level Ef= Ei ~Eg/2.

N A=1016 cm−3

ni=1 .5×1010 cm−3

d=1000 Α

Cox=3 .9×8 .854×10−14

1000×10−8 =3.45×10−8 F /cm

φms=−0 . 6−kTq

lnN A

ni

¿−0 .6−0 . 0259 ln 1016

1.5×1010

φms=−0 . 947V

V FB=φms−Qox

Cox

¿−0 . 947−2 .103×10−8

3 .45×10−8 =−1. 557V

V G=2V, and V D=0 . 5V

I D=800×3. 45×10−8×40μm10 μm

×[ (2−0 . 533 ) 0. 5−0 .52

2 ]¿1 .104×10−4×[1 . 467×0 . 5−0. 25

2 ]=1 .104×10−4×0 . 6085=6 . 718×10−5 Α

V G=2V, and V D=2 .5 V

I D ( sat )=1. 104×10−4×[ (2−0 . 533 )2

2 ]=1 .104×10−4×[ (1 . 467 )2

2 ]I D ( sat )=1. 187×10−4 Α

Similarly ,V G=4 V , V D=0 . 5 V and2 .5 V are belowV D (sat ) .Hence , V D ( sat )=3 . 467 V ,V G=4V ,V D=0 . 5V

I D=1.104×10−4×[ (4−0 . 533 )×0. 5−0. 52

2 ]¿1 .104×10−4×[3 . 467×0 .5−0 .25

2 ]=1 . 775×10−4 Α

We use the linear regime ID equation for VD < VD(sat)

V G=4 V ,V D=2 .5V

I D=1. 104×10−4×[3 . 467×2 . 5−2 .52

2 ]=6 .118×10−4 Α

Summary Table

ID VG VD

6.718x10-5A 2V 0.5V

1.187x10-4A 2V 2.5V

1.775x10-4A 4V 0.5V

6.118x10-4A 4V 2.5V

Q.4(b) Find saturation current and voltage VD(sat) at the VG = 4V.

ID(sat) at VG=4.0 V

VD = VD(sat) = VG – VTH =4.0-0.533=3.467 volts

I D( sat )=μn COXZL [V D(sat )2

2 ]=1.104∗10−4∗(3 .467 )2

2 =6 . 63∗10−4 Amp

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Using Case-I definition of VD(sat)

Q.4(c) Calculate the channel conductance gD and the transconductance gm at the following drain voltages VD = 0.5 V and VD = 2.5 V.

gm at VD=0.5 V, VD=2.5 V, VG=4.0 V (likes part b)

Find gd at VD=0.5 V, VD=2.5 V VG=4.0 V

gm for VG =4.0 V:

VD(sat) = VG –VTH = 4.0 – 0.533 = 3.467 V.

So both VD=0.5 V & VD=2.5 V will give unsaturated linear regime values.

gm=∂ I D

∂V G=μn∗COX∗

ZL(V D )=800×3.45×10−8×40

10×V D=1. 104∗10−4 V D

gm(at V D=0 .5 )=1 .104×10−4×0 .5=0 . 552×10−4 Mho, gm(at V D=2.5 )=1. 104×10−4×2 . 5≃2 .76∗10−4 Mho

Drain conductance; gD=

∂ I D

∂V D|V G

=μn COXZL [(V G−V TH )−V D ]

For VG=4.0 , VD(sat)=3.467 V(VD=0.5 V, 2.5 V are below Saturation )

gD|V D=0. 5=1.104∗10−4 ¿ [ (4−0 .533 )−0. 5 ]=3 . 275∗10−4 Mho

gD|V D=2. 5=1 .104∗10−4 ¿ [( 4−0 .533 )−2 .5 ]=1. 06∗10−4 Mho

Q.4(d) If the gate is n+ poly Si (ND = 1x1019cm-3), calculate the flat band and threshold voltage assuming the same Qox as in part (a).

Gate is n+ poly Si , ND=1019 cm-3

qφms≡qφn+Poly-pSi=qφn+Poly−qφpSi

¿ [4 .15+0 .55-0 .0259×ln (1019

1 .5∗1010 )]−[4 .15+0 .55+0 . 0259× ln(1016

1. 5∗1010 )]=( 4 .1738−5 . 0473)eV

qφms=−0 . 8735V

V FB=φms−QOX

COX=−0 . 8735−2. 103∗10−8

3 . 45∗10−8 =−0. 8735−0 .609=−1 . 4825V

Note: In Part Q4(a), VFB = -1.557 V, and in part Q1(d) VFB =-1.4825 V

V TH=V FB−Q sc

COX+2 ψB

V TH=V FB−(−q∗N A∗W m)COX

+2 ψB

V TH=−1 . 4825+(1 .6∗10−19∗1016∗3 . 01∗10−5 )3 . 45∗10−8 +0 .694=−1 . 4825+1 .3959+0. 694=0 . 607 V

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The parameters used are from Q4(a).

N A=1016 cm−3 , Qsc=−q∗N A∗W m , and ψB=kTq

ln ( N A

ni)

Q4(e) Calculate the transconductance gm in the linear regime. From Q1(c) we have

gm=∂ I D

∂V G=μn∗COX∗

ZL(V D )=800×3.45×10−8×40

10×V D=1. 104∗10−4 V D

. It depends on VD.

Q4(f) What is the cut off frequency fT (= gm/(2 Cg)) of this FET? Cg is the gate capacitance which varies between Cox and Cox/3 depending on the depletion width variations. It also depends on the drain and source to body capacitance.

Using gm =2.76*10-4 from part Q1(d) at VD = 2.5V, and Cg = Cox/3 = 3.45*10-8/3=1.15*10-8

F/cm2. Here we have used the capacitance of unit area (L*Z = 1 cm2).

fT =2.76*10-4/(2 *1.15*10-8) = 3819.71 Hz for a 1cm2 gate area FET.

For FET with dimensions L=10 m and Z=40 m,

fT = 3819.71/(10m * 40m) =9.54*108 Hz.

Q.5(a) The resistance of load transistor is 4 to 6 times higher than of the driver transistor resistance. Resistance is inversely proportional to (W/L) ratio. As a result, (W/L) Driver = 4 to 6 * (W/L) Load.

Fig 1. Schematic of an NMOS logic gate. W/L (or Z/L) ratios are shown. Justification: When there are more than one transistor is in series on the driver side (i.e. below the output), we increase the (W/L) ratio by the number of transistors in series. Two transistors T1 and T3 are in series with size = 2*20/5=40/5.Similarly, T2 and T3 are in series with same sizing.

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Q5(b) The PMOS-FET (W/L) is made 2.5 times larger than (W/L) of NMOS. This is done to charge and discharge the load capacitor CL (at the output of a CMOS gate). When input voltage goes from low to high, discharging of CL (which was at VDD) takes place through NMOS FET. Similarly, charging happens through PMOS FET when the input changes from high-to-low.

μn∗COX∗(WL )n−MOS

=μP∗COX∗(WL )P−MOS

Since μn≃μp∗2. 5 ,(WL )n−MOS

=2 .5∗(WL )P−MOS

Fig.2 shows the topology of this CMOS inverter.

Fig.2 CMOS Inverter on p-Si substrate

Q.5(c) Justify the W/L ratios shown for CMOS NOR and NAND gates in Fig.3.

Fig. 3 W/L ratios for CMOS NOR and NAND gates.

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NOR gate Fig.3(A). Here two P-MOS FETs are in series. When both are “ON”, we need to reduce their total series resistance to equivalent of one transistor.

The W/L ratio is multiplied by number of FETs in series. (W/L) P-MOS when two in series =2*(W/L) P-MOS when single =2*(25/5)=50/5Fig.3 (B) is a NAND. This gate has two NMOS in series. Therefore, (W/L)N-MOS when two in series(NAND) =(10/5) *2# FET in series =20/5

Q.6. NANOFET Design: (a) Outline the steps used in scaling a FET from 1.3 micron to 0.25 micron is described in Baccarani et al (1984 paper) and shown in Table I below. Design steps: 1. Find the dimensional scaling factor l which is L/L’ or W/W’ or Tox/Tox’.2. Find the V’TH for the new scaled down FET including process variations, masking registration errors, doping changes. Find V’TH= 4 V’TH. Find V’DD = 4 V’TH. Calculate scaling factor for voltages and potentials: k = VTH/ V’TH

3. Find

4. Compute new substrate doping N’A = NA/ = (2/k) NA

Table I Hint set for 25nm FET designParameters LATV

1.3micron

0.25 micron QMDT* (IBM)

25nm SiGe

(Home work)

Scaling

factor

Comments

Channel Length L(m)

1.3 0.25 0.025 =10

Gate InsulatorOxide tox (nm)

25 5.0 (SiO2) 0.5 (SiO2) 10 0.5(HfO2 /SiO2)= 1.7nm

Junction Depth xj(nm)

350 70-140 7-14 10 Gives high Rs and Rd

VTH (V)VTH 4xVTH

0.6 0.25V’TH 4xV’TH

V’TH =0.06

0.06V’TH 4xV’TH

V’TH =0.015

=4 VTH=0.015V

VDS = VDD (V)VDD = 4 x VTH

2.5 1.0 0.25 =4

Band Bending (V) 1.8 0.8 0.3 ?

Doping NA (cm-3) 3x1015 N’A =31016 N’A=7.51017 NA x 2/=25

(Rs + Rd)IDIR Drop (mV)

NA < 10mV < 1mV ?? How to solve this

RC Delay (ps) Not appl. (NA) 100ps 2-5 ps?? ?? How to solve thisScaled down FET Original FET

1. Dimensions

L’, W’, Tox’ Lλ ,

Wλ ,

T ox

λ λ>1

2. Voltages

VGS’, VDS’ ,VTH’ V GS

k ,V DS

k ,V TH

k k>1

3. Doping Levels

NA’, ND’ N A

δ ,N D

δ δ<1

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Since δ=kλ2 and (1/= 2/k, substrate doping NA’ is higher. [Pages 579-580 Notes III]

Q6(b) Scale down a 0.25 micron FET to design the 0.025 micron (25nm) transistor following the 10-fold scaling. Given VTH = 0.015V for 25 nm process. Justify the values given in Table I.

For 0.025micron FET, use VTH = ¼ of VDD. Assume VDD of 0.4 Volt. Obtain gate oxide thickness, Si doping levels, source and drain thicknesses and doping etc. The three design steps to obtain 0.25μm FET from 1.3μm FET are shown below

1.3 μm channel length L FET

0.25 μm FET channel length L’ Scaling factor

L = 1.3 μm Tox = 25 nm

VDD = 2.5 VVTH = 0.6 V

L’ = 0.25 μm Tox ’ = 5 nm

VDD ’ = 1 VVTH ’ = 0.25 V

L’=Lλ , λ=¿

1.30.25= 5

VDD’=V DD

k , k=¿

2.51 = 2.5

Substrate doping NA Scaling factor δ

NA’ = NAλ2

k = NA / δ

δ = k / λ2

NA’ = NA252.5 = NA * 10

N’A =31016 cm-3

These parameters are given in Reference 1, Pg 591Now our task is to scale 0.25μm to 0.025 μm FET

0.25 μm channel length L FET

0.025 μm channel length L’ FET Scaling factor

L = 0.25 μm

Tox = 5 nm

VDD = 1.0 V

VTH = 0.25 V

NA = 3 * 1016 cm-3.

L’ = 0.025 μm

Tox’ =5

10 =0.5 nm = 5Å

VDD’ = 0.25V (given). VDD’ = 4* VTH’VTH’ = 4 VTH’=4*0.015 = 0.06Vk = VDD/ VDD’= 1.0/0.25 = 4

NA’ = NA/(1/= 2/k= 100/4=25.NA’= 3*1016 *25 = 7.5*1017 cm-3.

L’=Lλ ,

λ=¿ 0.25 ⁄ 0.025= 10

VDD’=V DD

k , k=¿

1.00.25= 4

k =4

10

NA’ = 3 * 1016 *

102

4 = 7.5* 1017 cm−3

Certain issues following scaling: 1. Oxide thickness in 0.25 μm ≈ 50 - 60 Ao

Tox’ in 0.025 μm ≈ 5 Ao is too small and permits tunneling. 2. Tunneling from source to drain when L’ = 25nm and lower. 3. ID * ( R S + RD ) voltage drop is < 1 mV.

Q.6 (c) Generalized scaling (GS, Table IV) is better than constant electric field (CE) scaling (Table–II) and constant voltage (CV) and Quasi constant voltage (QCV) in (Table-III) as it permits different scaling for voltages/ potential, dimensions (L,W,Tox ) and doping. GS is based on preserving Poisson’s equation. GS gives relationship for NA’ and ND’ with NA and ND

multiplied by 1/δ.

Constant electric (CE) field scaling: All dimensions, voltages are divided by k (or scaling factor). Doping levels are multiplied by k.

Quasi Constant Voltage (QCV) Scaling: All dimensions are divided by k (or scaling factor). Doping levels are multiplied by k. The voltages are divided by (1/k)1/2 which is less than k.

Constant Voltage (CV) Scaling: All dimensions are divided by k (or scaling factor). Doping levels are multiplied by k. The voltages are not changed.

Most difficult parameters are:(i) Gate Insulator. Solution is to increase Tox‘ = 5 Ao by using HfO2 which has a higher dielectric constant ɛHf O2 ≈ 13.7 and dielectric constant for SiO2 is 3.9.

Tox’ for HfO2 as gate insulator is = ɛ HfO2ɛ SiO 2 * Tox’(SiO2),

= 13.73.9 * 5 Ao = 17.5 Ao= 1.75 nm

Eg for Hf O2 = 5.7 eV and electron affinity qHf O2 = (2.0 ± 0.25 ) eV

The other parameter is the voltage drop in R S + RD

(ii) Source and Drain resistances and voltage drops for a 25nm FET are calculated below.

Xj for 0.25 µm FET (Baccarani et al Table II) Ls= 22nm (contact) +11nm +11nm=44nm11

L=22nm

= 0.07 – 0.14 µm RS = RD =ρn* Ls

X j∗W

Xj’ for 0.025 µm NanoFET For 1020 n+ doping the resistivity s is

=0.0710

0.14 µm10 ρs = 7 * 10−4Ω-cm. Given W=44nm,

= 0.007 µm 0.014 µm RS = RD =7∗10−4∗44 nm

0.007∗10−4∗44 nm

= 7 nm 14 nm = 1.0 kΩ

If the drain current is I D ≈ 1mA or 0.1 mA. Taking 0.1mA or 100 microamp, we get

I D * (R S + RD) ≈ 0. 2V =200mV, which is too high.

How can we reduce RS and RD ?

Method # 1 Increase the thickness Xj of source or source contact Tsource above the implanted 14 nm region.

New source resistance RS’

= Rs *[Xj/(Xj + Tsource] = 7∗10−7

154∗10−7 *1.0 kΩ = 45.45Ω

The new IRs’ drop is

I *RS’ = 100 µA * 45.45Ω = 4.5mV. This value is still higher than 1mV.

Method 2: (a) Increase W of the channel, and (b) further increase thickness of source TSource. Both are not desirable as they increase the area of FET (option a) and make processing difficult when using masks or metal contacts (option b).

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Method 3. Use metal silicides for vertical extensions in place of n+ Si which have reduced resistivity.

What is done is to replace Tsource contact with lower resistivity silicides or TiN or TaN.

RS (with silicides) is reduced by a factor of 10. The new drop is 0.45mV.

Reduce RS from 45.4Ω to approximately 4.5 Ω.

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