PROBLEM SET #8 - University of California, Berkeleyee140/sp09/homework/h… · ·...
2
EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen PROBLEM SET #8 Issued: Tuesday, March 31, 2009 Due: Tuesday, April 7, 2009, 8:00 p.m. in the EE 140 homework box in 240 Cory 1. This problem concerns the class B output stage shown in Figure PS8-1(a). The input signal is ( ) t f V v in m IN π 2 sin = . (a) If the load is resistive R Z L = sketch timing diagrams of the output voltage ( ) t v OUT , the load current () t i L , and collector currents ( ) t i C1 and ( ) t i C 2 . (b) Repeat (a) if the load is capacitive C j Z L ω 1 = . (c) The output stage is connected in a feedback loop as shown in Figure PS8-1(b). Sketch timing diagrams of () t v OUT , ( ) t i L , ( ) t i C1 , ( ) t i C 2 , and ( ) t v A if R Z L = . Assume amplifier A is ideal. (d) Repeat (c) if C j Z L ω 1 = . Draw only one period in steady state. Clearly mark all important points in your diagrams. V V m 9 = , kHz f in 1 = , pF C 100 = , Ω = 500 R , V V on BE 7 . 0 , = , V V V EE CC 10 = = . (a) (b) Figure PS8-1
Transcript of PROBLEM SET #8 - University of California, Berkeleyee140/sp09/homework/h… · ·...
EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen
PROBLEM SET #8
Issued: Tuesday, March 31, 2009
Due: Tuesday, April 7, 2009, 8:00 p.m. in the EE 140 homework box in 240 Cory
1. This problem concerns the class B output stage shown in Figure PS8-1(a). The input signal is ( )tfVv inmIN π2sin= .
(a) If the load is resistive RZL = sketch timing diagrams of the output voltage ( )tvOUT , the load current ( )tiL , and collector currents ( )tiC1 and ( )tiC 2 .
(b) Repeat (a) if the load is capacitiveCj
ZL ω1
= .
(c) The output stage is connected in a feedback loop as shown in Figure PS8-1(b). Sketch timing diagrams of ( )tvOUT , ( )tiL , ( )tiC1 , ( )tiC 2 , and ( )tvA if RZL = . Assume amplifier A is ideal.
(d) Repeat (c) ifCj
ZL ω1
= .
Draw only one period in steady state. Clearly mark all important points in your diagrams.
VVm 9= , kHzfin 1= , pFC 100= , Ω= 500R , VV onBE 7.0, = , VVV EECC 10== .
(a) (b)
Figure PS8-1
EE 140 ANALOG INTEGRATED CIRCUITS SPRING 2009 C. Nguyen
2. The slew rate of the circuit in Fig. PS8-2 is to be increased by using two 10 kΩ resistors placed at the emitters of Ql and Q2. If the same unity-gain frequency is to be achieved, calculate the new value of compensation capacitor required and the improvement in slew rate.
RE RE
Figure PS8-1
3. Razavi, Chapter 9: Problem 9.19.
4. Razavi, Chapter 9: Problem 9.20.
