Pipelining – Βασικές αρχές

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Pipelining – Βασικές αρχές. Κ. Διαμαντάρας Α. Βαφειάδης Τμήμα Πληροφορικής ΑΤΕΙ Θεσσαλονίικης 2011. Η βασική ιδέα. - PowerPoint PPT Presentation

Transcript of Pipelining – Βασικές αρχές

. . 2011Pipelining 1This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. / . . 2 Pipeline . . pipeline : : : : : : , ,

Pipeline / 3. . pipeline -(-1) . -4 . P P + (M-1) . P+4 Pipeline

P ( = 50P ) P pipeline ( = 4*10 + 10P ) = 10min = 50P/(10P+40) = 5/(1+4/P) P 5 ( )

/ 4. . pipeline :10 min :9 min :7 min :10 min :12 min 48 min

A F= 12 ( )

= (48P) / (12P +4*12) = 4 / (1+4/P)

P P 4 ( )

/ 5. . pipeline

? / 6. . / . . 7 pipelining . 10 10 ( ) .DLX: / . . 8 load/store (Registers)32-bit general purpose registers (GPR): R0, R1, ..., R31. R0 = 0.32 floating-point registers (FPR), 32 single precision (32-bit) registers F0,F2,...,F31 16 double-precision (64-bit) registers. FPR 64-bit F0,F2,...,F15 Data types for integer data8-bit bytes16-bit half words32-bit wordsfor floating point32-bit single precision64-bit double precisionO DLX :byte addressableBig Endian mode : 32-bit2 addressing modes (immediate displacement). load/store GPRs FPRs GPR byte, half-word, word

/ 9. . DLX Addressing / 10. . ADD R1, R2, #17; R2 ; 17 () ;R1 ( )LW R1, 120(R2); R1 ; 120+R2;( )LW R4, 0(R1); R4 ; R1;( )LW R2, 1520(R0); R2 ; 1520, ; R0 ;( )DLX:

I Type (immediate) LW R1, 30(R2)Load word Regs[R1]