Semiconductor Components Industries, LLC, 2000

November, 2000 – Rev. 11 Publication Order Number:

MTP27N10E/D

MTP27N10EPreferred Device

Power MOSFET27 Amps, 100 VoltsN–Channel TO–220

This Power MOSFET is designed to withstand high energy in theavalanche and commutation modes. The energy efficient design alsooffers a drain–to–source diode with a fast recovery time. Designed forlow voltage, high speed switching applications in power supplies,converters and PWM motor controls, these devices are particularlywell suited for bridge circuits where diode speed and commutatingsafe operating areas are critical and offer additional safety marginagainst unexpected voltage transients.• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• IDSS and VDS(on) Specified at Elevated Temperature

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain–to–Source Voltage VDSS 100 Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 100 Vdc

Gate–to–Source Voltage– Continuous– Non–Repetitive (tp ≤ 10 ms)

VGSVGSM

± 20± 40

VdcVpk

Drain Current – Continuous @ 25°CDrain Current – Continuous @ 100°CDrain Current – Single Pulse (tp ≤ 10 µs)

IDID

IDM

271795

Adc

Apk

Total Power Dissipation @ 25°CDerate above 25°C

PD 1040.83

WattsW/°C

Operating and Storage TemperatureRange

TJ, Tstg –55 to150

°C

Single Pulse Drain–to–Source AvalancheEnergy – Starting TJ = 25°C(VDD = 75 Vdc, VGS = 10 Vdc,IL = 27 Apk, L = 0.3 mH, RG = 25 Ω)

EAS 109 mJ

Thermal Resistance– Junction to Case– Junction to Ambient

RθJCRθJA

1.262.5

°C/W

Maximum Lead Temperature for SolderingPurposes, 1/8″ from case for 10seconds

TL 260 °C

27 AMPERES100 VOLTS

RDS(on) = 70 mΩ

Preferred devices are recommended choices for future useand best overall value.

Device Package Shipping

ORDERING INFORMATION

MTP27N10E TO–220AB 50 Units/Rail

TO–220ABCASE 221A

STYLE 5

12

3

4

http://onsemi.com

N–Channel

D

S

G

MARKING DIAGRAM& PIN ASSIGNMENT

MTP27120E = Device CodeLL = Location CodeY = YearWW = Work Week

MTP27N10ELLYWW

1Gate

3Source

4Drain

2Drain

MTP27N10E

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3.)(VGS = 0 Vdc, ID = 0.25 mAdc)Temperature Coefficient (Positive)

V(BR)DSS100–

–120

––

VdcmV/°C

Zero Gate Voltage Drain Current(VDS = 100 Vdc, VGS = 0 Vdc)(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)

IDSS––

––

10100

µAdc

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc

ON CHARACTERISTICS (Note 1.)

Gate Threshold Voltage (Cpk ≥ 2.0) (Note 3.)(VDS = VGS, ID = 250 µAdc)Threshold Temperature Coefficient (Negative)

VGS(th)2.0–

3.17.0

4.0–

VdcmV/°C

Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Note 3.)(VGS = 10 Vdc, ID = 13.5 Adc)

RDS(on)– 0.058 0.07

Ohm

Drain–to–Source On–Voltage(VGS = 10 Vdc, ID = 27 Adc)(VGS = 10 Vdc, ID = 13.5 Adc, TJ = 125°C)

VDS(on)––

––

2.32.0

Vdc

Forward Transconductance (VDS = 7.7 Vdc, ID = 13.5 Adc) gFS 6.0 11 – mhos

DYNAMIC CHARACTERISTICS

Input Capacitance(V 25 Vd V 0 Vd

Ciss – 1131 1580 pF

Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,f = 1.0 MHz)

Coss – 468 660

Transfer Capacitancef = 1.0 MHz)

Crss – 186 370

SWITCHING CHARACTERISTICS (Note 2.)

Turn–On Delay Time td(on) – 13 30 ns

Rise Time (VDD = 50 Vdc, ID = 27 Adc,VGS = 10 Vdc

tr – 142 280

Turn–Off Delay TimeVGS = 10 Vdc,

RG = 9.1 Ω) td(off) – 29 60

Fall Time

RG 9.1 Ω)

tf – 59 120

Gate Charge(S Fi 8)

QT – 41 60 nC(See Figure 8)

(VDS = 80 Vdc, ID = 27 Adc, Q1 – 9.0 –(VDS 80 Vdc, ID 27 Adc,VGS = 10 Vdc) Q2 – 25 –

Q3 – 22 –

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage(IS = 27 Adc, VGS = 0 Vdc)

(IS = 27 Adc, VGS = 0 Vdc, TJ = 125°C)

VSD––

1.00.94

1.5–

Vdc

Reverse Recovery Time trr – 126 – ns

(IS 27 Adc VGS 0 Vdcta – 98 –

(IS = 27 Adc, VGS = 0 Vdc,dIS/dt = 100 A/µs) tb – 28 –

Reverse Recovery StoredCharge

dIS/dt = 100 A/µs)

QRR – 0.685 – µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance(Measured from contact screw on tab to center of die)(Measured from the drain lead 0.25″ from package to center of die)

LD– 3.5

4.5–

nH

Internal Source Inductance(Measured from the source lead 0.25″ from package to source bond pad)

LS – 7.5 – nH

1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.2. Switching characteristics are independent of operating junction temperature.3. Reflects typical values.

Cpk =Max limit – Typ

3 x SIGMA

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TYPICAL ELECTRICAL CHARACTERISTICSR

DS

(on)

, DR

AIN

-TO

-SO

UR

CE

RE

SIS

TAN

CE

(NO

RM

ALI

ZE

D)

RD

S(o

n), D

RA

IN-T

O-S

OU

RC

E R

ES

ISTA

NC

E (

OH

MS

)

RD

S(o

n), D

RA

IN-T

O-S

OU

RC

E R

ES

ISTA

NC

E (

OH

MS

)

0 2 4 6 8 100

30

50

60

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

I D, D

RA

IN C

UR

RE

NT

(AM

PS

)

I D, D

RA

IN C

UR

RE

NT

(AM

PS

)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0 10 20 400

0.02

0.06

0.1

0.14

0 10 40 600.04

0.05

0.06

0.07

0.08

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Currentand Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Currentand Gate Voltage

-500

0.4

1.2

2.0

2 4 6 8 9 101

10

100

1000

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with Temperature

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source LeakageCurrent versus Voltage

I DS

S, L

EA

KA

GE

(nA

)

-25 0 25 50 75 100 125 150

TJ = 25°C VDS ≥ 10 V

TJ = -55°C

25°C

100°C

TJ = 100°C

25°C

-55°C

TJ = 25°CVGS = 10 V

20

40

1 3 5 7 9

10

9 V

5 V

6 V

7 V

8 V

VGS = 10 V

0

30

50

60

20

40

10

2 3 4 5 6 7 8 9 10

0.12

0.08

0.04

30 50 60

0.075

0.065

0.055

0.045

20 30 50

0.8

1.6

2.4

3 5 7

VGS = 10 V

15 V

VGS = 10 V

ID = 13.5 A

0.2

0.6

1.4

2.2

1.0

1.8

10

VGS = 0 V

TJ = 125°C

100°C

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predictedby recognizing that the power MOSFET is chargecontrolled. The lengths of various switching intervals (∆t)are determined by how fast the FET input capacitance canbe charged by current from the generator.The published capacitance data is difficult to use forcalculating rise and fall because drain–gate capacitancevaries greatly with applied voltage. Accordingly, gatecharge data is used. In most cases, a satisfactory estimate ofaverage input current (IG(AV)) can be made from arudimentary analysis of the drive circuit so that

t = Q/IG(AV)During the rise and fall time interval when switching aresistive load, VGS remains virtually constant at a levelknown as the plateau voltage, VSGP. Therefore, rise and falltimes may be approximated by the following:

tr = Q2 x RG/(VGG – VGSP)tf = Q2 x RG/VGSPwhere

VGG = the gate drive voltage, which varies from zero to VGGRG = the gate drive resistanceand Q2 and VGSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current isnot constant. The simplest calculation uses appropriatevalues from the capacitance curves in a standard equation forvoltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG – VGSP)]td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve ata voltage corresponding to the off–state condition whencalculating td(on) and is read at a voltage corresponding to theon–state when calculating td(off).

At high switching speeds, parasitic circuit elementscomplicate the analysis. The inductance of the MOSFETsource lead, inside the package and in the circuit wiringwhich is common to both the drain and gate current paths,produces a voltage at the source which reduces the gate drivecurrent. The voltage is determined by Ldi/dt, but since di/dtis a function of drain current, the mathematical solution iscomplex. The MOSFET output capacitance alsocomplicates the mathematics. And finally, MOSFETs havefinite internal gate resistance which effectively adds to theresistance of the driving source, but the internal resistanceis difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gateresistance (Figure 9) shows how typical switchingperformance is affected by the parasitic circuit elements. Ifthe parasitics were not present, the slope of the curves wouldmaintain a value of unity regardless of the switching speed.The circuit used to obtain the data is constructed to minimizecommon inductance in the drain and gate circuit loops andis believed readily achievable with board mountedcomponents. Most power electronic loads are inductive; thedata in the figure is taken with a resistive load, whichapproximates an optimally snubbed inductive load. PowerMOSFETs may be safely operated into an inductive load;however, snubbing reduces switching losses.

10 0 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

C, C

AP

AC

ITA

NC

E (

pF)

Figure 7. Capacitance Variation

3500

2500

1500

500

0

VGS VDS

TJ = 25°CVDS = 0 V VGS = 0 V

3000

2000

1000

5 5

Ciss

Coss

Ciss

Crss

Crss

15

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DRAIN–TO–SOURCE DIODE CHARACTERISTICS

1.10.6 0.7 0.8 0.9 1.050

10

25

30

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 8. Gate–To–Source and Drain–To–SourceVoltage versus Total Charge

I S, S

OU

RC

E C

UR

RE

NT

(AM

PS

)

Figure 9. Resistive Switching TimeVariation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1 10 100

1000

10

t, T

IME

(ns

)

tr

tf

td(off)

td(on)

VGS = 0 V

TJ = 25°C

Figure 10. Diode Forward Voltage versus Current

60V

GS

, GA

TE

-TO

-SO

UR

CE

VO

LTA

GE

(V

OLT

S)

54

48

42

36

30

24

0

9

7

4

0

QG, TOTAL GATE CHARGE (nC)

VD

S, D

RA

IN-T

O-S

OU

RC

E V

OLTA

GE

(VO

LTS

)

10

8

2

5 10 15 20 45

TJ = 25°C

ID = 27 A

VDS

VGS

250

Q1 Q2

QT

Q3

100

5

15

0.65 0.75 0.85 0.95 1.0

VDD = 50 V

ID = 27 A

VGS = 10 V

TJ = 25°C

30 35 40

6

5

3

1

18

12

6

1

20

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves definethe maximum simultaneous drain–to–source voltage anddrain current that a transistor can handle safely when it isforward biased. Curves are based upon maximum peakjunction temperature and a case temperature (TC) of 25°C.Peak repetitive pulsed power limits are determined by usingthe thermal response data in conjunction with the proceduresdiscussed in AN569, “Transient ThermalResistance–General Data and Its Use.”

Switching between the off–state and the on–state maytraverse any load line provided neither rated peak current(IDM) nor rated voltage (VDSS) is exceeded and thetransition time (tr,tf) do not exceed 10 µs. In addition the totalpower averaged over a complete switching cycle must notexceed (TJ(MAX) – TC)/(RθJC).

A Power MOSFET designated E–FET can be safely usedin switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductancedissipated in the transistor while in avalanche must be lessthan the rated limit and adjusted for operating conditionsdiffering from those specified. Although industry practice isto rate in terms of energy, avalanche energy capability is nota constant. The energy rating decreases non–linearly with anincrease of peak current in avalanche and peak junctiontemperature.

Although many E–FETs can withstand the stress ofdrain–to–source avalanche at currents up to rated pulsedcurrent (IDM), the energy rating is specified at ratedcontinuous current (ID), in accordance with industrycustom. The energy rating must be derated for temperatureas shown in the accompanying graph (Figure 12). Maximumenergy at currents below rated continuous ID can safely beassumed to equal the values indicated.

MTP27N10E

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SAFE OPERATING AREA

TJ, STARTING JUNCTION TEMPERATURE (°C)

E AS

, SIN

GLE

PU

LSE

DR

AIN

-TO

-SO

UR

CE

Figure 11. Maximum Rated Forward BiasedSafe Operating Area

0.1 1.0 100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Avalanche Energy versusStarting Junction Temperature

0.1

10

1000

AV

ALA

NC

HE

EN

ER

GY

(m

J)

I D, D

RA

IN C

UR

RE

NT

(AM

PS

)

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT0.01 0

25 50 75 100 125

40

20

ID = 27 A

100

1.0

10 150

t, TIME (s)

Figure 13. Thermal Response

r(t)

, NO

RM

ALI

ZE

D E

FF

EC

TIV

E

TR

AN

SIE

NT

TH

ER

MA

L R

ES

ISTA

NC

E

RθJC(t) = r(t) RθJCD CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1TJ(pk) - TC = P(pk) RθJC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1/t2

Figure 14. Diode Reverse Recovery Waveform

di/dt

trr

ta

tp

IS

0.25 IS

TIME

IS

tb

VGS = 20 V

SINGLE PULSETC = 25°C

0.2

0.1

0.050.02

0.01

SINGLE PULSE

D = 0.5

120

80

60

100

0.1

1.0

0.01

100µs

1ms

10msdc

1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01

1000

10µs

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PACKAGE DIMENSIONS

TO–220 THREE–LEADTO–220AB

CASE 221A–09ISSUE AA

STYLE 5:PIN 1. GATE

2. DRAIN3. SOURCE

4. DRAIN

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES AREALLOWED.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.570 0.620 14.48 15.75

B 0.380 0.405 9.66 10.28

C 0.160 0.190 4.07 4.82

D 0.025 0.035 0.64 0.88

F 0.142 0.147 3.61 3.73

G 0.095 0.105 2.42 2.66

H 0.110 0.155 2.80 3.93

J 0.018 0.025 0.46 0.64

K 0.500 0.562 12.70 14.27

L 0.045 0.060 1.15 1.52

N 0.190 0.210 4.83 5.33

Q 0.100 0.120 2.54 3.04

R 0.080 0.110 2.04 2.79

S 0.045 0.055 1.15 1.39

T 0.235 0.255 5.97 6.47

U 0.000 0.050 0.00 1.27

V 0.045 --- 1.15 ---

Z --- 0.080 --- 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATINGPLANE–T–

CST

U

R

J

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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MTP27N10E/D

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