Microelectronics Reliability 55 (2015) 2229–2235

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Microelectronics Reliability

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Investigation on SCR-based ESD protection device for biomedicalintegrated circuits in a 0.18-μm CMOS process

Chun-Yu Lin a,b,⁎, Yan-Lian Chiu a

a Department of Electrical Engineering, National Taiwan Normal University, Taiwanb Biomedical Electronics Translational Research Center, National Chiao Tung University, Taiwan

⁎ Corresponding author at: Department of ElectricalNormal University, Taiwan.

http://dx.doi.org/10.1016/j.microrel.2015.02.0200026-2714/© 2015 Elsevier Ltd. All rights reserved.

a b s t r a c t

a r t i c l e i n f o

Article history:Received 16 November 2014Accepted 20 February 2015Available online 10 March 2015

In these decades, integrated circuits for biomedical electronics applications have been designed and im-plemented in CMOS technologies. In order to be safely used by human, all microelectronic productsmust meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into con-sideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, adual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimentalresults show that the DDSCR has the advantages of high ESD robustness, low leakage, large swingtolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical inte-grated circuits.

© 2015 Elsevier Ltd. All rights reserved.

Keywords:BiomedicalCMOSElectrostatic discharge (ESD)Silicon-controlled rectifier (SCR)

1. Introduction

As medical science and electronics engineering evolving, bioelec-tronics combined the microelectronics technology with medicineknowledge results in a new generation of healthcare and therapy. In re-cent decades, the inseparable relationship between electrical transac-tion and nervous system has been studied [1]. The electricalstimulation that transmitted artificial electrical signals into nervous sys-tem has been verified for innovative medical treatments, including thetherapeutic electrical stimulation (TES) and the functional electricalstimulation (FES) [2–4]. The electrical stimulations have been success-fully used in a large set of applications, such as cardiac pacemaker, co-chlear implant, muscle exercising, vision restoration, and seizuresuppression. Comparing with the traditional treatments by using med-icine or surgery, the electrical stimulation is more harmless, flexible, re-coverable, and less-destructive [5,6].

CMOS technologies are attractive to implement the integratedcircuits for biomedical electronics applications [7–9]. However, thetransistors currently used in CMOS technologies are vulnerable toelectrostatic discharge (ESD) events, which is the major reliabilityconcern. In order to sustain the required ESD robustness, the on-chip ESD protection devices must be added in the IC products. A

Engineering, National Taiwan

typical specification for a commercial IC on human-body-model(HBM) ESD robustness is 2 kV [10]. If consider the reliability of bio-medical integrated circuits used on the human, the required ESD ro-bustness may be even higher.

In thiswork, a novel ESD protection design for electrical stimulator isinvestigated in a 0.18-μm 1.8-V/3.3-V CMOS process.

2. Architecture of electrical stimulator

Some fundamental biophysical analyses of excitable membraneproperties have usedmonophasic stimulation in order to simplify inter-pretation of the results [11,12]. However, the monophasic stimulationcan be safely used only during short pulses and at low intensities [13].Using the biphasic stimulation could avoid charge accumulation intissues.

To realize the biphasic stimulation, the commonly used configura-tions of monopolar and bipolar stimulators are shown in Figs. 1 and 2[14,15]. In Fig. 1, the bipolar stimulator utilizes the single supply voltage(VHH) with single output driver from VHH. In Fig. 2, themonopolar stim-ulator utilizes the dual supply voltages (VHH and VLL) with anodic andcathodic output drivers to deliver anodic and cathodic stimulus cur-rents. The anodic and cathodic stimulus currents of the bipolar stimula-tor are generated by reversing the current paths using switches. Themonopolar stimulation is preferred over a bipolar counterpart if the cur-rent is intended to spread over a wider area, and the monopolar stimu-lation is usually more efficient than the bipolar stimulation [16]. On the

Fig. 1. Biphasic stimulator with bipolar configuration.

Fig. 2. Biphasic stimulator with monopolar configuration.

Fig. 3. Biomedical integrated circuits with large signal swing.

Fig. 4. Cross-sectional view of conventional ESD protection d

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other hand, in the simultaneous stimulation using electrode arrays, thebipolar stimulation is preferred tomonopolar stimulation, as the formercan reduce crosstalk among neighboring sites [17].

For some biomedical electronics applications, the signal swing atinput/output (I/O) pads may be higher than the supply voltage (VDD)or lower than 0 V (GND) [18]. To prevent from the reliability issuessuch as electrical overstress, the stacked MOS configuration is used todesign the biomedical integrated circuits in these applications. Ofcourse, the ESD protection devices at I/O pads also need to tolerate thesignal swing which is higher than VDD or lower than 0 V, as illustratedin Fig. 3.

The conventional ESD protection devices have the drawback of leak-age current. Fig. 4 shows the conventional ESD protection devices usedin the CMOS technologies, including diode, gate-grounded NMOS(GGNMOS), silicon-controlled rectifier (SCR), and dual-directional SCR(DDSCR) [19–22]. A parasitic pn junction exists in the conventionalESD protection devices with the common grounded P-substrate, asshown in Fig. 4.

3. ESD robustness of stand-alone output stage of electricalstimulator

The stacked PMOS and NMOS of the output stage of electricalstimulator are shown in Fig. 5(a) and (b), respectively. To investi-gate the I–V characteristics of the stand-alone output stage of elec-trical stimulator under ESD-like conditions, the transmission linepulsing (TLP) system with a 10-ns rise time and a 100-ns pulsewidth is used. The TLP-measured I–V curves of the test devices areshown in Fig. 6. According to the test results, the stacked PMOSand NMOS under ESD-like conditions can sustain up to 27 V and25 V, respectively, without damage (increasing leakage current). Inother word, the additional ESD protection device must clamp theovershoot voltage lower than 25 V to prevent the electrical stimula-tor from ESD damages.

4. ESD protection design for electrical stimulator

4.1. Test devices

In this work, three novel dual-directional SCR (DDSCR) devices forESD protection in biomedical integrated circuits are investigated, in-cluding DDSCR1, DDSCR2, and DDSCR3. These designs are wished toachieve high ESD robustness, low leakage, large swing tolerance, andgood latchup immunity.

For the implementation of DDSCR1, two kinds of layout are shown inFig. 7. In Fig. 7(a) and (b), the SCR paths are divided into 4 and 8 seg-ments, respectively. The SCR paths consist of P+/P-well/N-well/P-well/N+. The SCR paths along A–A′ and B–B′ provide the dischargingpath from I/O to GND and from GND to I/O, respectively, as shown inFig. 8. The distance between I/O and GND of SCR is wished to be mini-mized, so the layout style with minimized “d” is used. The turn-on

evices: (a) diode, (b) GGNMOS, (c) SCR, and (d) DDSCR.

Fig. 5. Cross-sectional view of output stage of electrical stimulator: (a) stacked PMOS and (b) stacked NMOS.

Fig. 6.Measured TLP I–V curves of (a) stacked PMOS and (b) stacked NMOS.

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resistance of SCR can be lowered by using this layout style. The triggervoltage of DDSCR1 is mainly determined by the breakdown voltage ofN-well/P-well junction.

To reduce the trigger voltage, additional N+ was added into theDDSCR2, as shown in Fig. 9. The SCR paths along A–A′ and B–B′ still con-sist of P+/P-well/N-well/P-well/N+. In the beginning of ESD stress, theN+/P-well junctionwill breakdown to discharge the initial current, andthen the SCR path will take over to discharge the primary current. Twokinds of layout of DDSCR2 with 4 and 8 segments are implemented.

To further reduce the trigger voltage, additional P-implantation [23]was added into the DDSCR3, as shown in Fig. 10. The SCR paths along A–A′ and B–B′ still consist of P+/P-well/N-well/P-well/N+. In the begin-ning of ESD stress, the N+/P-junction will breakdown to discharge theinitial current, and then the SCR pathwill take over to discharge the pri-mary current. Two kinds of layout of DDSCR3 with 4 and 8 segments areimplemented.

All the dimensions of test devices are listed in Table 1. These test de-vices have been fabricated in a 0.18-μm 1.8-V CMOS process.

Fig. 7. Layout top view of DDSCR1 with (a) 4 segments and (b) 8 segments.

Fig. 8. Cross-sectional view of DDSCR1 along (a) A–A′ and (b) B–B′.

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4.2. Measured ESD robustness

The HBM ESD robustness of test devices are evaluated by the ESDtester. The failure criterion is defined as the I–V characteristics shiftingover 30% from its original curve after ESD stressed at every ESD testlevel. All these measurement results are listed in Table 1.

4.3. Measured TLP I–V characteristics

To investigate the turn-on behavior and the I–V characteristics inhigh-current regions of the ESD protection devices, the transmission-line-pulsing (TLP) system with 10-ns rise time and 100-ns pulsewidth is used. The TLP-measured I–V characteristics are shown in

Fig. 9. Cross-sectional view of DDSCR2 along (a) A–A′ and (b) B–B′.

Fig. 10. Cross-sectional view of DDSCR3 along (a) A–A′ and (b) B–B′.

Table 1Summary of test devices.

Test device w (μm) d (μm) s (μm) x1 (μm) x2 (μm) x3 (μm) x4 (μm) x5 (μm) HBM Level (kV) Vt1 (V) Vh (V) It2 (A) C (fF)

DDSCR1 with 4 segments 20 2.26 5 1.29 0.43 1.4 N/A N/A 2 11.5 2.0 0.8 67.140 2.26 10 1.29 0.43 1.4 N/A N/A 4 11.5 2.0 1.6 110.560 2.26 15 1.29 0.43 1.4 N/A N/A 5 11.6 1.9 2.3 154.9

DDSCR1 with 8 segments 20 2.26 2.5 1.29 0.43 1.4 N/A N/A 2 11.8 2.3 0.8 70.640 2.26 5 1.29 0.43 1.4 N/A N/A 3.5 11.6 2.3 1.6 116.460 2.26 7.5 1.29 0.43 1.4 N/A N/A 5 11.6 2.2 2.4 163.1

DDSCR2 with 4 segments 20 2.26 5 1.29 0.92 0.42 0.8 1.5 2 10.4 2.0 0.8 74.940 2.26 10 1.29 0.92 0.42 0.8 1.5 3.5 10.5 1.9 1.5 121.060 2.26 15 1.29 0.92 0.42 0.8 1.5 5 10.4 1.9 2.3 167.8

DDSCR2 with 8 segments 20 2.26 2.5 1.29 0.92 0.42 0.8 1.5 2 10.4 2.0 0.8 78.940 2.26 5 1.29 0.92 0.42 0.8 1.5 3.5 10.4 2.0 1.5 127.460 2.26 7.5 1.29 0.92 0.42 0.8 1.5 4.5 10.4 2.0 2.2 176.7

DDSCR3 with 4 segments 20 2.26 5 1.29 0.92 0.42 0.8 1.5 2 9.2 2.0 0.7 62.540 2.26 10 1.29 0.92 0.42 0.8 1.5 3.5 9.2 1.9 1.5 116.760 2.26 15 1.29 0.92 0.42 0.8 1.5 5 9.2 2.0 2.2 169.5

DDSCR3 with 8 segments 20 2.26 2.5 1.29 0.92 0.42 0.8 1.5 2 9.2 2.0 0.8 80.140 2.26 5 1.29 0.92 0.42 0.8 1.5 3.5 9.2 2.0 1.5 128.060 2.26 7.5 1.29 0.92 0.42 0.8 1.5 4.5 9.2 2.0 2.2 177.3

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Figs. 11–13. The trigger voltages (Vt1) of the test devices are about9–12 V, which means the ESD protection devices can sustain the signalswing up to ±9 V. The secondary breakdown current (It2) of ESD

protection device, which indicated the current-handling ability, canalso be obtained from the TLP-measured I–V curves. All these measure-ment results are also listed in Table 1.

Fig. 11.Measured TLP I–V curves of DDSCR1 with (a) 4 segments and (b) 8 segments.

Fig. 12.Measured TLP I–V curves of DDSCR2 with (a) 4 segments and (b) 8 segments.

Fig. 13.Measured TLP I–V curves of DDSCR3 with (a) 4 segments and (b) 8 segments.

Fig. 14.Measured parasitic capacitances.

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4.4. Measured parasitic capacitance

With the on-wafer measurement, the two-port S-parameters of thetest devices were measured by using the vector network analyzer. Theparasitic effects of the pads have been removed by using the de-embedding technique [24]. The parasitic capacitance of each test devicecan be extracted from the S-parameters. Fig. 14 shows the extractedparasitic capacitance of the test devices.

4.5. Measured latchup immunity

To evaluate the latchup immunity of the test devices, the transient-induced latchup (TLU) was tested [25,26]. A 200-pF charging capacitoris used to store the charges as the TLU-triggering source, and then thestored charges are discharged to the test device through the relay.Among the test devices, the DDSCR1 with 4 segments and w = 60 μm

Fig. 15.Measured voltage waveforms on DDSCR1 with 4 segments and w = 60 μm under TLU tests with charging voltage of (a) +20 V and (b)−20 V.

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has the lowest holding voltage and the highest latchup danger.Fig. 15(a) and (b) shows the measured transient voltage waveforms ofthe DDSCR1 with 4 segments and w = 60 μm under the TLU tests withcharging voltage of +20 V and −20 V, respectively. Before the TLUtests, the voltage across the test device was 1.8 V, which is the VDD volt-age of the stimulator system [18]. During the TLU tests, the measuredvoltage waveforms are influenced simultaneously by the underdampedsinusoidal voltage. After the TLU tests, the voltage across the test devicewas returned to 1.8 V. From the TLU test results, the test device can im-mune to the latchup issue.

5. Conclusion

The dual-directional SCR devices have been developed for on-chipESD protection in biomedical integrated circuits where the signalswing may be higher than VDD or lower than 0 V. The dual-directionalSCR paths consist of P+/P-well/N-well/P-well/N+. Several test deviceswith different dimensions have been investigated in 0.18-μm CMOSprocess. According to the measurement results, the DDSCR devices canachieve the targets of high ESD robustness, low leakage, large swing tol-erance, and good latchup immunity.

Acknowledgments

This work was supported by Ministry of Science and Technology,Taiwan, under Contract MOST 103-2220-E-003-001, 103-2220-E-009-007, and MOST 103-2221-E-009-197-MY2, by Biomedical ElectronicsTranslational Research Center, National Chiao Tung University, Taiwan,and by National Taiwan Normal University, Taiwan. The authorswould like to thank Prof. Ming-Dou Ker and Ms. Mei-Lian Fan, NationalChiao Tung University, Taiwan, for their great help during design andmeasurement.

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