Proceedings of 1998 International Symposium on Power Semiconductor Devices & ICs, Kyoto 5.4

A NConolithic IGBT Gate Driver Implemented in a Conventional 0.8pm BiCMOS process

Mehrdad Ramezani and C . Andre T. Salama

Department of Electrical and Computer Engineering, University of Toronto, 10 King’s College Rd., Toronto, Ontario, Canada M5S3G4

Tel: 416-978-8658 /Fax: 416-978-4576

Abstract

This paper discusses the design and implementation of a monolithic gate driver for an Insulated Gate Bipolar Transistor (IGBT). The objective is to implement a high voltage (25V) monolithic gate driver with an efficient protection circuit in a conventional low-vo1l:age (5V) high-density (0.8pm) BiC- MOS process. Extended drain MOSFTs are used to implement the high-voltage capability in this design.

Introduction

An effective IGBT gate: driver must interface with a microcon- troller, have the voltage and current capability to turn-on/off the IGBT [l], and be able to protect the IGBT in fault situa- tions. In recent years, various processes have been used to implement monolithic IGBT gate drivers [2,3]. In most of these designs, the proc1:ss used to implement the high-voltage gate driver circuitry is usually different from the one used to implement the low-voltage controller circuits. The objective of this work is to implement the high voltage portion of the IGBT driver in a conventional low-voltage (SV) high density (0.8pm) BiCMOS process [4], in which the high-voltage capa- bility is achieved, without adding any extra mask layers, using extended drain MOS transistor [5,6]. This process would be ideally suited for the implementation of the low-voltage con- troller circuitry, thus resulting in a microcontroller plus high- voltage driver on a single chip.

In this paper, the implementation of high voltage devices in a low-voltage BiCMOS process is discussed. The design and experimental implementation of the high voltage driving blocks and the protection circuitry of the IGBT gate driver are presented.

High Voltage Devices Implementation

Fig. 1 shows the high-voltage high-current device implementa- tion in a low-voltage BiCMOS process. The structures of high-voltage NMOS arid PMOS transistors are shown in Fig. 1 The high doping region of the drain connection is extended by a low doping “well” region in order to increase the breakdown voltage at the drain-bulk junction. The increase in breakdown voltage is proportional to the length and the doping profile of the extended drain. The layout of the high-voltage transistor

cells are shown in Fig. 2. In these layouts, the corners are rounded to increase the breakdown voltage. The source is placed around the cell. The IV characteristics of the high-volt- age NMOS and high-voltage PMOS transistors are illustrated in Fig. 3. The configuration of large aspect ratio high-voltage high-current NMOS and PMOS transistors are made up of interdigated, interconnected individual transistor cells shown in Fig. 4.

The Gate Driver Architecture

The schematic of the monolithic gate driver is shown in Fig.2. The high voltage interface circuits consist of a biasing circuit, a level shifter, a logic controller and a high voltage high cur- rent output driver [7]. The other circuits, such as unintentional IGBT switching protection, over-voltage sensing, timer and pulse stretcher are parts of the protection circuitry.

A. High Voltage interjiuce

In Fig. 5, the shaded blocks show the main driving path inside the logic controller circuit. Low-power input pulses define the on/off time of the IGBT. However, the voltage and current capability of these signals are not enough to drive the IGBT directly. Once voltage level of the input pulses is adjusted by the level shifter, several stages of buffering are necessary to provide the signal needed to drive the IGBT. Transistors M3 1, M32 and M33 make up the output high-voltage, high-current stage, which drives the gate of the IGBT. When the input volt- age to the gate driver changes from high to low, the output of the level shifter rises, and transistor M31 turns on through Comparator2 and inverter 18. At the same time transistors M32 and M33 are turned off by inverters 11, 12, I3 and buffer B5 and inverters 11, 14, I5 and buffer B6, respectively. This results in the drain current of M31 charging the IGBT gate capacitance and the voltage across that capacitance increases to Vdd(l5V). When the input voltage to the gate driver rises, transistors M32 and M33 turn on, transistor M3 1 turns off and the IGBT gate capacitance discharges to Vss (-1OV) through the drain current of transistors M32 and M33. Capacitor C1 creates a small delay in the turn on/off time of the sourcing transistor M31 and the sinking transistors M32, M33 to avoid simultaneously turning on these transistors and short circuit- ing Vdd to Vss. Either transistors M32 and M33 can be used to turn off the IGBT by discharging its gate capacitance.

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Transistor M33 has a smaller width than M32 to allow slower turn off of the IGBT under desaturation conditions. More details about this slow turn-off are presented in the fol- lowing section.

B. Protection Circuitry

The gate driver includes unintentional switching and desatu- ration failure protection circuits. The unintentional IGBT switching protection circuit monitors the rail-to-rail power supply voltage and shuts down the system if the gate driver output voltage is not enough to drive the IGBT efficiently.

A desaturation failure occurs if a short circuit appears across the load while the IGBT is ‘on’. In this fault situation, the protection circuit must turn off the IGBT. This turn-off is implemented in a step by step process to avoid high di/dt through the inductances in the circuit. To fulfill this require- ment, a state-of-the-art protection circuit is included in this design. The desaturation protection circuit includes over- voltage sensing, a timer and a pulse stretcher circuit.

In Fig. 5 once a desaturation failure occurs, the output volt- age of the over-voltage sensing block (Vf) rises and the IGBT turns off in three successive steps, shown in Fig. 6. First, the IGBT gate voltage falls to help increase the short circuit withstanding time of the IGBT. This voltage reduc- tion is achieved by turning on transistors M32 and M33 and turning off transistor M3 1 for a short period of time, defined by the capacitor C3 and resistor R10. Transistors M25, M27 and M29 are used to turn off M31 and turn on M32 and M33, respectively. Subsequently, after a delay of Atl (cre- ated by the timer at the output T1) transistor M30 turns on and results in the turn-on of M33 through inverter I5 and buffer B6. The IGBT gate capacitance discharges through the drain current of M33 and the device turns off slowly releasing the energy stored in the inductances of the circuit. Finally, after time At2 (defined by the timer at the output T2), when the IGBT is almost off, M32 and M33 are turned on by M26 and M28, respectively and reduce the gate voltage of the IGBT to Vss. The timing durations At1 and At2 can be adjusted through external capacitors C4 and C5, respec- tively.

When the IGBT is in off state, the output signal of inverter I7 (PC) disables the over voltage sensing circuit to prevent a premature protection recovery. When an ‘on’ signal is sent to the IGBT, capacitor C2 creates a small delay before I7 enables the over-voltage sensing circuit again. This delay gives enough time to the output voltage of the IGBT to drop below its predefined ‘on’ voltage (Von), prior to the over voltage sensing circuit being activated.

The output of the timer (T2) is connected to the input of the pulse stretcher circuit. Each time a fault situation is recov- ered by the protection circuit, the output of the timer creates

a pulse. The pulse stretcher measures the number of the suc- cessive fault situations occurring in a predefined period of time. If the fault situation lasts for a significant time, the pulse stretcher sends a signal to the output of the gate driver to inform a permanent failure in the system to shut down the system.

Experimental Results

Fig. 7 shows the micrograph of the implemented IGBT gate driver. The IGBT gate driver output waveform in normal drive is shown in Fig. 8. In the frequency of lOKHz, the gate driver shows a neat driving waveform for a lOnF equivalent IGBT gate capacitance. The output of the gate driver in desaturation failure is shown in Fig. 9. The three steps of the desaturation protection are shown in this figure. The summary of the IGBT gate driver characteristics for a lOnF equivalent IGBT gate capacitance is given in Table 1 . The experimental results for the gate driver are generally in good agreement (+20) with the simulation results.

Conclusion

A monolithic IGBT gate driver design, implemented in a low voltage BiCMOS process, was proposed. Using a low- voltage high-density process for this work allows the high- density controlling circuits and the high-voltage circuits of the gate driver on one chip, resulting in cost reduction and enhanced reliability.

Acknowledgments

The authors would like to thank Allied Signal Aerospace, NSERC and Micronet for their support of this work.

References A. R, Hefner, “ An Analytic Model for the Steady-State and Tran- sient Characteristic of the Power Insulated Gate Bipolar Transistor”, Solid-state Electronics, Vol. 31, pp. 1513-1532, 1988.

C. Kuratli, Q. Huang, A. Biber, ” Implementation of High Peak Cur- rent IGBT Gate Driver in a VLSI Compatible BiCMOS Technol- ogy’’, IEEE J. of Solid State Circuits, Vol. 31, pp.924-932, 1996.

B. Murari, E Bertotti, G.A. Vignola, “Smart Power ICs, Technolo- gies and Applications”, Springer, New York, 1996.

R. Hadaway, P. Kemp, P. Schan, M. Rowlandson, V. Ha, J. Kolt, B. Tait, D. Sutherland, G. Jolly, I . Emesh, “A Sub-micron BiCMOS Technology for Telecommunications”, European Solid State Device Research Conference(ESSDERC), pp.513-516, 1991,

M. Liu, C.A.T. Salama, P. Schvan, M. King, “A Fully Resurfed, BiC- MOS Compatible, high Voltage MOS Transistor”, ISPSD, pp,143- 146,1996.

Y. Q. Li, C.A.T. Salama, M. Seufert, P. Schvan, M. King, “Submi- cron BiCMOS Compatible High Voltage MOS Transistors”, ISPSD, pp.355-359, 1994.

R. S. Chokhawala, J. Catt, B. R. Pelly, “ Gate Driver Consideration for IGBT Modules”, IEEE Transactions on Industry Applications, Vol. 31, pp. 603-611, 1995.

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Lext.

F'well Nwell Nwell Pwell Extended drain Extended drain - - - - N-buried Layer N-burled Layer

..............................................................................

P- Substrate P- Substrate

(a) HV-NMOS Structure (b) HV-PMOS Structure Fig. 1 Structure of the High-Voltage MOS Transistors

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Fig. 2 Layout of the High-Voltage MOS Transistor Cells

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Fig. 3 IV Characteristics of the High-Voltage MOS Transistor Cells

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Fig. 4 Layout of the Interdigated High-Voltage Transistors

111

.. ......................................................................., Gate Driver

Simulation

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690 ns 380 ns

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Fig. 5 The IGBT Gate Driver Schematic

Experimental 4.82 mmL 15V, -lOV

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3ps to 15ps 200 mW 400 mW

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Fig. 7 The Micrograph of the Implemented IGBT Gate Driver

TABLE 1 SUMMARY OF THE IGBT GATE DRIVER CHARACTERISTICS

(IGBT input Capacitance = 10nF)

Parameter Total die area (including pads) Gate Driver Power Supply IGBT gate tum-on voltage IGBT gate tum-off voltage Current driving capability Rise time (IGBT Cg = 1OnF) Fall time (IGBT Cg = 10nF) Protection recovery time - adjustable Static Power dissipation Total Power dissipation

127 112 117 122

.....

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Fig. 6 The Desaturation Protection Steps at the Output of thr Gate Driver

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20 40 60 80 100 120

Time ( p s)

Fig. 8 The IGBT Gate Driver Waveform in Normal Drive

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Fig. 9 The IGBT Gate Driver Waveform in Desaturation Failure

112