Input Offset Voltage DriftTypically D, JG, OR P PACKAGE 0 ... · Vn Equivalent input noise voltage...

TLC271, TLC271A, TLC271BLinCMOS PROGAMMABLE LOW-POWER

OPERATIONAL AMPLIFIERS

SLOS090B – NOVEMBER 1987 – REVISED AUGUST 1996

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Input Offset Voltage Drif t . . . Typically0.1 µV/Month, Including the First 30 Days

Wide Range of Supply Voltages OverSpecified Temperature Range:

0°C to 70°C . . . 3 V to 16 V–40°C to 85°C . . . 4 V to 16 V–55°C to 125°C . . . 5 V to 16 V

Single-Supply Operation

Common-Mode Input Voltage RangeExtends Below the Negative Rail (C-Suffixand I-Suffix Types)

Low Nois e . . . 25 nV/√Hz Typically atf = 1 kHz (High-Bias Mode)

Output Voltage Range includes NegativeRail

High Input Impedanc e . . . 1012 Ω Typ

ESD-Protection Circuitry

Small-Outline Package Option AlsoAvailable in Tape and Reel

Designed-In Latch-Up Immunity

description

The TLC271 operational amplifier combines awide range of input offset voltage grades with lowoffset voltage drift and high input impedance. Inaddition, the TLC271 offers a bias-select modethat allows the user to select the best combination of power dissipation and ac performance for a particularapplication. These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offsetvoltage stability far exceeding the stability available with conventional metal-gate processes.

AVAILABLE OPTIONS

TV

PACKAGE

TAVIOmaxAT 25°C

SMALL OUTLINE

(D)

CHIPCARRIER

(FK)

CERAMICDIP(JG)

PLASTIC DIP(P)

0°C 2 mV TLC271BCD TLC271BCP0 Cto

2 mV5 mV

TLC271BCDTLC271ACD — —

TLC271BCPTLC271ACP

70°C 10 mV TLC271CD TLC271CP

–40°C 2 mV TLC271BID TLC271BIP40 Cto

2 mV5 mV

TLC271BIDTLC271AID — —

TLC271BIPTLC271AIP

85°C 10 mV TLC271ID TLC271IP

–55°Cto

125°C10 mV TLC271MD TLC271MFK TLC271MJG TLC271MP

The D package is available taped and reeled. Add R suffix to the device type (e.g.,TLC271BCDR).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright 1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

1

2

3

4

8

7

6

5

OFFSET N1IN –IN +

GND

BIAS SELECTVDDOUTOFFSET N2

D, JG, OR P PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NCVDDNCOUTNC

NCIN –NC

IN +NC

FK PACKAGE(TOP VIEW)

NC

OF

FS

ET

N1

NC

NC

NC

NC

GN

DN

C

NC – No internal connection

OF

FS

ET

N2

BIA

S S

ELE

CT

LinCMOS is a trademark of Texas Instruments Incorporated.

TLC271, TLC271A, TLC271BLinCMOS PROGAMMABLE LOW-POWEROPERATIONAL AMPLIFIERS


2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DEVICE FEATURES

PARAMETER†BIAS-SELECT MODE

UNITPARAMETER†HIGH MEDIUM LOW

UNIT

PD 3375 525 50 µW

SR 3.6 0.4 0.03 V/µs

Vn 25 32 68 nV/√Hz

B1 1.7 0.5 0.09 MHz

AVD 23 170 480 V/mV

† Typical at VDD = 5 V, TA = 25°C

description (continued)

Using the bias-select option, these cost-effective devices can be programmed to span a wide range ofapplications that previously required BiFET, NFET or bipolar technology. Three offset voltage grades areavailable (C-suffix and I-suffix types), ranging from the low-cost TLC271 (10 mV) to the TLC271B (2 mV)low-offset version. The extremely high input impedance and low bias currents, in conjunction with goodcommon-mode rejection and supply voltage rejection, make these devices a good choice for newstate-of-the-art designs as well as for upgrading existing designs.

In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,without the power penalties of bipolar technology. General applications such as transducer interfacing, analogcalculations, amplifier blocks, active filters, and signal buffering are all easily designed with the TLC271. Thedevices also exhibit low-voltage single-supply operation, making them ideally suited for remote andinaccessible battery-powered applications. The common-mode input voltage range includes the negative rail.

A wide range of packaging options is available, including small-outline and chip-carrier versions for high-densitysystem applications.

The device inputs and output are designed to withstand –100-mA surge currents without sustaining latch-up.

The TLC271 incorporates internal ESD-protection circuits that prevent functional failures at voltages up to 2000V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devicesas exposure to ESD may result in the degradation of the device parametric performance.

The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterizedfor operation from – 40°C to 85°C. The M-suffix devices are characterized for operation over the full militarytemperature range of – 55°C to 125°C.

bias-select feature

The TLC271 offers a bias-select feature that allows the user to select any one of three bias levels dependingon the level of performance desired. The tradeoffs between bias levels involve ac performance and powerdissipation (see Table 1).





bias-select feature (continued)

Table 1. Effect of Bias Selection on Performance

TYPICAL PARAMETER VALUESMODE

UNITTYPICAL PARAMETER VALUES

TA = 25°C, VDD = 5 V HIGH BIAS MEDIUM BIAS LOW BIAS UNITTA = 25 C, VDD = 5 V HIGH BIASRL = 10 kΩ

MEDIUM BIASRL = 100 kΩ

LOW BIASRL = 1 MΩ

PD Power dissipation 3.4 0.5 0.05 mW

SR Slew rate 3.6 0.4 0.03 V/µs

Vn Equivalent input noise voltage at f = 1 kHz 25 32 68 nV/√Hz

B1 Unity-gain bandwidth 1.7 0.5 0.09 MHz

φm Phase margin 46° 40° 34°AVD Large-signal differential voltage amplification 23 170 480 V/mV

bias selection

Bias selection is achieved by connecting the bias select pin to one of three voltage levels (see Figure 1). Formedium-bias applications, it is recommended that the bias select pin be connected to the midpoint between thesupply rails. This procedure is simple in split-supply applications, since this point is ground. In single-supplyapplications, the medium-bias mode necessitates using a voltage divider as indicated in Figure 1. The use oflarge-value resistors in the voltage divider reduces the current drain of the divider from the supply line. However,large-value resistors used in conjunction with a large-value capacitor require significant time to charge up tothe supply midpoint after the supply is switched on. A voltage other than the midpoint can be used if it is withinthe voltages specified in Figure 1.

bias selection (continued)

VDD

1 MΩ

1 MΩ

0.01 µF

Low

Medium

High

To the BiasSelect Pin

BIAS MODEBIAS-SELECT VOLTAGE

(single supply)

Low

Medium

High

VDD1 V to VDD – 1 V

GND

Figure 1. Bias Selection for Single-Supply Applications

high-bias mode

In the high-bias mode, the TLC271 series features low offset voltage drift, high input impedance, and low noise.Speed in this mode approaches that of BiFET devices but at only a fraction of the power dissipation. Unity-gainbandwidth is typically greater than 1 MHz.

medium-bias mode

The TLC271 in the medium-bias mode features low offset voltage drift, high input impedance, and low noise.Speed in this mode is similar to general-purpose bipolar devices but power dissipation is only a fraction of thatconsumed by bipolar devices.




low-bias mode

In the low-bias mode, the TLC271 features low offset voltage drift, high input impedance, extremely low powerconsumption, and high differential voltage gain.

ORDER OF CONTENTS

TOPIC BIAS MODE

schematic all

absolute maximum ratings all

recommended operating conditions all

electrical characteristicsoperating characteristicstypical characteristics

high(Figures 2 – 33)


medium(Figures 34 – 65)


low(Figures 66 – 97)

parameter measurement information all

application information all

equivalent schematic

P3

P1

R1IN –

IN +

P2 R2

P4R6

N5

R5 C1

N3

N2N1

R3 D1

R4

D2N4

OFFSETN1 N2

OFFSET OUT GND

R7

N6

BIASSELECT

N10

N7

N9

N13

N12

N11

P12

P11

P10

P7A P8

P9A

P9B

P7BP6BP6A

P5

VDD





absolute maximum ratings over operating free-air temperature (unless otherwise noted) †

Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input voltage, VID (see Note 2) ±VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (any input) – 0.3 V to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duration of short-circuit current at (or below) 25°C (see Note 3) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M suffix – 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range – 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.2. Differential voltages are at IN+ with respect to IN–.3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded (see application section).

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C

POWER RATINGDERATING FACTORABOVE TA = 25°C

TA = 70°CPOWER RATING



D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW

FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW

JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW

P 1000 mW 8.0 mW/°C 640 mW 520 mW 200 mW

recommended operating conditions

C SUFFIX I SUFFIX M SUFFIXUNIT

MIN MAX MIN MAX MIN MAXUNIT

Supply voltage, VDD 3 16 4 16 5 16 V

Common-mode input voltage VICVDD = 5 V –0.2 3.5 –0.2 3.5 0 3.5

VCommon-mode input voltage, VICVDD = 10 V –0.2 8.5 –0.2 8.5 0 8.5

V

Operating free-air temperature, TA 0 70 –40 85 –55 125 °C




HIGH-BIAS MODE

electrical characteristics at specified free-air temperature (unless otherwise noted)

PARAMETERTEST †

TLC271C, TLC271AC, TLC271BC

UNITPARAMETERTEST

CONDITIONS TA† VDD = 5 V VDD = 10 V UNITCONDITIONS AMIN TYP MAX MIN TYP MAX

V I ff l

TLC271C

V 1 4 V

25°C 1.1 10 1.1 10

VV I ff l

TLC271C

VO = 1 4 VFull range 12 12

VVIO Input offset voltage TLC271AC

VO = 1.4 V,VIC = 0 V, 25°C 0.9 5 0.9 5

mVVIO Input offset voltage TLC271AC VIC 0 V,RS = 50 Ω,R 10 kΩ

Full range 6.5 6.5mV

TLC271BCRL = 10 kΩ

25°C 0.34 2 0.39 2TLC271BC

Full range 3 3

αVIOAverage temperature coefficientof input offset voltage

25°C to70°C 1.8 2 µV/°C

IIO Input offset current (see Note 4)VO = VDD/2, 25°C 0.1 0.1

pAIIO Input offset current (see Note 4)VO VDD/2,VIC = VDD/2 70°C 7 300 7 300

pA

IIB Input bias current (see Note 4)VO = VDD/2, 25°C 0.6 0.7

pAIIB Input bias current (see Note 4)VO VDD/2,VIC = VDD/2 70°C 40 600 50 600

pA

Common-mode input voltage

25°C–0.2

to4

–0.3to

4.2

–0.2to9

–0.3to

9.2V

VICRCommon-mode input voltagerange (see Note 5)

Full range–0.2

to3.5

–0.2to

8.5V

V Hi h l l lV 100 mV

25°C 3.2 3.8 8 8.5

VVOH High-level output voltageVID = 100 mV,RL = 10 kΩ 0°C 3 3.8 7.8 8.5 VOH g p gRL = 10 kΩ

70°C 3 3.8 7.8 8.4

V L l l lV 100 mV

25°C 0 50 0 50

VVOL Low-level output voltageVID = –100 mV,IOL = 0

0°C 0 50 0 50 mVOL p gIOL = 0

70°C 0 50 0 50

ALarge signal differential R 10 kΩ

25°C 5 23 10 36

V/ VAVDLarge-signal differentialvoltage amplification

RL = 10 kΩ,See Note 6

0°C 4 27 7.5 42 V/mVVD voltage amplification See Note 670°C 4 20 7.5 32

CMRR C d j i i V V i

25°C 65 80 65 85

dBCMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 84 60 88 dBj IC ICR70°C 60 85 60 88

kSupply voltage rejection ratio V 5 V to 10 V

25°C 65 95 65 95

dBkSVRSupply-voltage rejection ratio(∆VDD/∆VIO)

VDD = 5 V to 10 VVO = 1.4 V

0°C 60 94 60 94 dBSVR (∆VDD/∆VIO) VO = 1.4 V70°C 60 96 60 96

II(SEL) Input current (BIAS SELECT) VI(SEL) = 0 25°C –1.4 –1.9 µA

I S lVO = VDD/2, 25°C 675 1600 950 2000

AIDD Supply currentVO = VDD/2,VIC = VDD/2,N l d

0°C 775 1800 1125 2200 µADD pp y IC DDNo load 70°C 575 1300 750 1700

µ

† Full range is 0°C to 70°C.NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.





HIGH-BIAS MODE


PARAMETERTEST †

TLC271I, TLC271AI, TLC271BI

UNITPARAMETERTEST


V I ff l

TLC271I

V 1 4 V

25°C 1.1 10 1.1 10

VV I ff l

TLC271I


VVIO Input offset voltage TLC271AI

VO = 1.4 V,VIC = 0 V, 25°C 0.9 5 0.9 5

mVVIO Input offset voltage TLC271AI VIC 0 V,RS = 50 Ω,R 10 kΩ

Full range 7 7mV

TLC271BIRL = 10 kΩ

25°C 0.34 2 0.39 2TLC271BI

Full range 3.5 3.5


25°C to 85°C 1.8 2 µV/°C



pA



pA

VICRCommon-mode input

25°C–0.2

to4

–0.3to

4.2

–0.2to9

–0.3to

9.2V

VICRCommon mode inputvoltage range (see Note 5)

Full range–0.2

to3.5

–0.2to

8.5V


25°C 3.2 3.8 8 8.5

VVOH High-level output voltageVID = 100 mV,RL = 10 kΩ –40°C 3 3.8 7.8 8.5 VOH g p gRL = 10 kΩ

85°C 3 3.8 7.8 8.5

V L l l lV 100 mV

25°C 0 50 0 50


–40°C 0 50 0 50 mVOL p gIOL = 0

85°C 0 50 0 50


25°C 5 23 10 36



–40°C 3.5 32 7 46 V/mVVD voltage amplification See Note 685°C 3.5 19 7 31


25°C 65 80 65 85

dBCMRR Common-mode rejection ratio VIC = VICRmin –40°C 60 81 60 87 dBj IC ICR85°C 60 86 60 88


25°C 65 95 65 95


VDD = 5 V to 10 VVO = 1.4 V

–40°C 60 92 60 92 dBSVR (∆VDD/∆VIO) VO = 1.4 V85°C 60 96 60 96


I S lVO = VDD/2, 25°C 675 1600 950 2000


–40°C 950 2200 1375 2500 µADD pp yNo load 85°C 525 1200 725 1600

µ

† Full range is –40°C to 85°C.NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.





HIGH-BIAS MODE


PARAMETERTEST †

TLC271M

UNITPARAMETERTEST


V I ff l

VO = 1.4 V, 25°C 1 1 10 1 1 10VVIO Input offset voltage

VO = 1.4 V,VIC = 0 V,

25°C 1.1 10 1.1 10mVVIO Input offset voltage VIC 0 V,

RS = 50 Ω,Full range 12 12

mVS ,

RL = 10 kΩ Full range 12 12


25°C to 125°C 2.1 2.2 µV/°C

IIO Input offset current (see Note 4)VO = VDD/2, 25°C 0.1 0.1 pA

IIO Input offset current (see Note 4)VO VDD/2,VIC = VDD/2 125°C 1.4 15 1.8 15 nA

IIB Input bias current (see Note 4)VO = VDD/2, 25°C 0.6 0.7 pA

IIB Input bias current (see Note 4)VO VDD/2,VIC = VDD/2 125°C 9 35 10 35 nA

VICRCommon-mode input voltage

25°C0to4

–0.3to

4.2

0to9

–0.3to

9.2V

VICRCommon mode input voltagerange (see Note 5)

Full range0to

3.5

0to

8.5V


25°C 3.2 3.8 8 8.5

VVOH High-level output voltageVID = 100 mV,RL = 10 kΩ –55°C 3 3.8 7.8 8.5 VOH g p gRL = 10 kΩ

125°C 3 3.8 7.8 8.4

V L l l lV 100 mV

25°C 0 50 0 50


–55°C 0 50 0 50 mVOL p gIOL = 0

125°C 0 50 0 50


25°C 5 23 10 36



–55°C 3.5 35 7 50 V/mVVD voltage amplification See Note 6125°C 3.5 16 7 27


25°C 65 80 65 85



25°C 65 95 65 95


VDD = 5 V to 10 VVO = 1.4 V



I S lVO = VDD/2, 25°C 675 1600 950 2000



µ







HIGH-BIAS MODE

operating characteristics at specified free-air temperature, V DD = 5 V

PARAMETER TEST CONDITIONS TA

TLC271C, TLC271AC,TLC271BC UNITA

MIN TYP MAXUNIT

SR Sl i iR 10 kΩ

V 1 V

25°C 3.6

V/SR Sl i iR 10 kΩ

VI(PP) = 1 V 0°C 4

V/SR Slew rate at unity gainRL = 10 kΩ,CL = 20 pF

I(PP)70°C 3

V/µsSR Slew rate at unity gain CL = 20 pF,See Figure 98

V 2 5 V

25°C 2.9V/µs

See Figure 98VI(PP) = 2.5 V 0°C 3.1I(PP)

70°C 2.5

Vn Equivalent input noise voltagef = 1 kHz, RS = 20 Ω,

25°C 25 nV/√HzVn Equivalent input noise voltagef 1 kHz,See Figure 99

RS 20 Ω,25°C 25 nV/√Hz

B M i i b d id hV V C 20 pF

25°C 320

kHBOM Maximum output-swing bandwidthVO = VOH ,RL = 10 kΩ,

CL = 20 pF,See Figure 98

0°C 340 kHzOM p gRL = 10 kΩ, See Figure 98

70°C 260

B U i i b d id hV 10 mV C 20 pF

25°C 1.7

MHB1 Unity-gain bandwidthVI = 10 mV,See Figure 100

CL = 20 pF,0°C 2 MHz1 y g

See Figure 10070°C 1.3

Ph iV 10 mV f B

25°C 46°

φm Phase marginVI = 10 mV,CL = 20 pF,

f = B1,See Figure 100

0°C 47°φm gCL = 20 pF, See Figure 100

70°C 44°




MIN TYP MAX

SR Sl i iR 10 kΩ

V 1 V

25°C 5.3

V/SR Sl i iR 10 kΩ

VI(PP) = 1 V 0°C 5.9


I(PP)70°C 4.3


V 5 5 V

25°C 4.6V/µs


70°C 3.8



RS 20 Ω,25°C 25 nV/√Hz


25°C 200

kHBOM Maximum output-swing bandwidthVO = VOH,RL = 10 kΩ,



70°C 140


25°C 2.2


CL = 20 pF,0°C 2.5 MHz1 y g


Ph if = B1 VI = 10 mV

25°C 49°

φm Phase marginf = B1,CL = 20 pF,

VI = 10 mV,See Figure 100 0°C 50°φm g CL = 20 pF, See Figure 100

70°C 46°




HIGH-BIAS MODE



TLC271I, TLC271AI,TLC271BI UNITA

MIN TYP MAX

SR Sl i iR 10 kΩ

V 1 V

25°C 3.6

V/SR Sl i iR 10 kΩ

VI(PP) = 1 V –40°C 4.5


I(PP)85°C 2.8


V 2 5 V

25°C 2.9V/µs

See Figure 98VI(PP) = 2.5 V –40°C 3.5I(PP)

85°C 2.3



RS 20 Ω,25°C 25 nV/√Hz


25°C 320

kHBOM Maximum output-swing bandwidthVO = VOH,RL = 10 kΩ


–40°C 380 kHzOM p gRL = 10 kΩ, See Figure 98

85°C 250


25°C 1.7


CL = 20 pF,–40°C 2.6 MHz1 y g


Ph iV 10 mV f B

25°C 46°

φm Phase marginVI = 10 mV,CL = 20 pF


–40°C 49°φm gCL = 20 pF, See Figure 100

85°C 43°




MIN TYP MAX

SR Sl i iR 10 kΩ

V 1 V

25°C 5.3

V/SR Sl i iR 10 kΩ

VI(PP) = 1 V –40°C 6.8


I(PP)85°C 4


V 5 5 V

25°C 4.6V/µs


85°C 3.5



RS 20 Ω,25°C 25 nV/√Hz


25°C 200




85°C 130


25°C 2.2


CL = 20 pF,–40°C 3.1 MHz1 y g


Ph iV 10 mV f B

25°C 49°


f= B1,See Figure 100


85°C 46°





HIGH-BIAS MODE


PARAMETER TEST CONDITIONS TATLC271M

UNITPARAMETER TEST CONDITIONS TA MIN TYP MAXUNIT

SR Sl i iR 10 kΩ

V 1 V

25°C 3.6

SR Sl i iR 10 kΩ

VI(PP) = 1 V –55°C 4.7

SR Slew rate at unity gainRL = 10 kΩ,CL = 20 pF

I(PP)125°C 2.3


V 2 5 V

25°C 2.9V/µs


125°C 2



RS 20 Ω,25°C 25 nV/√Hz


25°C 320




125°C 230


25°C 1.7


CL = 20 pF,–55°C 2.9 MHz1 y g


Ph iVI = 10 mV f = B1

25°C 46°

φm Phase marginVI = 10 mV,CL = 20 pF,

f = B1,See Figure 100 –55°C 49°φm g CL = 20 pF, See Figure 100

125°C 41°




SR Sl i iR 10 kΩ

V 1 V

25°C 5.3

V/SR Sl i iR 10 kΩ

VI(PP) = 1 V –55°C 7.1


I(PP)125°C 3.1


V 5 5 V

25°C 4.6V/µs


125°C 2.7



RS 20 Ω,25°C 25 nV/√Hz


25°C 200




125°C 110


25°C 2.2


CL = 20 pF,–55°C 3.4 MHz1 y g


Ph if = B1 VI = 10 mV

25°C 49°

φm Phase marginf = B1,CL = 20 pF,

VI = 10 mV,See Figure 100 –55°C 52°φm g CL = 20 pF, See Figure 100

125°C 44°




TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)

Table of Graphs

FIGURE

VIO Input offset voltage Distribution 2, 3

αVIO Temperature coefficient Distribution 4, 5

V Hi h l l lvs High-level output current 6, 7

VOH High-level output voltagevs High level output currentvs Supply voltage

6, 78OH g p g pp y g

vs Free-air temperature 9

V L l l l

vs Common-mode input voltage 10, 11

VOL Low-level output voltage

vs Common-mode input voltagevs Differential input voltage

10, 1112VOL Low-level output voltage vs Differential input voltage

vs Free-air temperature1213p

vs Low-level output current 14, 15

A L i l diff i l l lifi ivs Supply voltage 16

AVD Large-signal differential voltage amplificationvs Supply voltagevs Free-air temperature

1617VD g g g p p

vs Frequency 28, 29

IIB Input bias current vs Free-air temperature 18

IIO Input offset current vs Free-air temperature 18

VIC Common-mode input voltage vs Supply voltage 19

IDD Supply currentvs Supply voltage 20

IDD Supply currentvs Supply voltagevs Free-air temperature

2021

SR Slew ratevs Supply voltage 22

SR Slew ratevs Supply voltagevs Free-air temperature

2223

Bias-select current vs Supply voltage 24

VO(PP) Maximum peak-to-peak output voltage vs Frequency 25

B1 Unity-gain bandwidthvs Free-air temperature 26

B1 Unity-gain bandwidthvs Free air temperaturevs Supply voltage

2627

AVD Large-signal differential voltage amplification vs Frequency 28, 29

Ph ivs Supply voltage 30

φm Phase marginvs Supply voltagevs Free-air temperature

3031φm g p

vs Load capacitance 32

Vn Equivalent input noise voltage vs Frequency 33

Phase shift vs Frequency 28, 29





TYPICAL CHARACTERISTICS (HIGH-BIAS MODE) †

Figure 2

Figure 4

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

– 50

Per

cent

age

of U

nits

– %

VIO – Input Offset Voltage – mV5

60

– 4 – 3 – 2 – 1 0 1 2 3 4

10

20

30

40

50

DISTRIBUTION OF TLC271INPUT OFFSET VOLTAGE

TA = 25°CP Package

ÎÎÎÎÎÎÎÎÎÎÎÎ753 Amplifiers Tested From 6 Wafer LotsVDD = 5 V

50

40

30

20

10

86420– 2– 4– 6– 8

60

10αVIO – Temperature Coefficient – µV/°C

Per

cent

age

of U

nits

– %

0– 10


TEMPERATURE COEFFICIENT

P PackageTA = 25°C to 125°CVDD = 5 VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

324 Amplifiers Tested From 8 Wafer Lots

Outliers:ÎÎÎÎÎÎÎÎÎÎ

(1) 20.5 µV/°C

Figure 3

50

40

30

20

10

43210– 1– 2– 3– 4

60

5P

erce

ntag

e of

Uni

ts –

%0– 5


VIO – Input Offset Voltage – mV

P Package

TA = 25°CVDD = 10 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


Figure 5

– 100

Per

cent

age

of U

nits

– %

10

60

– 8 – 6 – 4 – 2 0 2 4 6 8

10

20

30

40

50



TA = 25°C to 125°C

Outliers:P Package

ÎÎÎÎÎÎÎÎÎÎ

(1) 21.2 µV/°C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

324 Amplifiers Tested From 8 Wafer lotsVDD = 10 V

αVIO – Temperature Coefficient – µV/°C





Figure 6

Figure 8


00

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

IOH – High-Level Output Current – mA– 10

5

– 2 – 4 – 6 – 8

1

2

3

4TA = 25°CVID = 100 mV

VDD = 5 V

VDD = 4 V

VDD = 3 V

HIGH-LEVEL OUTPUT VOLTAGEvs

HIGH-LEVEL OUTPUT CURRENT

ÁÁÁÁÁÁ

V OH

0VDD – Supply Voltage – V

162 4 6 8 10 12 14

14

12

10

8

6

4

2

16

0

VID = 100 mVRL = 10 kΩTA = 25°C


SUPPLY VOLTAGE

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁV O

H

Figure 7

00

IOH – High-Level Output Current – mA

– 40

16

– 10 – 20 – 30

2

4

6

8

10

12

14

VDD = 16 V


VDD = 10 V

VID = 100 mVTA = 25°C



VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁÁÁÁ

V OH

– 5 – 15 – 25 – 35

Figure 9

– 1.7

– 1.8

– 1.9

– 2

– 2.1

– 2.2

– 2.3

1007550200– 25– 50

VDD – 1.6

125TA – Free-Air Temperature – °C

– 2.4– 75

IOH = –5 mAVID = 100 mA

VDD = 5 V

VDD = 10 V


FREE-AIR TEMPERATURE

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁV O

H






Figure 10

Figure 12


0300

VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

VIC – Common-Mode Input Voltage – V4

700

1 2 3

400

500

600

TA = 25°CIOL = 5 mAVDD = 5 V

VID = –1 V

LOW-LEVEL OUTPUT VOLTAGEvs

COMMON-MODE INPUT VOLTAGE

650

550

450

350ÁÁÁÁ

VO

L


VID = –100 mV

0VID – Differential Input Voltage – V

– 10– 2 – 4 – 6 – 8

800

700

600

500

400

300

200

100

0

IOL = 5 mAVIC = VID/2TA = 25°C

VDD = 10 V


DIFFERENTIAL INPUT VOLTAGE

VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁÁÁ

VO

L

– 1 – 3 – 5 – 7 – 9

ÎÎÎÎÎVDD = 5 V

Figure 11

2500

VIC – Common-Mode Input Voltage – V

300

350

400

450

500

2 4 6 8 10

VDD = 10 VIOL = 5 mATA = 25°C

VID = –1 V

VID = –2.5 V

VID = –100 mV



1 3 5 7 9V

OL

– Lo

w-L

evel

Out

put V

olta

ge –

mV

ÁÁÁÁ

VO

L

Figure 13

– 750

TA – Free-Air Temperature – °C125

900

– 50 – 25 0 25 50 75 100

100

200

300

400

500

600

700

800VIC = 0.5 VVID = –1 VIOL = 5 mA



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁÁÁ

VO

L

ÎÎÎÎÎÎÎÎ

VDD = 10 V


VDD = 5 V





Figure 14

Figure 16



LOW-LEVEL OUTPUT CURRENT

0IOL – Low-Level Output Current – mA

1

80

1 2 3 4 5 6 7

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9VID = –1 VVIC = 0.5 VTA = 25°C

VDD = 5 V

VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁÁÁÁÁÁ

VO

L

ÎÎÎÎÎÎÎÎ

VDD = 3 V

ÎÎÎÎVDD = 4 V

0

AV

D –

Diff

eren

tial V

olta

ge A

mpl

ifica

tion

– V

/mV

60

160

2 4 6 8 10 12 14

10

20

30

40

50

VDD – Supply Voltage – V

85°C

125°C

TA = – 55°CÎÎÎÎÎÎÎÎRL = 10 kΩ

LARGE-SIGNALDIFFERENTIAL VOLTAGE AMPLIFICATION

vsSUPPLY VOLTAGE

ÁÁÁÁA

VD

ÎÎÎÎÎÎ

0°C

ÎÎÎÎÎÎ

25°C

Figure 15


3

300

5 10 15 20 25

0.5

1

1.5

2

2.5 TA = 25°CVIC = 0.5 VVID = –1 V

VDD = 10 V

VDD = 16 V



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁÁÁÁÁÁ

V OL

Figure 17

– 75TA – Free-Air Temperature – °C

50

1250

– 50 – 25 0 25 50 75 100

5

10

15

20

25

30

35

40

45

VDD = 5 V

VDD = 10 V


vsFREE-AIR TEMPERATURE

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁ

AV

DVo

ltage

Am

plifi

catio

n –

V/m

V

ÎÎÎÎRL = 10 kΩ






Figure 18

Figure 20

NOTE A: The typical values of input bias current and input offset current below 5 pA were determined mathematically.


0.1125

10000

45 65 85 105

1

10

100

1000


INPUT BIAS CURRENT AND INPUT OFFSETCURRENT


ÁÁÁÁÁÁÁÁÁÁÁÁ

VDD = 10 VVIC = 5 VSee Note A

ÎÎÎÎÎÎ

IIB

ÎÎÎÎÎÎ

IIO

IIB a

nd II

O –

Inpu

t Bia

s an

dIBI

I IO

Inpu

t Offs

et C

urre

nts

– nA

0

IDD

– S

uppl

y C

urre

nt –

mA


2.5

160

2 4 6 8 10 12 14

0.5

1

1.5

2 TA =–55°C

25°C

70°C

125°C

SUPPLY CURRENTvs

SUPPLY VOLTAGE

ÁÁÁÁÁÁ

DD

I

ÎÎÎÎÎÎ

0°C

ÎÎÎÎÎÎÎÎ

VO = VDD/2No Load

Figure 19


16

160

2 4 6 8 10 12 14

2

4

6

8

10

12

14TA = 25°C

COMMON-MODE INPUT VOLTAGE(POSITIVE LIMIT)

vsSUPPLY VOLTAGE

–

Com

mon

-Mod

e In

put V

olta

ge –

VV

IC

Figure 21

– 75TA – Free-Air Temperature – °C

2

1250

0.5

1

1.5

– 50 – 25 0 25 50 75 100

VDD = 10 V

VDD = 5 V

SUPPLY CURRENTvs


IDD

– S

uppl

y C

urre

nt –

mA

ÁÁÁÁÁÁ

DD

I

ÎÎÎÎÎÎÎÎ

VO = VDD/2No Load





Figure 22

Figure 24


TA = 25°CSee Figure 98

AV = 1VI(PP) = 1 VRL = 10 kΩCL = 20 pF

8

7

6

5

4

3

2

1

14121086420


SR

– S

lew

Rat

e –

V/ u

s

0

SLEW RATEvs

SUPPLY VOLTAGE

sµ

VI(SEL) = 0TA = 25°C

– 2.4

– 1.8

– 1.2

– 0.6

14121086420

16

– 3

VDD – Supply Voltage – V0

BIAS-SELECT CURRENTvs

SUPPLY VOLTAGE

– 2.7

– 2.1

– 1.5

– 0.9

– 0.3

Bia

s-S

elec

t Cur

rent

– u

aA

µ

Figure 23

VDD = 10 V

VI(PP) = 1 VVDD = 5 V

RL = 10 kΩAV = 1

See Figure 99CL = 20 pF

–750

1

2

3

4

5

6

7

8

1007550250–25–50 125TA – Free-Air Temperature – °C

SLEW RATEvs


SR

– S

lew

Rat

e –

V/ u

s sµ

ÎÎÎÎÎÎÎÎ

VDD = 10 VÎÎÎÎÎÎÎÎÎÎ

VI(PP) = 5.5 V


VI(PP) = 1 V

ÎÎÎÎÎÎÎÎ

VDD = 5 V


VI(PP) = 2.5 V

Figure 25

ÎÎÎÎVDD = 5 V

1000100

9

8

7

6

5

4

3

2

1

010000

10

f – Frequency – kHz10

MAXIMUM PEAK-TO-PEAK OUTPUTVOLTAGE

vsFREQUENCY


TA = 125°CÎÎÎÎÎÎÎÎÎÎ

TA = 25°CÎÎÎÎÎÎÎÎÎÎ

TA = 55°C

ÎÎÎÎÎÎÎÎ

VDD = 10 V

ÎÎÎÎÎÎÎÎ

RL = 10 kΩÎÎÎÎÎÎÎÎÎÎ

See Figure 98– M

axim

um P

eak-

to-P

eak

Out

put V

olta

ge –

VV O

(PP

)






Figure 26

Phase Shift

AVD

VDD = 5 VRL = 10 kΩTA = 25°C

Pha

se S

hift

106

105

104

103

102

101

1

1 M100 k10 k1 k1000.1

10 Mf – Frequency – Hz

10

LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE SHIFT

vsFREQUENCY

107

150°

120°

90°

60°

30°

0°

180°

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n

Figure 28


See Figure 100CL = 20 pFVI = 10 mVVDD = 5 V

2.5

2

1.5

1007550250– 25– 501

125

3

TA – Free-Air Temperature – °C

B1

– U

nity

-Gai

n B

andw

idth

– M

Hz

– 75

UNITY-GAIN BANDWIDTHvs


B1

Figure 27

VI = 10 mVCL = 20 pFTA = 25°CSee Figure 100

2

1.5

14121086421

16

2.5



SUPPLY VOLTAGE

B1

– U

nity

-Gai

n B

andw

idth

– M

Hz

B1





Phase Shift

AVD

TA = 25°CRL = 10 kΩVDD = 10 V

Pha

se S

hift

150°

120°

90°

60°

30°

0°

180°

106

105

104

103

102

101

1

1 M100 k10 k1 k1000.1


10

LARGE-SCALE DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE SHIFT

vsFREQUENCY

107A

VD

– L

arge

-Sig

nal D

iffer

entia

l

ÁÁÁÁA

VD

Volta

ge A

mpl

ifica

tion

Figure 29

Figure 30


0

m –

Pha

se M

argi

n


53°

162 4 6 8 10 12 14

47°

49°

51°

CL = 20 pFTA = 25°C

VI = 10 mV

See Figure 100

PHASE MARGINvs

SUPPLY VOLTAGE

46°

45°

48°

50°

52°

ÁÁÁÁ

mφ

Figure 31

– 75

50°

12540°

– 50 – 25 0 25 50 75 100

42°

44°

46°

48°

VDD = 5 V

CL = 20 pFVI = 10 mV

See Figure 100


PHASE MARGINvs


m –

Pha

se M

argi

n

ÁÁ

mφ






Figure 32


0CL – Capacitive Load – pF

50°

10025°

20 40 60 80

30°

35°

40°

45°See Figure 100

VI = 10 mVTA = 25°C

VDD = 5 mV

PHASE MARGINvs

CAPACITIVE LOAD

m –

Pha

se M

argi

n

ÁÁÁÁ

mφ

Figure 33

VN

– E

quiv

alen

t Inp

ut N

oise

Vol

tage

– n

V/H

z1

f – Frequency – Hz

400

10000

100

200

300

10 100

EQUIVALENT NOISE VOLTAGEvs

FREQUENCY

Vn

ÁÁÁÁÁÁÁÁ

nV/

Hz

350

250

150

50

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VDD = 5 V

TA = 25°CRS = 20 Ω

See Figure 99




MEDIUM-BIAS MODE


PARAMETER TEST CONDITIONS †TLC271C, TLC271AC, TLC271BC

UNITPARAMETER TEST CONDITIONS TA† VDD = 5 V VDD = 10 V UNITAMIN TYP MAX MIN TYP MAX

V I ff l

TLC271CV 1 4 V

25°C 1.1 10 1.1 10

VV I ff l

TLC271CVO = 1.4 V, Full range 12 12


VO = 1.4 V,VIC = 0 25°C 0.9 5 0.9 5

mVVIO Input offset voltage TLC271AC ICRS = 50 Ω,R 100 kΩ


TLC271BCRI = 100 kΩ 25°C 0.25 2 0.26 2

TLC271BCFull range 3 3

αVIOAverage temperature coefficient of input offset voltage

25°C to70°C 1.7 2.1 µV/°C


pAIIO Input offset current (see Note 4) O DD ,VIC = VDD/2 70°C 7 300 7 300

pA


pAIIB Input bias current (see Note 4) O DD ,VIC = VDD/2 70°C 40 600 50 600

pA


25°C–0.2

to4

–0.3to

4.2

–0.2to9

–0.3to

9.2V

VICRp

voltage range (see Note 5)

Full range–0.2

to3.5

–0.2to

8.5V

V Hi h l l lVID = 100 mV

25°C 3.2 3.9 8 8.7

VVOH High-level output voltageVID = 100 mV,RL = 100 kΩ

0°C 3 3.9 7.8 8.7 VOH g p gRL = 100 kΩ

70°C 3 4 7.8 8.7

V L l l lVID = 100 mV

25°C 0 50 0 50


0°C 0 50 0 50 mVOL p gIOL = 0

70°C 0 50 0 50

ALarge signal differential RL = 100 kΩ

25°C 25 170 25 275



0°C 15 200 15 320 V/mVVD voltage amplification See Note 670°C 15 140 15 230


25°C 65 91 65 94


kSupply voltage rejection ratio VDD = 5 V to 10 V

25°C 70 93 70 93


VDD = 5 V to 10 VVO = 1.4 V


II(SEL) Input current (BIAS SELECT) VI(SEL) = VDD/2 25°C –130 –160 nA

I S lVO = VDD/2, 25°C 105 280 143 300

AIDD Supply currentVO VDD/2,VIC = VDD/2,N l d


µ







MEDIUM-BIAS MODE


PARAMETER TEST CONDITIONS †TLC271I, TLC271AI, TLC271BI

UNITPARAMETER TEST CONDITIONS TA† VDD = 5 V VDD = 10 V UNITAMIN TYP MAX MIN TYP MAX

V I ff l

TLC271IV 1 4 V

25°C 1.1 10 1.1 10

VV I ff l

TLC271IVO = 1.4 V, Full range 13 13


VO = 1.4 V,VIC = 0 V, 25°C 0.9 5 0.9 5

mVVIO Input offset voltage TLC271AI IC ,RS = 50 Ω,R 100 kΩ

Full range 7 7mV

TLC271BIRL = 100 kΩ 25°C 0.25 2 0.26 2

TLC271BIFull range 3.5 3.5


25°C to85°C 1.7 2.1 µV/°C


pAIIO Input offset current (see Note 4) O DD ,VIC = VDD/2 85°C 24 1000 26 1000

pA


pAIIB Input bias current (see Note 4) O DD ,VIC = VDD/2 85°C 200 2000 220 2000

pA


25°C–0.2

to4

–0.3to

4.2

–0.2to9

–0.3to

9.2V

VICRp


Full range–0.2

to3.5

–0.2to

8.5V


25°C 3.2 3.9 8 8.7


–40°C 3 3.9 7.8 8.7 VOH g p gRL = 100 kΩ

85°C 3 4 7.8 8.7


25°C 0 50 0 50


–40°C 0 50 0 50 mVOL p gIOL = 0

85°C 0 50 0 50


25°C 25 170 25 275



–40°C 15 270 15 390 V/mVVD voltage amplification See Note 685°C 15 130 15 220


25°C 65 91 65 94



25°C 70 93 70 93


VDD = 5 V to 10 VVO = 1.4 V



I S lVO = VDD/2, 25°C 105 280 143 300


–40°C 158 400 225 450 µADD pp y IC DDNo load 85°C 80 200 103 260

µ






MEDIUM-BIAS MODE


PARAMETERTEST †

TLC271M

UNITPARAMETERTEST

CONDITIONSTA† VDD = 5 V VDD = 10 V UNITCONDITIONS A

MIN TYP MAX MIN TYP MAX

VIO Input offset voltage

VO = 1.4 V,VIC = 0 V,

25°C 1.1 10 1.1 10 mV

VIO Input offset voltageRS = 50 Ω,RL = 100 kΩ Full range 12 12


25°C to 125°C 1.7 2.1 µV/°C


IIO Input offset current (see Note 4) O DD ,VIC = VDD/2 125°C 1.4 15 1.8 15 nA


IIB Input bias current (see Note 4) O DD ,VIC = VDD/2 125°C 9 35 10 35 nA


25°C0to4

–0.3to

4.2

0to9

–0.3to

9.2V

VICRp


Full range0to

3.5

0to

8.5V


25°C 3.2 3.9 8 8.7


–55°C 3 3.9 7.8 8.6 VOH g p gRL = 100 kΩ

125°C 3 4 7.8 8.6


25°C 0 50 0 50


–55°C 0 50 0 50 mVOL p gIOL = 0

125°C 0 50 0 50


25°C 25 170 25 275


RL = 10 kΩSee Note 6



25°C 65 91 65 94



25°C 70 93 70 93


VDD = 5 V to 10 VVO = 1.4 V



I S lVO = VDD/2, 25°C 105 280 143 300


–55°C 170 440 245 500 µADD pp y IC DDNo load 125°C 70 180 90 240

µ







MEDIUM-BIAS MODE




MIN TYP MAXUNIT

SR Sl i iR 100 kΩ

V 1 V

25°C 0.43

V/SR Sl i iR 100 kΩ

VI(PP) = 1 V 0°C 0.46


I(PP)70°C 0.36


V 2 5 V

25°C 0.40V/µs


70°C 0.34

Vn Equivalent input noise voltagef = 1 kHz,See Figure 99

RS = 20 Ω,25°C 32 nV/√Hz


25°C 55




70°C 50


25°C 525

kHB1 Unity-gain bandwidthVI = 10 mV,See Figure 100

CL = 20 pF,0°C 600 kHz1 y g

See Figure 10070°C 400

Ph iV 10 mV f B

25°C 40°




70°C 39°




MIN TYP MAXUNIT

SR Sl i iR 100 kΩ

V 1 V

25°C 0.62


VI(PP) = 1 V 0°C 0.67


I(PP)70°C 0.51


V 5 5 V

25°C 0.56V/µs


70°C 0.46


RS = 20 Ω,25°C 32 nV/√Hz


25°C 35




70°C 30


25°C 635


CL = 20 pF,0°C 710 kHz1 y g


Ph iV 10 mV f B

25°C 43°




70°C 42°




MEDIUM-BIAS MODE




MIN TYP MAXUNIT

SR Sl i iR 100 kΩ

V 1 V

25°C 0.43


VI(PP) = 1 V –40°C 0.51


I(PP)85°C 0.35


V 2 5 V

25°C 0.40V/µs


85°C 0.32


RS = 20 Ω,25°C 32 nV/√Hz


25°C 55




85°C 45


25°C 525


CL = 20 pF,–40°C 770 MHz1 y g


Ph iV 10 mV f B

25°C 40°




85°C 38°




MIN TYP MAXUNIT

SR Sl i iR 100 kΩ

V 1 V

25°C 0.62


VI(PP) = 1 V –40°C 0.77


I(PP)85°C 0.47


V 5 5 V

25°C 0.56V/µs


85°C 0.44


RS = 20 Ω,25°C 32 nV/√Hz

B M i i b d id hV V 3 C 20 pF

25°C 35

kHBOM Maximum output-swing bandwidthVO = VOH,3RL = 100 kΩ



85°C 25


25°C 635


CL = 20 pF,–40°C 880 kHz1 y g


Ph iV 10 mV f B

25°C 43°




85°C 41°





MEDIUM-BIAS MODE




SR Sl i iR 100 kΩ

V 1 V

25°C 0.43


VI(PP) = 1 V –55°C 0.54


I(PP)125°C 0.29


V 2 5 V

25°C 0.40V/µs


125°C 0.28


RS = 20 Ω,25°C 32 nV/√Hz


25°C 55




125°C 40


25°C 525


CL = 20 pF,–55°C 850 kHz1 y g


Ph iV 10 mV f B

25°C 40°




125°C 36°




SR Sl i iR 100 kΩ

V 1 V

25°C 0.62


VI(PP) = 1 V –55°C 0.81


I(PP)125°C 0.38


V 5 5 V

25°C 0.56V/µs


125°C 0.35


RS = 20 Ω,25°C 32 nV/√Hz


25°C 35




125°C 20


25°C 635


CL = 20 pF,–55°C 960 kHz1 y g


Ph iV 10 mV f B

25°C 43°




125°C 39°




TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)

Table of Graphs

FIGURE





38, 3940OH g p g pp y g


V L l l l









4849VD g g g p p

vs Frequency 60, 61



VI Maximum Input voltage vs Supply voltage 51



5253



5455





5859



6263φm g p








TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE) †

Figure 34

Figure 36


–50

Per

cent

age

of U

nits

– %

VIO – Input Offset Voltage – mV5–4 –3 –2 –1 0 1 2 3 4

10

20

30

40

50

60



ÎÎÎÎÎÎÎÎ

VDD = 5 V

ÎÎÎÎÎÎÎÎ

TA = 25°CÎÎÎÎÎÎÎÎN Package

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ



TEMPERATURE COEFFICIENT60

50

40

30

20

10

0– 10 – 8 10


Per

cent

age

of U

nits

– %

– 6 – 4 – 2 0 2 4 6 8


224 Amplifiers Tested From 6 Water Lots

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VDD = 5 VTA = 25°C to 125°CP PackageOutliers:(1) 33.0 µV/°C

Figure 35

60

50

40

30

20

10

43210–1–2–3–4 5VIO – Input Offset Voltage – mV

Per

cent

age

of U

nits

– %

0–5


ÎÎÎÎÎÎÎÎÎÎÎÎ612 Amplifiers Tested From 6 Wafer LotsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ


VDD = 5 VÎÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎN Package

Figure 37



20

60

50

40

30

10

0– 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10


Per

cent

age

of U

nits

– %

ÎÎÎÎÎÎÎÎÎÎÎ224 Amplifiers Tested From 6 Water LotsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VDD = 10 VTA = 25°C to 125°CP PackageOutliers:(1) 34.6 µV/°C





Figure 38

Figure 40


00

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V


5

– 2 – 4 – 6 – 8

1

2

3

4

TA = 25°CVID = 100 mV

VDD = 5 V

VDD = 4 V

VDD = 3 V



ÁÁÁÁ

V OH


162 4 6 8 10 12 14

14

12

10

8

6

4

2

16

0

VID = 100 mVRL = 10 kΩTA = 25°C


SUPPLY VOLTAGE

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁ

V OH

Figure 39

00


16

– 10 – 20 – 30

2

4

6

8

10

12

14

VDD = 16 V

VDD = 10 V

VID = 100 mVTA = 25°C



– 35– 25– 15– 5

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁ

V OH

Figure 41

– 1.7

– 1.8

– 1.9

– 2

– 2.1

– 2.2

– 2.3

1007550200– 25– 50

VDD – 1.6


– 2.4– 75

IOH = –5 mAVID = 100 mA

VDD = 5 V

VDD = 10 V



VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁ

V OH






Figure 42

Figure 44


0300


700

1 2 3

400

500

600




650

550

450

350VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁ

VO

L ÎÎÎÎÎÎÎÎ

VID = –1 V


VID = –100 mV

0VID – Differential Input Voltage – V

– 10– 2 – 4 – 6 – 8

800

700

600

500

400

300

200

100

0

VDD = 5 V

VDD = 10 V



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁV

OL

– 1 – 3 – 5 – 7 – 9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IOL = 5 mAVIC = |VID/2|TA = 25°C

Figure 43

2500


300

350

400

450

500

2 4 6 8 10

VDD = 10 VIOL= 5 mA

TA = 25°C

VID = –1 V

VID = –2.5 V

VID = –100 mV



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁ

VO

L97531

Figure 45

– 750


900

– 50 – 25 0 25 50 75 100

100

200

300

400

500

600

700

800VIC = 0.5 VVID = –1 VIOL = 5 mA

VDD = 5 V

VDD = 10 V



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁV

OL





Figure 46

Figure 48



1

80

1 2 3 4 5 6 7

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VID = –1 VVIC = 0.5 VTA = 25°C

VDD = 3 V

VDD = 4 V

VDD = 5 V



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁÁÁÁ

V OL


500

160

2 4 6 8 10 12 14

50

100

150

200

250

300

350

400

450TA = –55°C

–40°C

0°C

25°C

70°C

85°C


vsSUPPLY VOLTAGE


TA = 125°C

ÎÎÎÎÎÎÎÎ

RL = 100 kΩ

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n –

V/m

V

Figure 47


3

300

5 10 15 20 25

0.5

1

1.5

2

2.5 TA = 25°CVIC = 0.5 VVID = –1 V



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁÁÁÁ

V OL

ÎÎÎÎÎÎÎÎ

VDD = 16 V


VDD = 10 V

Figure 49



450

400

350

300

250

200

150

100

50

1007550250–25–500

125

500

TA – Free-Air Temperature – °C–75


VDD = 5 V

ÎÎÎÎÎÎÎÎ

VDD = 10 V


RL = 100 kΩ

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n –

V/m

V






Figure 50

Figure 52



0.1125

10000

45 65 85 105

1

10

100

1000

25




11595755535



ÎÎIIB

ÎÎÎÎÎÎ

IIO

IIB a

nd II

O –

Inpu

t Bia

s an

dIBI

I IO

Inpu

t Offs

et C

urre

nts

– pA

IDD

– S

uppl

y C

urre

nt –

mA


VO = VDD/2No Load TA = –55°C

0°C

25°C

70°C

125°C

0

400

160

2 4 6 8 10 12 14

50

100

150

200

250

300

350

–40°C

SUPPLY CURRENTvs

SUPPLY VOLTAGE

ÁÁÁÁ

I DD

Figure 51

MAXIMUM INPUT VOLTAGEvs

SUPPLY VOLTAGE

0


16

160

2 4 6 8 10 12 14

2

4

6

8

10

12

14

ÎÎÎÎÎÎÎÎ

TA = 25°C

VI –

Max

imum

Inpu

t Vol

tage

– V

VI

Figure 53

–75TA – Free-Air Temperature – °C

250

1250

–50 –25 0 25 50 75 100

25

50

75

100

125

150

175

200

225

SUPPLY CURRENTvs


IDD

– S

uppl

y C

urre

nt –

mA

ÁÁÁÁ

I DD

ÁÁÁÁÁÁÁÁNo Load

VO = VDD/2


VDD = 10 V

ÎÎÎÎÎÎÎÎ

VDD = 5 V





Figure 54

Figure 56


0

SR

– S

lew

Rat

e –

V/


0.9

160.3

2 4 6 8 10 12 14

0.4

0.5

0.6

0.7

0.8

SLEW RATEvs

SUPPLY VOLTAGE

sµ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CL = 20 pFRL = 100 kΩVI(PP) = 1 VAV = 1

See Figure 99TA = 25°C

0

Bia

s-S

elec

t Cur

rent

– n

A


–300

160

2 4 6 8 10 12 14

–30

–60

–90

–120

–150

–180

–210

–240

–270


SUPPLY VOLTAGE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VI(SEL) = 1/2 VDD

TA = 25°C

Figure 55


0.9

1250.2

–50 –25 0 25 50 75 100

0.3

0.4

0.5

0.6

0.7

0.8

SLEW RATEvs



RL = 10 kΩAV = 1

See Figure 99CL = 20 pF

SR

– S

lew

Rat

e –

V/

sµ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VI(PP) = 5.5 VVDD = 10 V

ÁÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎÎÎ

VDD = 10 VVI(PP) = 1 V


ÎÎÎÎÎÎÎÎÎÎVDD = 5 V

VI(PP) = 2.5 V

ÁÁÁÁÁÁÁÁÎÎÎÎÎÎÎÎ

VI(PP) = 1 VVDD = 5 V

Figure 57

1f – Frequency – kHz

10

10000

1

2

3

4

5

6

7

8

9

10 100

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGEvs

FREQUENCY


RL = 100 kΩSee Figure 99

ÎÎÎÎÎVDD = 10 V


VDD = 5 V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TA = –55°CTA = 25°CTA = 125°C

– M

axim

um P

eak-

to-P

eak

Out

put V

olta

ge –

VV O

(PP

)






Figure 58

Phase Shift

Pha

se S

hift

180°

0°

30°

60°

90°

120°

150°

106

105

104

103

102

101

1

100 K101 k100100.1


1


vsFREQUENCY


VDD = 5 VRL = 100 kΩTA = 25°C

107

ÎÎÎÎÎÎ

AVD

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n

Figure 60


800

700

600

500

400

1007550250–25–50300

125

900


B1

– U

nity

-Gai

n B

andw

idth

– M

Hz

–75



ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁSee Figure 101

CL = 20 pFVI = 10 mVVDD = 5 V

B1

Figure 59



SUPPLY VOLTAGE

750

700

650

600

550

500

450

1412108642400

16

800


VI = 10 mVCL = 20 pFTA = 25°CSee Figure 101

B1

– U

nity

-Gai

n B

andw

idth

– M

Hz

B1





1f – Frequency – Hz

1 M0.1

10 100 1 k 10 k 100 k

1

101

102

103

104

105

106

150°

120°

90°

60°

30°

0°

180°

Pha

se S

hift

ÎÎÎÎAVD

Phase Shift


vsFREQUENCY

107 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TA = 25°CRL = 100 kΩÎÎÎÎÎVDD = 10 V

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n

Figure 61

Figure 62


038°

m –

Pha

se M

argi

n


50°

2 4 6 8 10 12 14

40°

42°

44°

46°

48°See Figure 100TA = 25°CCL = 20 pFVI = 10 mV

PHASE MARGINvs

SUPPLY VOLTAGE

ÁÁÁÁ

mφ

Figure 63

–7535°


45°

–50 –25 0 25 50 75 100

37°

39°

41°

43°

VDD = 5 VVI = 10 mVCL = 20 pFSee Figure 100

PHASE MARGINvs


m –

Pha

se M

argi

n

ÁÁ

mφ






Figure 64


028°

CL – Capacitive Load – pF100

44°

20 40 60 80

30°

32°

34°

36°

38°

40°

42°VDD = 5 VVI = 10 mVTA = 25°CSee Figure 100

PHASE MARGINvs

CAPACITIVE LOAD

m –

Pha

se M

argi

n

ÁÁÁÁ

mφ

Figure 65

10

Vn

– E

quiv

alen

t Inp

ut N

oise

Vol

tage

– n

V/H

z

f – Frequency – Hz1000

300

50

100

150

200

250

10 100

See Figure 99TA = 25°CRS = 20 ΩVDD = 5 V

EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY

Vn

ÁÁÁÁÁÁnV

/H

z




LOW-BIAS MODE


PARAMETERTEST †

TLC271C, TLC271AC, TLC271BC

UNITPARAMETERTEST


V I ff l

TLC271C

V 1 4 V

25°C 1.1 10 1.1 10

VV I ff l

TLC271C



VO = 1.4 V,VIC = 0 V, 25°C 0.9 5 0.9 5

mVVIO Input offset voltage TLC271AC VIC 0 V,RS = 50 Ω,R 1 MΩ


TLC271BCRI = 1 MΩ

25°C 0.24 2 0.26 2TLC271BC

Full range 3 3

αVIOAverage temperature coefficient of in-put offset voltage

25°C to 70°C 1.1 1 µV/°C



pA



pA


25°C–0.2

to4

–0.3to

4.2

–0.2to9

–0.3to

9.2V


Full range–0.2

to3.5

–0.2to

8.5V


25°C 3.2 4.1 8 8.9

VVOH High-level output voltageVID = 100 mV,RL= 1 MΩ 0°C 3 4.1 7.8 8.9 VOH g p gRL= 1 MΩ

70°C 3 4.2 7.8 8.9

V L l l lV 100 mV

25°C 0 50 0 50


0°C 0 50 0 50 mVOL p gIOL = 0

70°C 0 50 0 50

ALarge signal differential R 1 MΩ

25°C 50 520 50 870


RL= 1 MΩ,See Note 6

0°C 50 700 50 1030 V/mVVD voltage amplification See Note 670°C 50 380 50 660


25°C 65 94 65 97



25°C 70 97 70 97


VDD = 5 V to 10 VVO = 1.4 V


II(SEL) Input current (BIAS SELECT) VI(SEL) = VDD 25°C 65 95 nA

I S lVO = VDD/2, 25°C 10 17 14 23



µ







LOW-BIAS MODE


PARAMETERTEST †

TLC271I, TLC271AI, TLC271BI

UNITPARAMETERTEST


V I ff l

TLC271I

V 1 4 V

25°C 1.1 10 1.1 10

VV I ff l

TLC271I



VO = 1.4 V,VIC = 0 V, 25°C 0.9 5 0.9 5

mVVIO Input offset voltage TLC271AI VIC 0 V,RS = 50 Ω,R 1 MΩ

Full range 7 7mV

TLC271BIRL = 1 MΩ

25°C 0.24 2 0.26 2TLC271BI

Full range 3.5 3.5


25°C to85°C 1.1 1 µV/°C



pA



pA


25°C–0.2

to4

–0.3to

4.2

–0.2to9

–0.3to

9.2V


Full range–0.2

to3.5

–0.2to

8.5V


25°C 3 4.1 8 8.9

VVOH High-level output voltageVID = 100 mV,RL= 1 MΩ –40°C 3 4.1 7.8 8.9 VOH g p gRL= 1 MΩ

85°C 3 4.2 7.8 8.9

V L l l lV 100 mV

25°C 0 50 0 50


–40°C 0 50 0 50 mVOL p gIOL = 0

85°C 0 50 0 50


25°C 50 520 50 870


RL= 1 MΩSee Note 6



25°C 65 94 65 97



25°C 70 97 70 97


VDD = 5 V to 10 VVO = 1.4 V



I S lVO = VDD/2, 25°C 10 17 14 23



µ

† Full range is –40 to 85°C.NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.





LOW-BIAS MODE


PARAMETERTEST †

TLC271M

UNITPARAMETERTEST


VIO Input offset voltage

VO = 1.4 V,VIC = 0 V,

25°C 1.1 10 1.1 10

mVVIO Input offset voltageRS = 50 Ω,RL = 1 MΩ Full range 12 12

mV


25°C to125°C 1.4 1.4 µV/°C


IIO Input offset current (see Note 4)VO VDD/2,VIC = VDD/2 125°C 1.4 15 1.8 15 nA


IIB Input bias current (see Note 4)VO VDD/2,VIC = VDD/2 125°C 9 35 10 35 nA


25°C0to4

–0.3to

4.2

0to9

–0.3to

9.2V


Full range0to

3.5

0to

8.5V


25°C 3.2 4.1 8 8.9

VVOH High-level output voltageVID = 100 mV,RL= 1 MΩ –55°C 3 4.1 7.8 8.8 VOH g p gRL= 1 MΩ

125°C 3 4.2 7.8 9

V L l l lV 100 mV

25°C 0 50 0 50


–55°C 0 50 0 50 mVOL p gIOL = 0

125°C 0 50 0 50


25°C 50 520 50 870


RL= 1 MΩ,See Note 6



25°C 65 94 65 97



25°C 70 97 70 97


VDD = 5 V to 10 VVO = 1.4 V



I S lVO = VDD/2, 25°C 10 17 14 23



µ







LOW-BIAS MODE




MIN TYP MAXUNIT

SR Sl i iR 1 MΩ

V 1 V

25°C 0.03

V/SR Sl i iR 1 MΩ

VI(PP) = 1 V 0°C 0.04

V/SR Slew rate at unity gainRL = 1 MΩ,CL = 20 pF

I(PP)70°C 0.03


V 2 5 V

25°C 0.03V/µs


70°C 0.02


RS = 20 Ω,25°C 68 nV/√Hz


25°C 5

kHBOM Maximum output-swing bandwidthVO = VOH,RL = 1 MΩ


0°C 6 kHzOM p gRL = 1 MΩ, See Figure 98

70°C 4.5


25°C 85


CL = 20 pF,0°C 100 kHz1 y g


Ph iV 10 mV f B

25°C 34°




70°C 30°




MIN TYP MAXUNIT

SR Sl i iR 1 MΩ

V 1 V

25°C 0.05

V/SR Sl i iR 1 MΩ

VI(PP) = 1 V 0°C 0.05


I(PP)70°C 0.04


V 5 5 V

25°C 0.04V/µs


70°C 0.04


RS = 20 Ω,25°C 68 nV/√Hz


25°C 1



0°C 1.3 kHzOM p gRL = 1 MΩ, See Figure 98

70°C 0.9

B U i i b d id hVI = 10 mV C 20 pF

25°C 110

kHB1 Unity-gain bandwidthVI = 10 mV,

See Figure 100CL = 20 pF,

0°C 125 kHz1 y gSee Figure 100

70°C 90

Ph iV 10 mV f B

25°C 38°




70°C 34°




LOW-BIAS MODE




MIN TYP MAXUNIT

SR Sl i iR 1 MΩ

V 1 V

25°C 0.03

V/SR Sl i iR 1 MΩ

VI(PP) = 1 V –40°C 0.04


I(PP)85°C 0.03


V 2 5 V

25°C 0.03V/µs


85°C 0.02


RS = 20 Ω,25°C 68 nV/√Hz


25°C 5



–40°C 7 kHzOM p gRL = 1 MΩ, See Figure 98

85°C 4


25°C 85


CL = 20 pF,–40°C 130 MHz1 y g


Ph iV 10 mV f B

25°C 34°




85°C 28°




MIN TYP MAXUNIT

SR Sl i iR 1 MΩ

V 1 V

25°C 0.05

V/SR Sl i iR 1 MΩ

VI(PP) = 1 V –40°C 0.06


I(PP)85°C 0.03


V 5 5 V

25°C 0.04V/µs


85°C 0.03


RS = 20 Ω,25°C 68 nV/√Hz

V V C 20 pF25°C 1

BOM Maximum output-swing bandwidthVO = VOH,RL = 1 MΩ


–40°C 1.4 kHzRL = 1 MΩ, See Figure 98

85°C 0.8

V 10 mV C 20 pF25°C 110

B1 Unity-gain bandwidthVI = 10 mV,See Figure 100

CL = 20 pF,–40°C 155 MHz


V 10 mV l f B25°C 38°

φm Phase marginVI = 10 mV,lCL = 20 pF


–40°C 42°CL = 20 pF, See Figure 100

85°C 32°





LOW-BIAS MODE




SR Sl i iR 1 MΩ

V 1 V

25°C 0.03

V/SR Sl i iR 1 MΩ

VI(PP) = 1 V –55°C 0.04


I(PP)125°C 0.02


V 2 5 V

25°C 0.03V/µs


125°C 0.02


RS = 20 Ω,25°C 68 nV/√Hz


25°C 5



–55°C 8 kHzOM p gRL = 1 MΩ, See Figure 98

125°C 3


25°C 85


CL = 20 pF,–55°C 140 kHz1 y g


Ph iV 10 mV f B

25°C 34°




125°C 25°




SR Sl i iR 1 MΩ

V 1 V

25°C 0.05

V/SR Sl i iR 1 MΩ

VI(PP) = 1 V –55°C 0.06


I(PP)125°C 0.03


V 5 5 V

25°C 0.04V/µs


125°C 0.03


RS = 20 Ω,25°C 68 nV/√Hz


25°C 1



–55°C 1.5 kHzOM p gRL = 1 MΩ, See Figure 98

125°C 0.7


25°C 110


CL = 20 pF,–55°C 165 kHz1 y g


Ph iV 10 mV f B

25°C 38°




125°C 29°




TYPICAL CHARACTERISTICS (LOW-BIAS MODE)

Table of Graphs

FIGURE





70, 7172OH g p g pp y g


V L l l l









8081VD g g g p p

vs Frequency 92, 93



VI Maximum input voltage vs Supply voltage 83



8485



8687





9091



9495φm g p








TYPICAL CHARACTERISTICS (LOW-BIAS MODE) †

Figure 66

Figure 68


–50

Per

cent

age

of U

nits

– %

VIO – Input Offset Voltage – mV5

70

–4 –3 –2 –1 0 1 2 3 4

10

20

30

40

50

60


VDD = 5 VTA = 25°CP Package



60

50

40

30

20

10

86420–2–4–6–8

70

10

Per

cent

age

of U

nits

– %

0–10




(1) 12.1 µV/°C(1) 19.2 µV/°COutliers:P PackageTA = 25°C to 125°CVDD = 5 V356 Amplifiers Tested From 8 Wafer Lots

Figure 67

60

50

40

30

20

10

43210–1–2–3–4

70

5VIO – Input Offset Voltage – mV

Per

cent

age

of U

nits

– %

0–5


P PackageTA = 25°CVDD = 10 V905 Amplifiers Tested From 6 Wafer Lots

Figure 69

–100

Per

cent

age

of U

nits

– %

αVIO – Temperature Coefficient – µV/°C10

70

–8 –6 –4 –2 0 2 4 6 8

10

20

30

40

50

60



356 Amplifiers Tested From 8 Wafer LotsVDD = 10 V

P PackageOutliers:(1) 18.7 µV/°C(1) 11.6 µV/°C

ÎÎÎÎÎÎÎÎÎÎÎÎ

TA = 25°C to 125°C





Figure 70

Figure 72


00

VO

H–

Hig

h-Le

vel O

utpu

t Vol

tage

– V

IOH – High-Level Output Current – mA–10

5

–2 –4 –6 –8

1

2

3

4

VDD = 5 V

VDD = 3 V

VDD = 4 V



ÁÁÁÁÁÁ

V OH

TA = 25°CVID = 100 mV

00


16

2 4 6 8 10 12 14

2

4

6

8

10

12

14VID = 100 mVRL = 1 MΩTA = 25°C


SUPPLY VOLTAGE

VO

H–

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁV O

H

Figure 71

00

IOH – High-Level Output Current – mA–40

16

–10 –20 –30

2

4

6

8

10

12

14 TA = 25°CVID = 100 mV

VDD = 16 V

VDD = 10 V



–35–25–15–5

VO

H–

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁÁÁÁ

V OH

Figure 73

–75–2.4


–1.6

–50 –25 0 25 50 75 100

–2.3

–2.2

–2.1

–2

–1.9

–1.8

–1.7

IOH = –5 mAVID = 100 mV

VDD = 5 V

VDD = 10 V



VO

H–

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁV

OH






Figure 74

Figure 76


0300

VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V


700

1 2 3

400

500

600



650

550

450

350ÁÁÁÁ

VO

L


VID = –1 V


VID = –100 mV



0

VID – Differential Input Voltage – V

–10–2 –4 –6 –8

800

700

600

500

400

300

200

100

0–1 –3 –5 –7 –9

VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁÁÁ

VO

L

IOL = 5 mAVIC = VID/2TA = 25°C

VDD = 10 V

ÎÎÎÎÎÎÎÎÎÎVDD = 5 V

Figure 75

2500


300

350

400

450

500

2 4 6 8 10



1 3 5 7 9V

OL

– Lo

w-L

evel

Out

put V

olta

ge –

mV

ÁÁÁÁ

VO

L

VDD = 10 VIOL = 5 mATA = 25°C

VID = –1 V

VID = –2.5 V

VID = –100 mV

Figure 77

–750


900

–50 –25 0 25 50 75 100

100

200

300

400

500

600

700

800



VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– m

V

ÁÁÁÁÁÁ

VO

L

VIC = 0.5 VVID = –1 VIOL = 5 mA


VDD = 10 V


VDD = 5 V





Figure 78

Figure 80


0

1

80

1 2 3 4 5 6 7

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9VID = –1 VVIC = 0.5 V

TA = 25°C

VDD = 3 V

VDD = 4 V

VDD = 5 V



IOL – Low-Level Output Current – mA

VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– V

ÁÁÁÁ

VO

L


2000

160

2 4 6 8 10 12 14

200

400

600

800

1000

1200

1400

1600

1800TA = –55°C

– 40°C

TA = 0°C

ÎÎÎÎ

25°CÎÎÎÎÎÎ70°C

ÎÎÎÎÎÎ

85°C

125°C


vsSUPPLY VOLTAGE

ÁÁÁÁÁÁ

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n –

V/m

V

ÎÎÎÎÎÎÎÎ

RL = 1 MΩ

Figure 79


3

300

5 10 15 20 25

0.5

1

1.5

2

2.5 TA = 25°CVIC = 0.5 VVID = –1 V

VDD = 10 V

VDD = 16 V

LOW-LEVER OUTPUT VOLTAGEvs


VO

L –

Low

-Lev

el O

utpu

t Vol

tage

– V

ÁÁÁÁÁÁ

V OL

Figure 81

1007550250–25–500


–75

VDD = 5 V

VDD = 10 V

1800

1600

1400

1200

1000

800

600

400

200

2000



ÁÁÁÁÁÁÁÁÁ

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n –

V/m

V

ÎÎÎÎÎÎÎÎ

RL = 1 MΩ






Figure 82

Figure 84



0.1125

10000

45 65 85 105

1

10

100

1000

25






35 55 75 95 115

ÎÎÎÎ

IIB

ÎÎÎÎ

IIO

IIB a

nd II

O –

Inpu

t Bia

s an

dIBI

I IO

Inpu

t Offs

et C

urre

nts

– pA

TA = –55°C

ÎÎÎÎ25°C

70°C

125°C

0

IDD

– S

uppl

y C

urre

nt –

mA


45

160

2 4 6 8 10 12 14

5

10

15

20

25

30

35

40

ÎÎÎ–40°C

0°C

No LoadVO = VDD/2

SUPPLY CURRENTvs

SUPPLY VOLTAGE

ÁÁÁÁ

DD

IA

µ

Figure 83

0


16

160

2 4 6 8 10 12 14

2

4

6

8

10

12

14

MAXIMUM INPUT VOLTAGEvs

SUPPLY VOLTAGE

ÎÎÎÎÎÎÎÎ

TA = 25°C

VI –

Max

imum

Inpu

t Vol

tage

– V

VI

Figure 85

VO = VDD/2No Load

VDD = 10 V

VDD = 5 V


30

1250

–50 –25 0 25 50 75 100

5

10

15

20

25

SUPPLY CURRENTvs


IDD

– S

uppl

y C

urre

nt –

mA

ÁÁÁÁÁÁ

DD

IA

µ





Figure 86

Figure 88


SR

– S

lew

Rat

e –

V/s

CL = 20 pFRL = 1 MΩVI(PP) = 1 VAV = 1

See Figure 98TA= 25°C


0.07

160.00

2 4 6 8 10 12 14

0.01

0.02

0.03

0.04

0.05

0.06

SLEW RATEvs

SUPPLY VOLTAGE

sµ

0

Bia

s-S

elec

t Cur

rent

– n

A


150

160

2 4 6 8 10 12 14

30

60

90

120

TA = 25°C


SUPPLY VOLTAGE

135

105

75

45

15

ÎÎÎÎÎVI(SEL) = VDD

Figure 87

SLEW RATEvs


VI(PP) = 5.5 VVDD = 10 V


VDD = 5 VVI(PP) = 2.5 V



0.07

1250.00

–50 –25 0 25 50 75 100

0.01

0.02

0.03

0.04

0.05

0.06 CL = 20 pFRL = 1 MΩ

See Figure 98AV = 1

SR

– S

lew

Rat

e –

V/s

sµ

Figure 89

0.1f – Frequency – kHz

10

1000

1

2

3

4

5

6

7

8

9

1 10

VDD = 10 V

VDD = 5 V

ÁÁ

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGEvs

FREQUENCY

ÁÁÁÁÁÁÁÁÁÁSee Figure 98

RL = 1 MΩ


TA = 125°CTA = 25°CTA = –55°C

– M

axim

um P

eak-

to-P

eak

Out

put V

olta

ge –

VV O

(PP

)






Figure 90

1f – Frequency – Hz

1 M0.1

10 100 1 k 10 k 100 k

1

101

102

103

104

105

106

150°

120°

90°

60°

30°

0°

180°

Pha

se S

hift

TA = 25°CRL = 1 MΩVDD = 5 V

ÎÎÎÎÎÎ

AVD


vsFREQUENCY

107


Phase Shift

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n

Figure 92




VDD = 5 VVI = 10 mVCL = 20 pFSee Figure 100

–75

B1

– U

nity

-Gai

n B

andw

idth

– k

Hz


150

12530

–50 –25 0 25 50 75 100

50

70

90

110

130

B1

Figure 91


140

1650

2 4 6 8 10 12 14

60

70

80

90

100

110

120

130TA = 25°CCL = 20 pFVI = 10 mV


SUPPLY VOLTAGE

B1

– U

nity

-Gai

n B

andw

idth

– k

Hz

B1


See Figure 100






vsFREQUENCY

VDD = 10 VRL = 1 MΩTA = 25°C

Pha

se S

hift

180°

0°

30°

60°

90°

120°

150°

106

104

103

102

101

1

100 k10 k1 k100100.1


1

105

107

ÎÎÎÎAVD


Phase Shift

AV

D –

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁÁÁ

AV

DVo

ltage

Am

plifi

catio

n

Figure 93

Figure 94


PHASE MARGINvs

SUPPLY VOLTAGE

0

m –

Pha

se M

argi

n


42°

1630°

2 4 6 8 10 12 14

32°

34°

36°

38°

40°

See Figure 100

VI = 10 mV

TA = 25°CCL = 20 pF

ÁÁÁÁ

mφ

Figure 95

See Figure 100

VI = 10 mVCL = 20 pF

VDD = 5 mV


40°

12520°

–50 –25 0 25 50 75 100

24°

28°

32°

36°

PHASE MARGINvs


38°

34°

30°

26°

22°

m –

Pha

se M

argi

n

ÁÁÁÁ

mφ






Figure 96


VDD = 5 mV

TA = 25°CSee Figure 100

VI = 10 mV

0CL – Capacitive Load – pF

37°

10025°

20 40 60 80

27°

29°

31°

33°

35°

PHASE MARGINvs

CAPACITIVE LOAD

10 30 50 70 90

m –

Pha

se M

argi

n

ÁÁÁÁ

mφ

Figure 97

75

1V

N –

Equ

ival

ent I

nput

Noi

se V

olta

ge –

nV

/Hz

f – Frequency – Hz

200

10000

25

50

100

125

150

175

10 100

EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY

Vn

ÁÁÁÁÁÁn

V/

Hz ÁÁÁÁÁ


TA = 25°CRS = 20ΩVDD = 5 V

ÎÎÎÎÎÎSee Figure 99




PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits

Because the TLC271 is optimized for single-supply operation, circuit configurations used for the various testsoften present some inconvenience since the input signal, in many cases, must be offset from ground. Thisinconvenience can be avoided by testing the device with split supplies and the output load tied to the negativerail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit givesthe same result.

+

VDD

CL RL

VO

VI VI

VO

RLCL

–

+

VDD+

VDD–

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

–

Figure 98. Unity-Gain Amplifier

VDD–

+

VDD+–

+

1/2 VDD

20 Ω

VO

2 kΩ

20 Ω

VDD–

20 Ω 20 Ω

2 kΩ

VO


Figure 99. Noise-Test Circuit

100 ΩVDD

–

+

10 kΩ

VO

CL

1/2 VDD

VI VI

CL

100 Ω

VO

10 kΩ

–

+

VDD+

VDD–


Figure 100. Gain-of-100 Inverting Amplifier






input bias current

Because of the high input impedance of the TLC271 operational amplifiers, attempts to measure the input bias currentcan result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pA,a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneousmeasurements:

1. Isolate the device from other potential leakage sources. Use a grounded shield around and between thedevice inputs (see Figure 101). Leakages that would otherwise flow to the inputs are shunted away.

2. Compensate for the leakage of the test socket by actually performing an input bias current test (using apicoammeter) with no device in the test socket. The actual input bias current can then be calculated bysubtracting the open-socket leakage readings from the readings obtained with a device in the test socket.

One word of caution: many automatic testers as well as some bench-top operational amplifier testers us theservo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage dropacross the series resistor is measured and the bias current is calculated). This method requires that a device beinserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using thismethod.

V = VIC

41

58

Figure 101. Isolation Metal Around Device inputs (JG and P packages)

low-level output voltage

To obtain low-supply-voltage operation, some compromise is necessary in the input stage. This compromiseresults in the device low-level output being dependent on both the common-mode input voltage level as wellas the differential input voltage level. When attempting to correlate low-level output readings with those quotedin the electrical specifications, these two conditions should be observed. If conditions other than these are tobe used, please refer to the Typical Characteristics section of this data sheet.

input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. Thisparameter is actually a calculation using input offset voltage measurements obtained at two differenttemperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the deviceand the test socket. This moisture results in leakage and contact resistance which can cause erroneous inputoffset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since themoisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that thesemeasurements be performed at temperatures above freezing to minimize error.





full-power response

Full-power response, the frequency above which the amplifier slew rate limits the output voltage swing, is oftenspecified two ways: full-linear response and full-peak response. The full-linear response is generallymeasuredby monitoring the distortion level of the output while increasing the frequency of a sinusoidal inputsignal until the maximum frequency is found above which the output contains significant distortion. The full-peakresponse is defined as the maximum output frequency, without regard to distortion, above which fullpeak-to-peak output swing cannot be maintained.

Because there is no industry-wide accepted value for significant distortion, the full-peak response is specifiedin this data sheet and is measured using the circuit of Figure 98. The initial setup involves the use of a sinusoidalinput to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave isincreased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the sameamplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained(Figure 102). A square wave is used to allow a more accurate determination of the point at which the maximumpeak-to-peak output is reached.

(a) f = 100 Hz (b) B OM > f > 100 Hz (c) f = B OM (d) f > B OM

Figure 102. Full-Power-Response Output Signal

test time

Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFETdevices, and require longer test times than their bipolar and BiFET counterparts. The problem becomes morepronounced with reduced supply levels and lower temperatures.

APPLICATION INFORMATION

single-supply operation

While the TLC271 performs well using dual powersupplies (also called balanced or split supplies),the design is optimized for single-supplyoperation. This includes an input common modevoltage range that encompasses ground as wellas an output voltage range that pulls down toground. The supply voltage range extends downto 3 V (C-suffix types), thus allowing operationwith supply levels commonly available for TTL andHCMOS; however, for maximum dynamic range,16-V single-supply operation is recommended.

–

+

R4

VO

VDD

R2

R1

VI

VrefR3 C

0.01 µF

Vref VDDR3

R1 R3

VO (Vref VI)R4R2 Vref

Figure 103. Inverting Amplifier With VoltageReference






single-supply operation (continued)

Many single-supply applications require that a voltage be applied to one input to establish a reference level thatis above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 103).The low input bias current consumption of the TLC271 permits the use of very large resistive values toimplement the voltage divider, thus minimizing power consumption.

The TLC271 works well in conjunction with digital logic; however, when powering both linear devices and digitallogic from the same power supply, the following precautions are recommended:

1. Power the linear devices from separate bypassed supply lines (see Figure 104); otherwise, the lineardevice supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.

2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitivedecoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.

(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)

(a) COMMON SUPPLY RAILS

Logic

–

+ Logic LogicPowerSupply

SupplyPower

LogicLogic

–

+ Logic

OUT

OUT

Figure 104. Common Versus Separate Supply Rails





input offset voltage nulling

The TLC271 offers external input offset null control. Nulling of the input off set voltage may be achieved byadjusting a 25-kΩ potentiometer connected between the offset null terminals with the wiper Connected asshown in Figure 105. The amount of nulling range varies with the bias selection. In the high-bias mode, thenulling range allows the maximum offset voltage specified to be trimmed to zero. In low-bias and medium-biasmodes, total nulling may not be possible.

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ25 kΩ

N2VDD N2

N125 kΩ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

GND


–

+

–

+

N1

OUTOUT

IN–

IN+

IN–

IN+

Figure 105. Input Offset Voltage Null Circuit






bias selection

Bias selection is achieved by connecting the bias select pin to one of the three voltage levels (see Figure 106).For medium-bias applications, R is recommended that the bias select pin be connected to the mid-pointbetween the supply rails. This is a simple procedure in split-supply applications, since this point is ground. Insingle-supply applications, the medium-bias mode necessitates using a voltage divider as indicated. The useof large-value resistors in the voltage divider reduces the current drain of the divider from the supply line.However, large-value resistors used in conjunction with a large-value capacitor requires significant time tocharge up to the supply midpoint after the supply is switched on. A voltage other than the midpoint may be usedif it is within the voltages specified in the table of Figure 106.

0.01 µF

1 MΩ

VDD

Low

Medium

High

1 MΩ

To BIAS SELECT

BIAS MODEBIAS-SELECT VOLTAGE

(single supply)

Low

Medium

High

VDD1 V to VDD – 1 V

GND

Figure 106. Bias Selection for Single-Supply Applications

input characteristics

The TLC271 is specified with a minimum and a maximum input voltage that, if exceeded at either input, couldcause the device to malfunction. Exceeding this specified range is a common problem, especially insingle-supply operation. Note that the lower range limit includes the negative rail, while the upper range limitis specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the TLC271 very good inputoffset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOSdevices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopantimplanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates thepolarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offsetvoltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.

Because of the extremely high input impedance and resulting low bias current requirements, the TLC271 is wellsuited for low-level signal processing; however, leakage currents on printed circuit boards and sockets caneasily exceed bias current requirements and cause a degradation in device performance. It is good practice toinclude guard rings around inputs (similar to those of Figure 101 in the Parameter Measurement Informationsection). These guards should be driven from a low-impedance source at the same voltage level as thecommon-mode input (see Figure 107).

The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.

noise performanceThe noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stagedifferential amplifier. The low input bias current requirements of the TLC271 results in a very low noise current,which is insignificant in most applications. This feature makes the devices especially favorable over bipolardevices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noisecurrents.





noise performance (continued)

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

–

+

VI

VO VO


–

+

VOVI


–

+

VI

(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER

Figure 107. Guard-Ring Schemes

feedback

Operational amplifier circuits almost alwaysemploy feedback, and since feedback is the firstprerequisite for oscillation, a little caution isappropriate. Most oscillation problems result fromdriving capacitive loads and ignoring stray inputcapacitance. A small-value capacitor connectedin parallel with the feedback resistor is an effectiveremedy (see Figure 108). The value of thiscapacitor is optimized empirically.

electrostatic discharge protection

The TLC271 incorporates an internal electrostatic-discharge (ESD) protection circuit that prevents functionalfailures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised,however, when handling these devices as exposure to ESD may result in the degradation of the deviceparametric performance. The protection circuit also causes the input bias currents to be temperature dependentand have the characteristics of a reverse-biased diode.

latch-up

Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC271 inputsand output were designed to withstand –100-mA surge currents without sustaining latchup; however,techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodesshould not by design be forward biased. Applied input and output voltage should not exceed the supply voltageby more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supplytransients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply railsas close to the device as possible.

The current path established if latch-up occurs is usually between the positive supply rail and ground and canbe triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supplyvoltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and theforward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance oflatch-up occurring increases with increasing temperature and supply voltages.

ÏÏÏÏÏÏÏÏÏÏÏÏ

–

+

Figure 108. Compensation for InputCapacitance

VO






output characteristics

The output stage of the TLC271 is designed tosink and source relatively high amounts of current(see Typical Characteristics). If the output issubjected to a short-circuit condition, this highcurrent capability can cause device damageunder certain conditions. Output current capabilityincreases with supply voltage.

All operating characteristics of the TLC271 weremeasured using a 20-pF load. The devices drivehigher capacitive loads; however, as output loadcapacitance increases, the resulting responsepole occurs at lower frequencies, thereby causingringing, peaking, or even oscillation (see Figures110, 111, and 112). In many cases, adding somecompensation in the form of a series resistor in thefeedback loop alleviates the problem.

(a) CL = 20 pF, RL = NO LOAD (b) CL = 130 pF, RL = NO LOAD (c) CL = 150 pF, RL = NO LOAD

Figure 110. Effect of Capacitive Loads in High-Bias Mode

(c) CL = 190 pF, RL = NO LOAD(b) CL = 170 pF, RL = NO LOAD(a) CL = 20 pF, RL = NO LOAD

Figure 111. Effect of Capacitive Loads in Medium-Bias Mode


–

+

2.5 V

VO

CL

– 2.5 V

VI TA = 25°Cf = 1 kHzVI(PP) = 1 V

Figure 109. Test Circuit for OutputCharacteristics





output characteristics (continued)

(a) CL = 20 pF, RL = NO LOAD (b) CL = 260 pF, RL = NO LOAD (c) C L = 310 pF, RL = NO LOAD

Figure 112. Effect of Capacitive Loads in Low-Bias Mode

Although the TLC271 possesses excellent high-level output voltage and current capability, methods areavailable for boosting this capability, if needed. The simplest method involves the use of a pullup resistor (RP)connected from the output to the positive supply rail (see Figure 113). There are two disadvantages to the useof this circuit. First, the NMOS pulldown transistor, N4 (see equivalent schematic) must sink a comparativelylarge amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance betweenapproximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very lowvalues of RP, a voltage offset from 0 V at the output occurs. Secondly, pullup resistor RP acts as a drain loadto N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying theoutput current.

RPVDD–VO

IF IL IP


VI

VDD

RP

VO

R2

R1 RL

IP

IF

IL

IP = Pullup current required by the operational amplifier(typically 500 µA)

–

+

Figure 113. Resistive Pullup to Increase V OH






output characteristics (continued)

5 V

BIAS SELECT

0.016 µF


Low Pass

High Pass

Band PassR = 5 kΩ(3/d-1)(see Note A)

0.016 µF

BIAS SELECT

5 V

10 kΩ

10 kΩ

10 kΩ 5 V

BIAS SELECT


VI

5 kΩ

10 kΩ

10 kΩ

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

–

+

TLC271 –

+

TLC271 –

+

TLC271

NOTE A: d = damping factor, I/O

Figure 114. State-Variable Filter

BIASSELECT

R1, 100 kΩ

9 V

100 kΩ

C = 0.1 µF

R3, 47 kΩ

10 kΩ

10 kΩ

BIAS SELECT

VO (see Note B)

9 V

VO (see Note A)

R2

9 V

ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ


FO 1

4C(R2)R1R3

–

+

TLC271 –

+

TLC271

NOTES: A. VO(PP) = 8 VB. VO(PP) = 4 V

Figure 115. Single-Supply Function Generator




APPLICATION INFORMATION (HIGH-BIAS MODE)

100 kΩ10 kΩ

5 V

–5 V

VI–

5 V

VI+

–5 V

5 V

10 kΩ 95 kΩ

10 kΩ

BIASSELECT

BIAS SELECT

BIASSELECT

VO

R1, 10 kΩ(see Note A)

–5 V




–

+

TLC271

–

+

TLC271

–

+

TLC271

NOTE A: CMRR ad jus tment mus t be non induc t i ve .

Figure 116 . Low-Power Ins t rumenta t ion Ampl i f i e r

fNOTCH1

2RC

BIAS SELECT

5 V

VI

VOR10 MΩ

2C540 pF

10 MΩR

C270 pF

C270 pF

5 MΩR/2


–

+

TLC271

Figure 117. Single-Supply Twin-T Notch Filter





APPLICATION INFORMATION (HIGH-BIAS MODE)

VI(see Note A)

1.2 kΩ

4.7 kΩ

0.1 µF

22 kΩ

47 kΩ

0.01 µF

TIS 193

15 Ω

0.47 µF100 kΩ

1 kΩ

BIAS SELECT

20 kΩTL431TIP31

10 kΩ

250 µF,25 V VO

(see Note B)

110 Ω


–

+

TLC271

NOTES: A. VI = 3.5 to 15 VB. VO = 2.0 V, 0 to 1 A

+

–

Figure 118. Logic-Array Power Supply

BIASSELECT

100 kΩ

VO

12 V

N.O.Reset

0.5 µFMylar

H.P.5082-2835

12 V

BIASSELECT

VI ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

–

+

TLC271ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ

–

+

TLC271

Figure 119. Positive-Peak Detector




APPLICATION INFORMATION (MEDIUM-BIAS MODE)

NOTES: A. VO(PP) = 2 V


fo 1

2 R1R2C1C2

R268 kΩ

2.2 nFC2

VO

1N4148

470 kΩ

100 kΩ

C12.2 nF

R168 kΩ

47 kΩ

BIASSELECT

2.5 V

100 kΩ1 µF

100 kΩ

5 V

–

+

TLC271

B.

Figure 120. Wein Oscillator

2.5 VSELECTBIAS

0.22 µF

100 kΩ

100 kΩ

5 V

0.1 µF

10 kΩ

1 MΩ

0.01 µF1 MΩ

VI

VO


–

+

TLC271

Figure 121. Single-Supply AC Amplifier





APPLICATION INFORMATION (MEDIUM-BIAS MODE)

SELECTBIAS

2.5 V100 kΩ

1 µF

100 kΩ

100 kΩ

Gain Control1 MΩ

1 kΩ

10 kΩ

5 V

1 µF(see Note A)


–

+

TLC271

NOTE A: Low to medium impedance dynamic mike

– +

– +0.1 µF

+ –

Figure 122. Microphone Preamplifier

SELECTBIAS

VDD/2

VDD

10 MΩ

VO

VREF

150 pF

100 kΩ

15 nF

SELECTBIAS

VDD/2

VDD

1 kΩÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ


–

+

TLC271 –

+

TLC271

NOTES: A. NOTES: VDD = 4 V to 15 VB. Vref = 0 V to VDD–2 V

Figure 123. Photo-Diode Amplifier With Ambient Light Rejection


–

+

TLC271

2N3821

IS5 V

2.5 V

BIASSELECT

R

VI

ISVIR

NOTES: A. VI = 0 V TO 3 V

B.

Figure 124. Precision Low-Current Sink




APPLICATION INFORMATION (LOW-BIAS MODE)

TLC4066

VDD

BIAS SELECT

VI

90 kΩ

9 kΩ

X1

11

B

VDD

VI

S1

S2

C

A

C

A2

X22

B

1 kΩ

AnalogSwitch


+

–

TLC271

AV

Select S 1 S2

10 100

NOTE A: VDD = 5 V to 12 V

Figure 125. Amplifier With Digital Gain Selection

5 V

500 kΩ

500 kΩ

5 V

500 kΩ

0.1 µF

500 kΩ

VO2

VO1

BIASSELECT

BIAS SELECTÏÏÏÏÏÏÏÏÏÏÏÏ


–

+

TLC271

+

–

TLC271

Figure 126. Multivibrator





APPLICATION INFORMATION (LOW-BIAS MODE)


10 kΩ

VO

100 kΩ

BIAS SELECT20 kΩ

VI

–

+

TLC271

VDD


Figure 127. Full-Wave Rectifier

Set100 kΩ

VDD

BIASSELECT

10 kΩ

100 kΩReset

33 Ω


+

–TLC271


Figure 128. Set/Reset Flip-Flop

BIAS SELECT

5 V

0.016 µF

10 kΩ10 kΩ

VO0.016 µF

Vi


+

–

TLC271

NOTE A: Normalized to FC = 1 kHz and RL = 10 kΩ

Figure 129. Two-Pole Low-Pass Butterworth Filter

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductorproduct or service without notice, and advises its customers to obtain the latest version of relevant informationto verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable atthe time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques areutilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of eachdevice is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, orsevere property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TIproducts in such applications requires the written approval of an appropriate TI officer. Questions concerningpotential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, orinfringement of patents or services described herein. Nor does TI warrant or represent that any license, eitherexpress or implied, is granted under any patent right, copyright, mask work right, or other intellectual propertyright of TI covering or relating to any combination, machine, or process in which such semiconductor productsor services might be or are used.

Copyright 1996, Texas Instruments Incorporated

Input Offset Voltage DriftTypically D, JG, OR P PACKAGE 0 ... · Vn Equivalent input noise voltage...

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Transcript of Input Offset Voltage DriftTypically D, JG, OR P PACKAGE 0 ... · Vn Equivalent input noise voltage...