An Analog Perspective on Device Reliability in

32nm High-κ Metal Gate Technology

Florian Raoul Chouard∗, Shailesh More∗, Michael Fulde† and Doris Schmitt-Landsiedel∗

∗Lehrstuhl fur Technische Elektronik, Technische Universitat Munchen

Munchen, Email: florian.chouard@tum.de†Intel Mobile Communications GmbH, Villach, Austria

Abstract—An assessment on analog circuit reliability for anadvanced 32nm high-κ metal gate technology is given fromthe analog designer’s point of view. Selected analog circuitblocks are investigated with respect to device stress states. Acustom test structure, designed to reveal analog related devicecharacteristics including relaxation effects, was used to performstress measurements. In addition to common aging in inversionmode, degradation in accumulation mode is determined.Experiments reveal that relaxation shows a large variety indrift behavior, and degradation induced variations - even foranalog size devices - can reach significant values. Both topicsare main issues for analog circuits design. Thereupon a generalapproach to consider device aging for analog circuit reliabilityis proposed.

Index Terms—analog, circuit reliability, aging, degradation,NBTI, PBTI

I. INTRODUCTION

Non-constant field scaling in advanced CMOS technology

nodes increases the emergence of well known electrical field

driven degradation effects like Negative Bias Temperature

Instability (NBTI) in pFETs and Hot-Carrier Injection (HCI).

Moreover, introduction of high-κ materials into MOS di-

electrics debuts a new degradation effect called Positive Bias

Temperature Instability (PBTI) in nFETs [1]. On the other

hand, reduced supply voltage leads to a reduction in voltage

signal headroom which generally increases the sensitivity

towards parameter drifts.

For analog circuits, device matching plays an important role

in the design and is one of the main causes for their large area

consumption. Furtheron, analog circuits exhibit a much more

complex degradation behavior than digital circuits. Each tran-

sistor has different stress conditions and degradation effects,

and already small deviations from the operating point can

cause malfunction of the circuits. Transistors can experience

a constant stress for a long time, other than the frequent

switching of nodes in digital logic, so relaxation of stress

effects after long stress is important. In our investigations

of differential amplifiers in [2], we showed that asymmetric

stress induces mismatch. Effect relaxation contributes as a

transient component which is not yet considered in aging

prediction models, although it appears during circuit operation.

Another critical issue is the possibility of mismatch induced by

statistical variations of degradation effects. An NBTI related

investigation was carried out in [3]. Further general investi-

gations on device degradation impact on digital and analog

circuits, design-in reliability modeling and countermeasures

are treated in [4]–[9].

In this work we present the employed technology related

aging models and discuss their usage in circuit age prediction.

Basing on our foregoing work, device stress states appearing

in selected analog circuits are discussed from a designer’s

point of view, and an outline over the most critical device

states is given. A test circuit for advanced device aging tests

is proposed, our experimental procedure is presented and the

model equations used for monitoring ’online’ degradations are

derived. We also discuss our approach for realistic accelerated

aging in the experimental tests. Afterwards, we examine

measurement results for distinct stress and transistor types. In

the end we discuss the experimental findings and summarize

this work in the conclusion.

II. ANALOG CIRCUIT RELIABILITY

A. Non-Destructive Device Aging

To guarantee reliable operation of an analog circuit, a

stable, time-invariant behavior of its incorporated transistors

is required. But current/voltage characteristics can change

during product lifetime according to its operation state and

temperature. Electric fields in the device may lead to formation

of charge in the MOS insulator, typically weakening the tran-

sistor’s current characteristic. After bias stress removal some

charge can be released, inducing relaxation to the degradation

drift. Bias Temperature Instability (BTI) mechanisms are in-

duced by high gate bias, maintaining high vertical electric field

in the MOSFET. Negative BTI (NBTI) for pMOS transistors

is known for at least 3 decades, but physical origins are

still under discussion. The introduction of high-k materials

into the gate stack debuts a corresponding mechanism for

the nMOS - the Positive BTI (PBTI). Moreover, Hot-Carrier

Injection (HCI) is induced by high horizontal electric fields

in the vicinity of the drain junction. This stress state arises

only in saturation and aggravates with high drain bias and

short gate length. In advanced technologies, HCI also emerges

for switched-off devices and is called Non-Conductive HCI

(NCHCI). As analog circuit designs typically do not incorpo-

rate minimum gate lengths, HCI effects typically are small.

In our investigations degradation prediction is performed via

semi-empirical modeling based on [4]–[6] with a parameter

978-1-4244-9756-0/11/$26.00 ©2011 IEEE

M1 M2

M3 M4

M5

M6

M7

M8

M9M15

Rc RcCc Cc

CMREF

CMOUT

INN=VSS INP=VDD

OUTP=VDDOUTN=VSS

IBIAS

Fig. 1. State-of-the-Art fully-differential Miller OTA operated in open-loopworst case state

TABLE IDIFFERENTIAL AMPLIFIER: DEVICE STRESS IN WORST CASE OPERATION

BTI CHCI NCHCI

nMOS M2 M9 M1

pMOS M8 M4 M6

set related to the used 32nm HK/MG technology [10]. Both

types of permanent BTI degradations are modeled as a shift

of device threshold voltage

∆Vth = A · (Vgs

tinv)m · e(

∆E

kT) · Lα ·W β · tn. (1)

HCI degradation for both nMOS and pMOS is modeled as a

decrease of drain current and is predicted via

∆Id

Id= B · V p

ds · e(∆H

kT) · Lχ · tq (2)

with a distinct parameter set for conductive and non-

conductive state. Due to extremely long simulation times,

direct combination of the degradation prediction in the circuit

simulation proves to be incompatible. For our investigations,

we use the CAD aging tool RelXpert™ [11], extrapolating

device stress during the simulation time periods to the degrada-

tion time domain by employing the above aging effect models.

Moreover, the tool enables the consideration of time varying

stress conditions.

B. State-of-the-Art Differential Amplifier

In [2] and [12] we investigated the differential amplifier

depicted in fig. 1 with respect to its aging behavior. We

found that for worst case open-loop conditions (drafted in fig.

1), several devices of the circuit are exposed to significant

stress conditions inducing device mismatch and thus changing

device matching behavior in balanced operation. As depicted

in table I, all introduced degradation mechanisms are present

in this worst case operation state. The contributing effects may

misalign operating points in positive or negative direction and

add or subtract from the overall circuit mismatch. So, the

circuit itself can cause a masking of device aging drifts as it

only provides the collective effects of all single contributions.

For example, with regards to OUTP, NBTI/M8 yields to

negative and CHCI/M9 to positive operating point drifts and

Mp1 Mn1

Mp2 Mn2

VDD VSS

LtailLtail

ACTIVE BRIDGESWITCHED CAPS

VARACTORS

COIL

outp

outn

Fig. 2. Schematic of the differential LC-VCO

0 0.05 0.1 0.15 0.2 0.25 0.3

0

0.2

0.4

0.6

0.8

1

HCIMp Mn

PBTI Mn1NCHCI Mn2

PBTI Varactor

NBTI Mp2NCHCI Mp1

HCIMp Mn

PBTI Mn2NCHCI Mn1

PBTI Varactor

NBTI Mp1NCHCI Mp2

Time [ns]V

olta

ge

[V

DD

]

outpoutn

Fig. 3. VCO oscillation sequence: separation in device stress intervals

total mismatch at OUTP is due to their difference. Our investi-

gations revealed that contributions from HCI effects are small,

resulting from the design with moderate gate lengths, and

circuit mismatch is dominated by BTI mechanisms. Examining

the occurence of stress due to both BTI effects, we identify

M2 and M8 to operate in deep triode region with high Vgs

and low Vds.

C. LC Voltage Controlled Oscillator

In [13] we investigated a state-of-the-art low power LC-

VCO for GSM applications with respect to its long term

reliability as depicted in fig. 2. Analysis of the oscillation

waveform (fig. 3) showed several stress states at the devices

of the active bridge and the inversion mode MOS varactors

that occur during operation. When oscillation reach peak

voltage, devices of the active bridge are exposed to BTI stress

condition and the counterpart to NCHCI. In the region of

oscillation transition, active bridge devices enter saturation and

are exposed to HCI stress. Our further investigations revealed

that mainly degradation of the active bridge reduces supply

current that downgrades oscillator’s start-up ability. CHCI

contributions play a minor role as voltage stress conditions are

relaxed during oscillation transition and so CHCI degradation

is negligibly small. Also for this circuit type, BTI mechanisms

emerge as the dominant degradation effects in which devices

operate in deep triode region and are stressed with high Vgs

and low Vds.

D. Analog Circuit Stress Conditions

The usual operation of analog circuits in saturation does not

provide the most significant aging contributions, as BTI stress

bias proves to be moderate and CHCI is either limited by

...

Vout Voutb

D0 Db0 D1 Db1 D2 Db2

Vbias

Fig. 4. Basic test circuit structure for a nMOS implementation

relaxed stress bias or fair device lengths. But during circuit

operation, saturation states can be left and devices can also

enter triode region. According to the previous findings, the

deep triode region emerges as the most critical device stress

state, contributing to main parts of device parameter drifts.

Otherwise, NCHCI stress state may get a critical contributor

for a series of circuits tending to incorporate minimum length

devices such as VCOs. Contrary to HCI effects, the appearance

of BTI degradations can not be lowered by simple design

parameters like increasing device length. Another stress state,

that was not discussed yet, may occur for circuit standby

modes. In standby operation, internal floating nodes can

expose devices to uncommon operation conditions like the

stress in accumulation mode, which can also induce significant

device degradation as it conforms to the BTI counterpart of

the device, e.g. PBTI/pMOS.

For this reason, a detailed experimental investigation on device

degradation in deep triode and accumulation region has to

be performed. In the subsequent study, we also treat the

other open questions like appearance of relaxation effects and

induced variations for analog size devices.

III. TEST SETUP

A. Test Circuit

The basic structure of the test circuit for the further studies

is shown in fig. 4 for a nMOS version. It should provide

the ability to measure degradation of several cells, stressed

under equal conditions, before, during and after stress. The

idea of this test structure comes from differential stage basics,

where the current of the tail transistor is shared between

both pair transistors according to their input voltage. For

full swing digital voltages at inputs Di and a sufficiently

large pair dimensioning, the current of the tail source can be

switched between the outputs Vout and Voutb with a negligibly

small impact of the switch resistance. In the test system,

a digital logic block generates the control signals to switch

one of the cells to Vout and in the mean time all other

cells to Voutb. This enables the separate measurement of each

cell. Via the voltages at Vbias, Vout and Voutb the operation

region of the tail transistor can be adjusted in a sufficiently

large interval to apply different stress modes, simultaneouly

switching between the cells while monitoring current and

derive transistor characteristics of each cell as well.

This test structure was designed and manufactured as nMOS

and pMOS version in a 32nm high-κ metal gate technology

[10] providing 16 cells with an ’analog size’ tail transistor of

WL

= 8.0um2.0um . Aging simulations revealed that all performed

stress tests primarily impact the tail source transistor. Only

negligibly small degradation at the switch transistors occurs,

which in turn has marginal impact.

B. Measuring Process

Stress measurements were performed in a fully automated

stress setup to ensure reproducable and reliable degradation

results. Stress application and determination of cell charac-

teristics were performed with an Agilent 4155B parameter

analyser. For the temperature control we used a Temptronic

DPO315B ThermoChuck. The test sequence performed the

following steps:

1) input and output characteristic ’virgin’

2) high-T and V stress, while monitoring stress current

3) input and output characteristic ’aged’

4) high-T annealing step in off-state

5) input and output characteristic ’annealed’

The 1st, 3rd and 5th step determines for each cell the tail

transistor’s input characteristic in saturation mode as well as

its output characteristic. Due to temperature control time con-

stants, transistor characteristics in the 3rd step are performed

15min after the high-T stress step. To ensure a sufficiently

high resolution for the Vth extraction, acquisition step size dur-

ing the input characteristic measurement was chosen smaller

around the expected Vth. Monitoring stress current while

switching through all cells during the stress phase offers the

possibility to monitor online degradation including relaxing

components of the degradation. The annealing step reveals the

long term stability of the aging induced parameter drifts.

C. Approximative Model for Online Degradation

Via an approximative model equation, Vth drifts can be

derived from the measured current degradation of each cell.

Starting with the basic MOSFET model equation for triode

region operation,

ID = µCox

W

L

[

(Vgs − Vth)Vds −1

2V 2ds

]

. (3)

Triode region stress current degradation can be expressed as

∆ID =ID,virgin − ID,aged

=µCox

W

L

[

(Vgs − Vth)Vds −1

2V 2ds

]

− µCox

W

L

[

(Vgs − Vth −∆Vth)Vds −1

2V 2ds

]

=µCox

W

L∆VthVds. (4)

Normalization to the stress current in the virgin case leads to

∆ID

ID,virgin

=µCox

WL∆VthVds

µCoxWL

[

(Vgs − Vth)Vds −12V

2ds

] (5)

Assuming deep triode region operation V 2ds ≈ 0 and eq. 5

reduces to∆ID

ID,virgin

≈∆Vth

(Vgs − Vth)(6)

0.3 0.4 0.5 0.6 0.7 0.8

10

20

30

40

50

60

70

80

90

I D,n

[%

I D,n

,max]

Vgs

[V]

nMOS VirginnMOS AgednMOS Annealed

−0.8 −0.7 −0.6 −0.5 −0.4 −0.3

90

80

70

60

50

40

30

20

10

I D,p

[%

I D,p

,max]

pMOS VirginpMOS AgedpMOS Annealed

Aging nMOS

Annealing nMOSAging pMOS

Annealing pMOS

Fig. 5. Input characteristic of nMOS (lower right part) and pMOS (upperleft part) circuit: virgin, after stress in inversion mode and further high-Tannealing; all 16 cells at 25°C

Vth can be determined from the extraction of the input

characteristic, while its temperature drift during the stress test

can be neglected, because the overdrive voltage is dominated

by the high stress Vgs. The critical value is ID,virgin that has to

be measured at time zero of the stress phase. Due to equipment

timing limitations, the sampling of the virgin stress current

can be performed only a few 100ms after stress application

yielding a slightly lower estimation of the ’online’-∆Vth.

D. Operation Use Case and Aging Acceleration

In this study, the circuit is investigated for an operation use

case of 4 years at 85°C with a slighty elevated supply of 105%

worst case VDD. Aging acceleration of this use case for a 104s

stress test is performed via elevation of temperature to 125°C

and stress voltage derived to fulfill equation 7.

∆Vth,op (Vop, Top, top) = ∆Vth,str (Vstr, Tstr, tstr) (7)

The annealing step is also run for 104s at 125°C for switched-

off circuit. Aging simulations of operation use case and

its corresponding accelerated stress case proved that for the

nMOS and the pMOS circuit primarily BTI degradation of

identical magnitude is induced in the tail transistor. All further

generated aging mechanisms turned out to be negligibly small.

IV. EXPERIMENTAL RESULTS

A. Input and Output Characteristic

Fig. 5 shows the input characteristic of the nMOS and the

pMOS before stress, after stress in inversion operation and

further annealing in off-state. The three graphs correspond to

step 1), 3) and 5) of the measurement process described above.

Fig. 5 shows that for both device types, the inversion operation

scenario leads to a general weakening of transistor current. For

completeness, the output characteristic of the nMOS circuit

is also shown in fig. 6. Comparing current characteristics

after the stress step (’Aged’) and the further annealing step

(’Annealed’), reveals that aging induced drift partially shifts

back which is related to long term relaxation effects. To verify

the approach of mapping BTI degradation solely in a drift of

threshold voltage instead of a partitioning in ∆Vth and ∆µ, fig.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

10

20

30

40

50

60

70

80

90

100

I D,n

[%

I D,n

,max]

Vds

[V]

nMOS VirginnMOS AgednMOS Annealed

Aging nMOS

Annealing nMOS

Fig. 6. Output characteristic for nMOS circuit: virgin, after stress in inversionmode and further high-T annealing; all 16 cells at 25°C

0.3 0.4 0.5 0.6 0.7 0.8

10

20

30

40

50

60

70

80

90

I D,n

[%

I D,n

,max]

Vgs

[V]

nMOS VirginnMOS AgednMOS Annealed

−0.8 −0.7 −0.6 −0.5 −0.4 −0.3

90

80

70

60

50

40

30

20

10

I D,p

[%

I D,p

,max]

pMOS VirginpMOS AgedpMOS Annealed

Fig. 7. Input characteristic of nMOS (lower right part) and pMOS (upperleft part) circuit including compensation of aging induced ∆Vth: virgin, afterstress in inversion mode and further high-T annealing; all 16 cells at 25°C

7 depicts the measured input characteristics compensated with

respect to the derived threshold voltage drift ∆Vth. After the

compensation, curves approximately match each other. Only a

very small current weakening can be seen that can be related

to a negligibly small mobility degradation.

Fig. 8 depicts the nMOS and pMOS input characteristic for

0.3 0.4 0.5 0.6 0.7 0.8

10

20

30

40

50

60

70

80

90

I D,n

[%

I D,n

,max]

Vgs

[V]

nMOS VirginnMOS AgednMOS Annealed

−0.8 −0.7 −0.6 −0.5 −0.4 −0.3

90

80

70

60

50

40

30

20

10

I D,p

[%

I D,p

,max]

pMOS VirginpMOS AgedpMOS Annealed

Annealing nMOS

Aging nMOS

Annealing pMOS

Aging pMOS

Fig. 8. Input characteristic of nMOS (lower right part) and pMOS (upperleft part) circuit: virgin, after stress in accumulation mode and further high-Tannealing; all 16 cells at 25°C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1595

100

105

110

115

Vth

[%

Vth

,virgin

]

Block #

nMOS VirginnMOS AgednMOS Annealed

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1597.5

100

102.5

105

Vth

[%

Vth

,virgin

]

Block #

pMOS VirginpMOS AgedpMOS Annealed

Fig. 9. Cell threshold voltage of nMOS and pMOS circuit: virgin, after stressin inversion mode and further high-T annealing; all measurements at 25°C

the accumulation stress case. Acceleration stress voltages were

used from the inversion mode counterpart, e.g. for the nMOS

the corresponding pMOS NBTI stress voltage. Contrary to

the inversion operation case, accumulation mode aging of the

nMOS leads to a higher on current of the ’aged’ device. This

is induced by a negative shift in threshold voltage, indicating a

formation of positive charge in the dielectric, probably related

to the formation of a p-accumulation layer. Accumulation

mode stress for pMOS, however, shows an opposite behavior.

Similar to the inversion operation, drain current is weakened,

resulting from an increase of the absolute |Vth|. For both

device types the annealing step leads to a relaxation of the

generated drift back to the virgin state. As in inversion mode

stress, a significant degradation in carrier mobility could not

be seen.

B. Threshold Voltage Behavior

Device threshold voltage extraction was performed via the

constant current density definition of 300nAWL

for nMOS

and −70nAWL

for pMOS devices from the input current

characteristic in saturation. Fig. 9 shows the extracted Vth of

each cell for the ’virgin’, inversion mode ’aged’ and ’annealed’

circuit for nMOS and pMOS, respectively. Vth values are

normalised to the mean threshold voltage of the ’virgin’ circuit.

Comparing nMOS and pMOS Vth confirms a larger drift for

the PBTI/nMOS than for the NBTI/pMOS that was already

expected from the plot in fig. 5. For both device types, the

high-T annealing step reduces degradation by approximately

20%. Investigating fig. 9 with respect to variations shows that

besides the common ∆Vth drift only marginal variations are

added to the threshold voltage. This can be related to the large

area averaging of the used devices.

In contrast, fig. 10 depicts the aging induced ∆Vth drifts

of nMOS/PBTI and pMOS/NBTI normalized to the virgin

Vth. The plots include both ∆Vth drifts before and after

the annealing step and confirm the small amount of induced

variations. Corresponding plots of the Vth and ∆Vth behavior

for accumulation stress show similar results. To illustrate the

statistical data found for the investigated aging scenario, table

II depicts means, upper and lower absolute deviations of the

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 150

5

10

15

∆ V

t [%

Vth

,virgin

]

Block #

nMOS OnlinenMOS AgednMOS Annealed

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 150

1

2

3

4

5

∆ V

t [%

Vth

,virgin

]

Block #

pMOS OnlinepMOS AgedpMOS Annealed

Fig. 10. Cell threshold voltage drift of nMOS and pMOS circuit: duringstress at 125°C, after inversion mode stress and 125°C annealing at 25°C

virgin threshold voltages as well as the aging induced drifts.

For comparison, all values are normalised to the virgin Vth.

Due to a systematic ’well proximity effect’, Vth variations

for the nMOS circuit are higher than those for the pMOS

counterpart. The high absolute drift for nMOS/PBTI also

increases its deviations, which are significantly higher than for

the pMOS/NBTI. As the relation D

(X)shows similar values for

both device types, the same area dependent averaging behavior

can be deduced. This also reveals that the built-in systematic

Vth variation seems to have minor impact on variations due

to degradation. For accumulation stress scenario, nMOS/NBTI

variations seem to be even worse than for the inversion mode

aging. Due to the measured minor drifts for pMOS/PBTI also

the induced variations are small (not shown).

Going back to fig. 10, the solid line illustrates the derived

∆Vth from the stress current degradation during deep triode

region stress according to eq. 6. The nMOS ’online’-∆Vth

reveals to be even smaller than the evaluated value in the

subsequent ’aged’ parameter extraction. This can be related to

a distinct PBTI short time relaxation behavior, that was also

discovered in [2]. We assume this is caused by a two polarity

charge trapping during the nMOS/PBTI stress recovering

with differing time constants, yielding to the relaxation curve

shown in [2]. This explains the smaller ’online’ degradation

in contrast to the degradation 15min after the stress. However,

pMOS/NBTI ’online’-∆Vth shows the expected behavior of

a higher degradation during stress, as according to common

literature only equal polarity charge formation occurs. In

this case ’online’-degradation is even twice the degradation

after the annealing step, which has to be considered when

performing circuit reliability simulations.

C. Discussion

The preceding investigations about the relaxation behavior

of aging induced Vth drifts show a large variety in magnitudes

and general relaxation behaviors. Due to its vast relaxation

time constants, a simple consideration of ’permanent’ param-

eter drift to prove circuit reliability reveals to be neither a

realistic modeling of device aging nor a suitable one, due to the

lack of definition of a ’permanent’ drift. As a first approach,

TABLE IICOMPARISON OF THRESHOLD VOLTAGE AND AGING INDUCED DRIFT

VARIATIONS: MEAN VALUES, UPPER AND LOWER MAXIMUM DEVIATIONS

IN % OF VIRGIN CIRCUIT Vth

nMOS X in %Vth Dmax in %Vth Dmin in %Vth

Vth 100 0.54 -0.60

∆Vth,PBTI 9.04 0.13 -0.18

∆Vth,NBTI -5.41 0.17 -0.15

pMOS X in %Vth Dmax in %Vth Dmin in %Vth

Vth 100 -0.23 0.24

∆Vth,NBTI 1.59 -0.03 0.03

∆Vth,PBTI 0.25 -0.02 0.03

we propose to consider and distinguish device degradation

similar to the preceding investigations: ’online’-degradations

without any relaxation occured, drifts after a stress period and

relaxation with short time constants and drift including long

term relaxation components in the product lifetime region. A

more detailed investigation for critical analog circuit blocks

like open loop amplifiers/comparators can be performed with

an accurate relaxation behavioral model according to [14] and

[15].

The investigation of variations showed that for minor drifts

also induced variations play a negligible role. But for drifts

reaching the 10% Vth region, aging induced variations do

not play a minor role besides the process variations any-

more, although the large device area fulfills defect averaging.

Especially for cases of large aging drifts in combination

with limited area consumption, aging induced variations can

get significant and have to be considered according to [16].

Nevertheless, we expect degradation induced variations under

symmetric stress conditions to be of minor importance for

future analog circuit designs. However, variations due to

asymmetric voltage stress will overcome effect and process

variations.

A new method of active countermeasures regarding aging

induced drifts in analog circuits could be the intentional

operation in accumulation mode to counteract and compen-

sate generated drifts under inversion mode operation. For a

validation of this approach, compound aging stress test will

be required.

V. CONCLUSION

This work investigates analog circuit reliability for an ad-

vanced 32nm high-κ metal gate technology. We showed that

the most critical operation stress state for analog circuits is

the deep triode region, but also operation in accumulation

can occur in circuit standby mode, that is commonly not

covered by aging prediction models. A distinct test structure

to investigate device degradation for these stress scenarios as

well as relaxation behavior and statistic variations has been

developed. Measurements revealed that absolute degradations

for nMOS/PBTI in an equal aging scenario are larger than

the pMOS/NBTI counterpart. For the equivalent operation

in accumulation nMOS/NBTI shows Vth drifts in opposite

direction to the PBTI case. In contrary, pMOS/PBTI drifts

show only small drifts in the same direction as for the inversion

mode stress. Relaxation behavior of aging effects results in

a general difficulty to determine Vth drifts for circuit relia-

bility simulations. Therefore we proposed to consider three

characteristic points during relaxation, namely the beginning,

the relaxation after short times and the end of the relaxation

phase. The results regarding statistic variations showed that

for large area transistors, only for high absolute degradations,

aging induced variations can reach the magnitudes of process

variation. Nevertheless, we find that asymmetric stress is the

main contributor for aging induced variations.

ACKNOWLEDGMENT

This work was supported by the European Commission and

the Austrian government in the MODERN project (ENIAC-

120003). The authors thank the entire reliability team at

Infineon for contributions to these studies. Further, we thank

Mr. H. Mulatz and Mr. W. Pielock for support regarding the

sample packaging, bonding and test setup.

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