A 30V EDMOS with Orthogonal Gate Structure Based on a 0.18μm CMOS Technology

Hao Wang, H. P. Edward Xu, Wai Tung Ng Electrical & Computer Engineering Department,

University of Toronto Toronto, Ontario, Canada, M5S 3G4

[ngwt@vrg.utoronto.ca]

Kenji Fukumoto, Ken Abe, Akira Ishikawa, Hisaya Imai, Kimio Sakai, Kaoru Takasuka

Asahi Kasei EMD Nishi-Shinjuku 1-23-7, Shinjuku-ku, Tokyo, Japan, 160-0023

takasuka@dc.ag.asahi-kasei.co.jp

Abstract—A transistor with an orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has a horizontal section to provide normal gate control and a vertical section to provide field shaping. This device is implemented in a 0.18μm 30V HV-CMOS process. Comparing to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The Figure-of-Merit (FOM) is improved by 37.5%.

I. INTRODUCTION

In recent years, significant effort has been directed to the optimization of the BV-Ron,sp performance of power semiconductor devices in order to reduce conduction loss. However, in order to operate power MOSFETs at high switching frequencies, it is also paramount to reduce switching loss. In particular, the total gate charge and gate capacitance must be reduced. In this paper, we propose an EDMOS transistor with a novel orthogonal gate electrode designed for fast switching speed and low switching loss.

II. DEVICE STRUCTURE

The proposed orthogonal gate EDMOS structure is as shown in Figure 1(a). It is identical to the conventional EDMOS transistor (Figure 1(b)) with the exception of the gate structure. RESURF [1], [2] concept is used to achieve optimized tradeoff between high breakdown voltage and specific on-resistance (Ron,sp). The n-drift region is placed underneath the STI. The orthogonal gate transistor has a gate electrode that is folded into the Shallow Trench Isolation (STI) region. The horizontal and vertical gate electrode segments are used to provide gate control and electric field shaping. This allows the orthogonal gate EDMOS transistor to have the same breakdown voltage as the conventional EDMOS transistor. Since the overlap between the gate electrode and the n-drift drain region is only amounted to the thickness of the gate electrode, the overall gate-drain capacitance, Cgd is significantly reduced.

The deep n-well formed by high energy ion implantation is used for isolation between adjacent devices. Moreover, with the deep n-well, the n-channel EDMOS transistor can also be

used as a high side driver, as well as other applications that require floating source potential.

The orthogonal gate EDMOS is designed to be compatible with a 0.18μm CMOS fabrication technology. The gate structure can be easily incorporated as part of the STI fabrication step. The fabrication process is described in the next section.

A

p+ n+

HV p-well

p-substrate

deep n-well

STI STI STIn+

n-drift

gate drainsourcebody A

p+ n+

HV p-well

p-substrate

deep n-well

STI STI STIn+

n-drift

gate drainsourcebody

Figure 1(a). Orthogonal gate EDMOS transistor structure.

p+ n+

HV p-well

p-substrate

deep n-well

STI STI STIn+

n-drift

gate drainsourcebody

p+ n+

HV p-well

p-substrate

deep n-well

STI STI STIn+

n-drift

gate drainsourcebody

Figure 1(b). Conventional EDMOS transistor structure.

1-4244-1533-0/08/$25.00 ©2008 IEEE 20

Proceedings of the 20th International Symposium on Power Semiconductor Devices & IC's

May 18-22, 2008 Oralando, FL

III. FABRICATION PROCESS

The orthogonal gate EDMOS fabrication process is based on a 0.18μm CMOS technology developed by Asahi Kasei EMD. This technology accommodates both high voltage devices (30V n and p-type EDMOS transistors) and standard CMOS on the same substrate. The thermal budget allocated to the standard CMOS devices is designed to remain the same as before, hence the electrical characteristics of the standard CMOS devices are not altered.

The fabrication steps are compatible with the standard CMOS flow. Process modules are designed to be optional steps that can be added or removed from the baseline CMOS technology. Figure 2 is a condensed flow chart for the orthogonal gate EDMOS process. The starting wafer is a <100> oriented p-type wafer with doping concentration of 1×1015cm−3. At the beginning of the fabrication process, field oxidation is carried out to form a thick layer of oxide followed by active lithography and oxide etching to define the device area.

Standard CMOS Process Additional Steps

Figure 2. Standard CMOS process flow with additional steps for the orthogonal gate EDMOS implementation.

Prior to the formation of the STI, TEOS (Tetraethylorthosilicate) deposition and annealing, deep n-well and HV p-well ion implantations are performed. All the implanted impurities can be activated together during the STI annealing. The n-drift ion implantation is carried out after the STI annealing, because RESURF conditions require careful control of the n-drift dose and junction depth. The choice of this dose is based on diffusion trials and extensive process and device simulations. Gate lithography and etch, gate oxidation, poly-silicon deposition, poly-silicon etch and doping annealing are then carried out to form the gate electrode. The detail process flow to form the orthogonal gate is as illustrated in Figure 3. The vertical gate formation requires an extra mask (see Figure 3(b)) and an extra etching

step (see Figure 3(c)). The conventional gate mask is then used to definite the entire orthogonal gate electrode.

Thereafter, a thick inter level oxide deposition of TEOS is followed by contact lithography and oxide etching to form the contact window. Finally, metallization covers the chip surface and forms the contacts for the EDMOS.

HV p-welln-driftHV p-well

STI

n-driftHV p-well

STI

n-driftHV p-well

STI

n-drift

STI

photoresist

HV p-well n-drift

STI

HV p-well n-drift

STI

(a) (b)

(c) (d)

(e) (f)

HV p-welln-driftHV p-well

STI

n-driftHV p-well

STI

n-driftHV p-well

STI

n-drift

STI

photoresist

HV p-well n-drift

STI

HV p-well n-drift

STI

(a) (b)

(c) (d)

(e) (f)

Figure 3. Orthogonal gate fabrication process flow. (a) structure right after STI formation, (b) orthogonal gate lithography, (c) dry etching, (d) gate oxidation, (e) gate polysilicon deposition, (f) gate lithography.

IV. SIMULATION RESULTS

The fabrication process and electrical characteristics are simulated using TSuprem4 and Medici. The most prominent improvement is the reduction in Cgd, this is due to the minimization of the gate-to-drain overlap capacitance. The trench opening width is 0.2μm, and there is no vertical sidewall overlap between gate and drain. Comparing to a conventional EDMOS, a 75% Cgd reduction is observed at Vds= 0V. All other capacitances are also plotted in Figure. 4. The gate-to-source capacitance (Cgs) is smaller than that of conventional EDMOS transistor, and the drain-to-source capacitance (Cds) is comparable to conventional EDMOS transistor.

The input capacitance, Ciss = Cgs + Cgd, is the summation of gate-to-source and gate-to-drain capacitance. Cgs and Cgd are the most relevant intrinsic capacitances which are responsible for limiting the overall device performance in terms of device switching speed. The gate-to-substrate capacitance is much smaller in strong inversion case [3]. The formation of an inversion layer in the channel region provides an electrostatic shield between the gate and substrate, such that total gate charge ceases to respond to the changes of the substrate bias.

P-type substrate

Field oxide and active region lithography

STI annealing

Gate lithography

Gate oxidation

TEOS oxide deposition and contact formation

Metallization

HV p-well I/I

n-drift I/I

Vertical gateformation

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Therefore, gate-to-substrate capacitance is often neglected. By reducing the gate-to-drain (Miller) capacitance, the switching speed can be enhanced while switching loss can be reduced.

0

2E-16

4E-16

6E-16

8E-16

1E-15

1.2E-15

0 5 10 15 20 25 30

Vds (V)

Cgd

Cap

acita

nce

(F)

OG-EDMOS

Conventional gate EDMOS

0

2E-16

4E-16

6E-16

8E-16

1E-15

1.2E-15

0 5 10 15 20 25 30Vds (V)

Cgs

Cap

acita

nce

(F)

OG-EDMOS

Conventional gate EDMOS

0

3E-16

6E-16

9E-16

1.2E-15

1.5E-15

1.8E-15

0 5 10 15 20 25 30

Vds (V)

Cds

Cap

acita

nce

(F)

Conventional gateEDMOSOG-EDMOS

Figure 4. Comparison of Cgd, Cgs, and Cds between orthogonal gate and conventional EDMOS transistors.

The field plate extension is necessary in EDMOS transistors to alleviate the electrical field crowding in the drift region for a given breakdown voltage [4]. The orthogonal gate structure serves as a vertical field plate. The simulated

breakdown voltage is comparable to conventional EDMOS. Figure 5 illustrated the potential distribution in orthogonal gate EDMOS upon breakdown. Without the vertical field plate, the electrical potential lines concentrate at the gate edge and the breakdown voltage of 14V is significantly lower when compared to the orthogonal gate EDMOS of the same device size and n-drift region design.

(a) (b) Figure 5. Potential contours at 3V/line for (a) orthogonal gate EDMOS and (b) conventional EDMOS transistors.

In Figure 6, the specific on-resistance for the orthogonal EDMOS transistor is simulated for various lateral channel length, A (see Figure 1(a)), while keeping all other parameters constant. The channel resistance contributed by A is 2m ·mm2 per 0.1μm.

20

25

30

35

40

45

50

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Lateral channel length A (μm)

Ron

-sp (

mO

hm-m

m2 )

0

5

10

15

20

25

30

35

Bre

akdo

wn

volta

ge (V

)

Figure 6. Simulated specific on-resistance variation vs. lateral channel length.

Since the lateral channel length “A” does not have a strong influence on the breakdown voltage of the orthogonal gate EDMOS transistor, it can be shortened to further reduce the channel resistance.

The comparison of gate charge between the orthogonal gate and conventional EDMOS transistors is presented in Figure 7, the orthogonal gate EDMOS demonstrates about 37.5% reduction in total Qg at Vg = 10V. The total figure-of-merit (Ron × Qg) is improved by 37.5%. A comparison of simulated electrical characteristics between the orthogonal

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gate and conventional EDMOS transistors are as presented in Table 1.

V. PRELIMINARY FABRICATION RESULTS

The orthogonal gate concept has been applied to both n-type and p-type EDMOS transistor. The cross sectional diagram of these devices are as illustrated in SEM micrographs in Figure 8. The measured I-V characteristics of the prototype n-channel orthogonal gate EDMOS transistors are shown in Fig. 9. The orthogonal gate EDMOS achieved a breakdown voltage of 30V and Ron,sp = 50m ·mm2 at Vgs = 5V. At Vgs = 10V, Ron,sp = 40m ·mm2.

0

5

10

15

0E+00 1E-14 2E-14 3E-14 4E-14 5E-14

Gate Charge (Coul/μm)

Vgat

e (V

)

OG-EDMOS

Conventional gate EDMOS

Figure 7. Gate charge comparison between OG-EDMOS and conventional EDMOS transistors.

Table1. Electrical characteristics of the conventional and orthogonal gate EDMOS transistors

Single Cell Conventional Orthogonal Gate

Ron,sp(m -mm2) 40 40

BV(V) 30 30

Cgd(F)@Vds=0V 1.1×10-15 2.8×10-16

Cgs(F)@Vds=0V 9×10-16 7×10-16

Cds(F)@Vds=0V 1.5×10-15 1.5×10-15

Figure 8. SEM micrographs of the (a) n-type and (b) p-type orthogonal gate EDMOS transistors.

0E+0

1E-3

2E-3

3E-3

4E-3

5E-3

0 5 10 15 20

Vds (V)

I ds (A

)

Vg = 1V

Vg = 2V

Vg = 3V

Vg = 4V

Vg = 5V

Figure 9. Measured IV characteristics for the orthogonal EDMOS transistor.

VI. CONCLUSION

In summary, an orthogonal gate structure has been developed. The fabrication process is based on a 0.18μmCMOS technology from Asahi Kasei EMD. The breakdown voltage and on-resistance are comparable with conventional EDMOS transistors. The proposed EDMOS achieved 75% reduction in Cgd and 37.5% improvement in FOM, without degradation in Ron,sp. The orthogonal gate device concept is fully compatible with standard CMOS process.

ACKNOWLEDGMENT

The authors would like to thank Asahi Kasei EMD for financial support and devices fabrication. We also want to thank Auto21, NSERC for financial support, and express our sincere gratitude to Jaro Pristupa for his continuous help with CAD tools.

REFERENCES

[1] Adriaan.W.Ludikhuize, “A review of RESURF Technology”, International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp 11-18, 2000.

[2] Mohamed Imam et al., “Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process”, IEEE Transactions on Electron Devices, VOL.50, NO.7, July 2003.

[3] Yuanzheng Zhu et at., “Folded gate LDMOS with low on-resistance and high tranconductance”, IEEE Transactions on electron devices, VOL. 48, NO. 12, December 2001.

[4] Zia Hossain et al., “Field-plate effects on the breakdown voltage of an integrated high-voltage EDMOS transistor”, International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp237-240, 2004.

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