978-1-4673-5672-5/13/$31.00 2013 IEEE

On-chip 500uA at 5V above battery Dual-Chain Dickson Charge Pump with Regulated Clock Supply

Florin Bzitu Infineon Technologies Romania

Blvd. Dimitrie Pompeiu, No. 6, Bucharest, Romania florin.biziitu@infineon.com

AbstractThe proposed circuit is a dual pumping chain Dickson-type charge pump using both active and passive charge transfer switches and adaptive control of the clock amplitude in order to improve the power efficiency. The circuit is sourcing up to 500uA at 5V-6.5V above the battery voltage as part of a high side driver [5] and uses a battery related floating ground regulator to deliver the supply voltage for the charge pump core.

I. INTRODUCTION Most of the usual charge pump (CP) applications require

that the generated output voltage has a fixed value related to the chip ground potential. Automotive systems however must function within a battery voltage that ranges usually from 6V (cranking conditions at cold) to 28V (jump start) so it is therefore necessary to reference the charge pump output voltage to the battery voltage Vs. As the output of the proposed charge pump is required to be between 5V to 6.5V above Vs the actual values related to the chip ground will be 11V-12.5V for Vs =6V and 33V-34.5V for Vs =28V putting very high constraints on the charge pump design requirements if a ground referenced topology would be used.

Many of the monolithic charge pump circuit implementations are based on the Dickson topology [1], using some form of passive (mainly PN junction or CMOS diodes) or active charge transfer switches separating the pumping capacitors. Active charge transfer switch implementations solve the gain degradation problem of the Dickson CP by increasing the circuits complexity and using multiple non-overlapping clock signals and boosted switch topologies.

In order to improve the power efficiency, to limit the amount of emitted electromagnetic interference and also limit the CP output voltage when it is delivering less than the nominal load, a regulation mechanism must be implemented [3],[4].

II. CONCEPT AND DESIGN OF THE REGULATED CHARGE PUMP

A. A system perspective The proposed regulated CP block diagram is presented in

Fig.1.The main blocks are a Dickson-type CP core generating the high voltage output VCP, a VS related voltage regulator providing the battery related ground potential GNDCP and a control circuit which is sensing the output voltage and generating an error signal VF proportional to the difference between VCP and the clamp voltage VCLAMP. The error signal VF is fed back and effectively subtracted from the (band gap

Fig.1 The proposed regulated CP topology

derived) reference input of the CP voltage regulator modulating the GNDCP potential. Because the supply of the CP core is given by the difference between VS and GNDCP a variation of the GNDCP potential translates into variation of the clock amplitude driving the CP core.

The regulated CP has reached steady state operation when for a given load current the difference between VCP and VCLAMP (the VF error signal) is minimal.

A standard automotive BCD technology was used, that provides several CMOS voltage classes: low voltage (1.5V) analog and logic transistors, several types of medium voltage analog transistors and high voltage (60V) DMOS power transistors as well as bipolar diodes and transistors. For simplicity reasons, the VCLAMP reference voltage is generated by a series combination of Zenner and bipolar junction diodes. When multiple devices are available, the linear combination of diodes that exhibits the minimal temperature dependence can be chosen.

The VCLAMP diode based reference together with the RF resistor forms the control circuit that generates the VF error signal driving the reference input of the CP regulator.

The static transfer characteristic of a CP designed for resistive loads, using (as most of the high side CPs do) clamping as a regulation method is presented in Fig. 2.a.

Fig.2 Static transfer characteristics

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The CP is sized to provide the maximum DC current IL, max corresponding to the (VCLAMP, IL, max) point on the transfer curve. VCP, max is the maximum unclamped voltage the CP core is capable of delivering if the load current is zero. If the pump is delivering the maximum load current IL, max then the voltage clamp sinks no current because the output voltage is already at the desired level VCLAMP. Otherwise, if the load current is smaller, equal to IL, nom the additional (IL, max-IL, nom) current will be sinked by the clamping circuit.

In the proposed system, the CP transfer characteristic can change according to the load current value. The system will move to the transfer curve corresponding to the minimum VCLK amplitude that can maintain the output voltage equal to VCLAMP for the given load current. (Fig2b.) The closest transfer curve to the origin corresponds to the minimum value of clock amplitude (VCLK, min) and is the state of the CP when the load current is 0. In this state the CP core only needs to deliver the very small IF current necessary to generate the error voltage VF keeping the regulation loop operating. The farthest transfer curve corresponds to the state of the CP when it is delivering the maximum load current IL, max. In this case the IF current is 0, the feedback error voltage is also 0 and the CP regulator has GNDCPREF as reference delivering the maximum amplitude VCLK, max=VS-GNDCPREF to the CP core.

B. The charge pump core implementation

Fig.3 The charge pump core

The implemented charge pump core consists of two Dickson pumping chains working in anti-phase. Charge is transferred to the output every semi-period (making the effective pumping frequency 2fCLK) and stored in the Ctank output capacitor ensuring a low output voltage ripple and a fast load transient response.

The clock signal generator has a Osc clock signal input coming from the on-chip RC oscillator (in the 1.5V voltage domain) and delivers 4 non-overlapping clock signals of equal amplitude VCLK =VS-GNDCP in the VS related voltage domain (between the GNDCP and VS supply rails) where the CP core is operating. The circuit consists of a 2 phase non-overlapping

clock signal generator realized in the low voltage domain which produces the necessary clock phases and their complements that are then levelshifted to the VS reffered voltage domain to drive the CP core. Non-overlapping phase relationship exists between Clk_N and nClk_N and between Clk_P and nClk_P in order to ensure that charge transfer via the N and P active switches is unidirectional. The simple clock generation mechanism allows the use of active switches only in the first and the final stages in each pumping chain. An implementation using only active switches would require additional non-overlapping phases. The chosen topology using both passive and active switches is a good compromise between charge transfer efficiency and system complexity.

The N1A and N1B switches are implemented using medium voltage NMOS devices actively switched in the triode region during charge transfer. The structure is symmetric, the boosted gate signal for one active switch being provided by the previously charged complementary node on the other pumping chain. While charging C1B the control signal for N1B is provided by Node1A and vice versa. The P-type switches in each pumping chain are implemented using medium voltage PMOS devices. In order to safeguard against the increased latch-up risk of the PMOS, an active bulk switching mechanism [2] was implemented with the additional PB1A and PB1B transistors by always keeping the bulk of all of the PMOS devices at the highest potential in the circuit and storing this potential on a small capacitor (CB) between refresh phases. Drain-bulk overstress is another reason that prevents the use of active N and P type switches in the other pumping stages determining (VCLK, max 4V) < |VDB, max| / 2.

The ND1A, ND1B passive charge transfer switches are NMOS diodes implemented using another type of medium voltage transistor with access to the bulk terminal. In order to forward bias the bulk source junction and lower the threshold voltage during the charge transfer phase, the bulk connection of the diodes is tied to the drain terminal. In order to verify that the majority of the charge transfer occurs through the transistor channel and not through the bulk to source diodes, test structures of the used NMOS diode configuration have been built and the reverse recovery time and forward drop during charge transfer were measured. The reverse recovery time was found to be very small and most importantly independent on the value of the forward current flowing through the NMOS diode before the switch-off event. This eliminates the possibility of a bipolar conduction mechanism as being dominant. Voltage drop measurements also confirm this hypothesis.

C. Charge pump (VS related) regulator implementation A linear regulator topology is used for the VS related CP

supply. The GNDCP output is sampled directly, without using a resistor divider. The CP regulator closed-loop gain is Kreg 1 as the regulators feedback loop is keeping the output GNDCP GNDCPREF_IN.

The regulator is divided into three voltage domains. The ground related low and medium voltage domains are shielded from the VS by high voltage cascodes. The same approach is also used to shield the medium voltage transistors residing in

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Fig.4 a). CP regulator implementation b).Controller circuit small signal model c). CP regulation loop small signal model

the VS domain from the ground potential.A voltage to current converter (OP1, M1, R3) having as input the bandgap reference is biasing the resistor divider consisting in R3 through R7 generating the VS related reference voltage GNDCPREF as well as the bias potentials for the pre-regulator (Bias_N and Bias_P) and high voltage separator transistors (Bias_HV_S). The VS related voltages depend only on the bandgap reference Vbg and precisely controlled (through careful matching) resistor divider ratios.

The reference voltage for the error amplifier GNDCPREF_IN is obtained by subtracting the (VCP depedent) VF voltage from the buffered (constant) GNDCPREF reference. This is the mechanism by which a variable clock supply is obtained in relation to the CP load.

The OTA1 stage residing in the VS related voltage domain together with M2 and M3 in the ground related medium voltage domain are forming the error amplifier of the CP regulator. Because the error amplifier is biased between the the actual GNDCP output and VS, a pre-regulator structure (NPRE, PPRE) is necessary to generate GNDCP before the regulator feedback loop starts operating .

The open-loop transfer function of the implemented regulator has two poles, with the dominant pole P1 being located at the gate of the pass transistor driven by the high impedance error amplifer output and the second pole P2 residing at the regulator output. The Miller capacitor CC takes advantage of the inverting gain across the pass transistor pulling the dominant pole to even lower frequencies, especially at lower loads. Since the pass device gain changes with varying load current, P1 is load depedent but much less sensitive than P2.. Because the CP core is always on (but driven by a variable VCLK) the minimum drain current of the pass transistor (equal to about 1mA, injected by the CP core at VCLK,min) is always sufficient to maintain P2 and the CGD generated RHP zero, Z1=gmpass/(CGD,pass+CC) above the open-loop unity gain frequency. Because of this, we can consider that the closed loop transfer function of the CP regulator HREG,CL(s) has a single pole at :

REG,CL P1,OL 1 AV,OL (1) where AV,OL is the open-loop voltage gain of the CP regulator.

D. Regulated CP small signal model and loop stability By using the small signal model in fig.5c. the linear

transfer function of the system can be derived. For the proposed Dickson-type CP architecture delivering the IL load current, implemented with N pumping stages and M pumping chains, using identical Cp pumping capacitors, having CS total stray capacitance in each pumping stage, supplied by VCLK and driven by a fCLK frequency clock we can write:

VCP VCLK N CPCP CS VCLK N 1 VD N ILM C CS fCLK (2) Only the first (N-type) and the last (P-type) switch in each pumping chain are the active type and have no voltage drop during charge transfer, while the rest of the diode-type switches with the bulk connected to the drain, have VD500mV drop. For the implemented CP core we have N=3, M=2 , VCLK, max 4V and fCLK 16MHz.

By considering the clock supply VCLK as the input, the CP core can be modeled as a linear amplifier having the gain:

Kpump VCPVCLK 1 N , (3) with = Cp/(Cp+CS) as the ratio of the capacitive divider introduced by CS and the output impedance given by :

Rout,cp NM Cp CS fCLK NM CP/ fCLK (4) Considering Kreg 1 and RF >>RD the regulated CP open

loop gain is : KL Kpump RLRout,cp RL 1 RFRF RD KregKL Kpump RLRout,cp RL (5) where RD=nrD+rZ is the sum of the small signal resistances of the diode chain in the control circuit (Fig.5b). The (-1) factor in the gain expression is introduced to take into account the polarity of the error signal VF generated by the control circuit.

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The CP open-loop transfer function has two poles with thedominant pole CP being defined by the equivalent pump output resistance, the load resistance and the sum of the storage and load capacitances: CP 1/ Rout,cpRLRout,cp RL Ctank CL (6) The second loop pole is generated by the CP regulator, being located at REG, CL. In case of the regulated CP, in addition of assuring that the output voltage ripple specifications are met, the value of Ctank is also chosen in order to establish the dominant pole of the pump regulation loop CP.

Given the fact that in most technologies is between 0.7 and 0.9 we conclude from (3) and (5) that the maximum loop gain of the implemented regulation loop is about 10dB. The low gain value implies that a pole separation of a decade is sufficient to ensure stability but not sufficient to keep the pump output accurately at the desired level Vclamp. This is not a drawback in this particular application because the output voltage has a wide tolerance (minimum 5V, maximum 6.5V).

With VCLK,max4V imposed by active switch overstress limits, VCLK, min needs to be determined in order to evaluate the clock amplitude variation domain when the regulation loop is operating. When the CP has a load IL lower than IL,max, VCLK,max is reduced by V(IL) in order to obtain VCLK(IL). Considering (2), (4) and the current through RF as (V(IL) /RF) we can find an expression for VCLK as a function of IL:

VCLK IL VCLK,max 1 N VCLK, max N1 VDILRout,cpVCLAMP2 N Rout,cp/RF (7)

For a VD of 500mV, with 0.9, N=3, RF >>Rout,cp and considering VCLAMP=9V (the CP core must provide 9V reffered to GNDCPREF=VS-4V in order to have VCP=VS+5V) we can calculate a VCLK,min=VCLK(0)3V.

III. MEASUREMENT RESULTS Figure 6 shows a photomicrograph of the fabricated

charge pump test chip. Two VS referred charge-pumps were included on the same chip, namely the regulated CP proposed in this article, and an identical, non-regulated CP using only voltage clamping, the latter being included for comparison purposes. Static measurements of the clock supply level versus load current are presented in Fig. 5a while graphs showing the measured CP output voltage versus load current are presented in Fig. 5b. The measured total ground current versus the sourced load current is shown in fig 5c. All voltages are measured relative to a nominal VS voltage of 13.5V. Measurements show that the regulation mechanism is operating as predicted, improving the efficiency compared to the non-regulated system at low to medium currents. (Fig.5d). As the load increases, the efficiencies of the two systems converge to the same value, as less current is being wasted by the clamping circuit of the non-regulated circuit.

IV. CONCLUSION A battery-referred, regulated charge pump circuit is

presented in this paper. The novel regulation method is based on the adaptive control of the clock supply driving the pump

Fig.5 a).VCLK versus load current. b). CP output voltage versus load current

c). Total ground current versus load current d).Efficiency of the regulated CP core vs. the non-regulated clamped CP core

Fig. 6 The fabricated charge pump test chip

core as a function of the load current. Stability is ensured by setting the filtering pole at the pump output as the dominant pole and by the inherent low open-loop gain of this topology. Measurements show that the circuit is capable of delivering up to 500uA of DC current at VS+5V in the [6V to 28V] VS range and [-40C to 150C] temperature range.

Only a high ohmic resistor (RF) and appropriate sizing of Ctank are required to transform a clamped CP into a regulated CP, making the presented mechanism simpler to implement than frequency regulation [3],[4] in VS related systems.

To improve the output voltage accuracy, an additional gain stage can be introduced in the pump regulation loop in order to amplify the error voltage fed back to the regulator. Such an approach would require an external Ctank filtering capacitor in the nF range to ensure stability.

REFERENCES [1]. J. F. Dickson, On-chip high-voltage generation in MNOS integrated

circuits using an improved voltage multiplier technique, IEEE JSSC, vol. SC-11, no. 3, pp. 374---378, June 1976.

[2]. P. Favrat, P. Deval, and M. J. Declercq, A high-efficiency CMOS voltage doubler, IEEE JSSC, vol. 33, pp. 410-416, March 1998.

[3]. Jae-Youl Lee et. al, A regulated charge pump with small ripple voltage and fast start-up, IEEE JSSC, Vol. 41, No. 2, February 2006

[4]. L. Aaltonen and K. Halonen, On-chip charge-pump with continuous frequency regulation for precision high-voltage generation,Proc. of the 2009 Ph.D. Research in Microelectronics and Electronics, July 2009, Cork, Ireland

[5]. R. Gariboldi and F. Pulvirenti, A 70 mV intelligent high side switch with full diagnostics, IEEE JSSC, vol. 31, no. 7, pp. 915-923, 1996.

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