Fully Integrated,Highly Linear, Wideband LNA in 0.13µm CMOS Technology

Hira Shumail1, Maliha Nisar1, Tooba Muzaffar1, Sana Arshad1 and Qamar-ul-Wahab1,2

Department of Electronic Engineering1 NED University of Engineering & Technology

Karachi, Pakistan hirashumail@neduet.edu.pk

Division of Electronic Devices2 Department of Electrical Engineering

Linköping University Linköping, Sweden

Abstract— This paper presents the design of a fully integrated, highly linear, wideband low noise amplifier (LNA). The LNA employs a three stage distributed topology along with input and output matching networks. The transistors have been biased in weak/moderate inversion to achieve better linearity. The post-layout simulation results for the proposed design presents a bandwidth of 0.1-1.9 GHz with an IIP3 of +3.8 dBm and input referred 1-dB CP of -7.72 dBm. The LNA achieves a power gain of 10 dB, NFmin of 4.4 dB and power consumption of 65 mW. With a supply voltage of 2 V, the design has been simulated in Cadence SpectreRF, using IBM 130 nm CMOS technology. The target is to achieve a wide band low noise amplifier that would suffice for multiple standards while offering high linearity.

Keywords—Complementary metal oxide semiconductor (CMOS), low noise amplifier (LNA), distributed topology (DA), Transmission lines, Cascode

I. INTRODUCTION With increased technological advancements, researchers

are now aiming to develop a single, multipurpose wireless terminal that incorporates numerous applications including phone, navigator, digital camera, video game console, web browser etc. This signifies the use for communication over various standards, so that several carrier frequencies may be acceptable to the front-end [1]. As a result, research in wide band LNAs prevails.

At the same time, the emergence of multiple applications has resulted in the incorporation of numerous standards within a limited frequency spectrum, as allocated by the authorities. This necessitates the requirement of highly linear low noise amplifiers at the front-end that would prevent the interferers from disrupting the carrier signal [2].

Some commonly used architectures for wideband LNAs reported in literature are the Shunt feedback, Common gate (CG) and Distributed topology [1][3][4]. Apart from suffering a tradeoff between bandwidth and noise figure, the shunt feedback topology requires a large open-loop bandwidth for achieving high linearity at higher frequencies [5]. However, the input capacitance of this architecture restricts the realization of a large bandwidth which in turn hinders the achievement of high linearity [6]. In the CG configuration, the input impedance is dependent on the transconductance of common gate transistor as well as the source impedance. The use of resistive degeneration offers wideband operation with

improved linearity but deteriorates gain, consumes voltage headroom and considerably increases noise figure. On the other hand, inductive degeneration would enhance linearity, but include a frequency dependent term in the input impedance of the CG configuration, thereby degrading the wideband operation [5].

Distributed topology is widely regarded as the suitable topology for the realization of wideband amplifiers with no ‘inherent’ linearity limitations. The basic architecture of distributed amplifier (DA) is presented in Fig.1. The DA avoids the usual gain bandwidth tradeoff by using transmission lines which absorb the parasitic capacitances of the transistor (the parasitic capacitances determine the upper-cutoff frequency) [7]. On the downside, distributed amplifiers exhibit high power consumption, increased noise figure and occupy a significant chip area. Low power versions of distributed LNAs are now available in the market [8]. The large area constraint can be disregarded because of their capability to achieve high linearity and large bandwidth due to wideband input and output impedance matching [4][7].

Based on the above discussion, we employ conventional wideband distributed architecture in our design and propose a design methodology to achieve good linearity performance. A few standards that have been targeted include UMTS, GSM and GPS. The proposed design fulfills the requirements of acceptable gain, low noise figure, wideband input and output matching, high linearity, low power dissipation, appropriate chip area and unconditional stability which are essential for an LNA.

The paper is organized as follows: Section II presents the design details of the proposed LNA. In Section III, layout design is discussed and Section IV describes the simulation results. The conclusion is presented in Section V.

Fig. 1. 4-Stage Distributed Amplifier

2013 IEEE Symposium on Wireless Technology and Applications (ISWTA), September 22-25, 2013, Kuching, Malaysia

978-1-4799-0156-2/13/$31.00 ©2013 IEEE 338

Fig. 2. Distributed LNA Schematic Design

II. DESIGN ANALYSIS The proposed LNA design is shown in Fig. 2. It employs

three stages, each in a cascode configuration. The cascode configuration allows independent input and output matching over a wide bandwidth since there is no direct coupling from the output to input. The improved reverse isolation also provides better circuit stability, while eliminating gain reduction due to Miller’s effect.

The DA is known to eliminate the regular gain-bandwidth limitation. However, unlike the multiplicative gain in a conventional cascaded amplifier, the DA gain is additive in nature [9]. Theoretically, it is assumed that a high gain can be achieved by increasing the number of stages infinitely [10]. However, as the input signal travels between the stages, increased delay and losses in the transmission lines limit the number of stages in practice. Thus a cascoded stage is an effective scheme for gain enhancement while also providing significant advantages as mentioned above.

The distributed architecture inherently suffers from high power dissipation [4]. A typical method of reducing power dissipation is to reduce the supply voltage (VDD). However, in our design, the gate voltages of transistors have been controlled to limit the power consumption. A MOS may be biased in weak, moderate or strong inversion. Biasing the transistor in weak or moderate inversion positively affects the linearity, hence improving the IIP3. At the same time it reduces the device transconductance which reduces drain current and hence dissipation [11]-[12]. The transistors in the proposed design are biased to operate in the weak/moderate inversion zone. The bias points have been precisely set to operate in the narrow region that allows an increased linearity by the cancellation of the third order non-linearity (which can ideally go down to zero) [13].

The linearity performance of the circuit is further enhanced by employing inductive degeneration which improves the

linearity by forming a negative feedback. An inductively degenerated cascode topology is assumed to give best noise performance that can be delivered by any architecture while also improving linearity [14]. Resistive degeneration is avoided since it causes dissipative power loss while also adversely affecting the noise figure.

Besides, transmission lines parameters (especially inductances) have been optimized, so that the forward travelling signal adds constructively at each stage.

III. LAYOUT DESIGN Fig. 3 shows the optimized layout of the distributed LNA.

The layout has been designed in Cadence Virtuoso Layout tool using 130 nm CMOS technology from IBM. Assura 1.8.0.2DM has been used for performing the physical verification checks. DRC, LVS and QRC checks have been successfully cleared by the LNA. Various parasitic effects were seen through QRC run. Therefore, careful layouting was employed to minimize the effects of these parasitics which could have significantly degraded the circuit performance.

The design occupies a chip area of 2.35x0.98 mm2 excluding bond pads. This area is comparable with various other reported designs of the distributed LNA.

IV. SIMULATION RESULTS The distributed LNA has been simulated in Cadence

SpectreRF using 130 nm CMOS technology from IBM. Transistor suitable for radio frequency applications was chosen. The widths were optimized to obtain good input and output impedance matching, reasonable gain, bandwidth etc. A width of 150 µm was selected for transistors T1-T5 whereas the width of transistor T6 was set to 200 µm. The gate voltages of transistors (VDC1 and VDC2) were chosen such that all transistors remain in saturation throughout the entire bandwidth while drawing minimum current. The transmission lines lengths are lower than 300 µm with minimum and

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maximum widths of 4 µm and 10 µm respectively. As shown in Fig. 4, the post layout simulation of the LNA presents a 3-dB bandwidth from 0.1 GHz to 1.9 GHz with a maximum gain of 9.7 dB. The input and output reflection coefficients S11 and S22 are well below -10 dB and -6 dB respectively, within the passband. VSWR is another parameter to give an insight of the impedance matching, especially while designing LNAs with low sensitivities [15]. The input VSWR for the worst case has been found to be < 1.78 while for the output it is < 2.8. This indicates that the percentage of transmitted power at the input is 92.1 % while that of the reflected power is 7.9 %. Similarly, at the output, around 80 % of the total incident power will be delivered to the load while 20% will be reflected. The Noise Figure is presented in Fig. 5. Minimum NF of 4.37 dB is achieved at 1.9 GHz. For the linearity analysis, two tone test was performed. Owing to the wideband nature of the LNA, two tones of 1.2 GHz and 1.21 GHz with a spacing of 10 MHz were chosen. The input power was swept from -40 dBm to 20 dBm. The LNA achieves a high IIP3 of +3.8 dBm as shown in Fig. 6. The linearity analysis of the LNA depicts 1dB-CP to be -7.72 dBm as shown in Fig.7. To determine the linear behavior of the LNA, PSS analysis was performed at randomly selected frequencies from 0.1-1.9 GHz. It was found that the LNA exhibits high linearity in the entire band of interest as shown in Fig. 8. For assuring the stability of the LNA, both Kf and B1f were simulated within and outside the desired band. It was found that the LNA remains unconditionally stable from 0.01 GHz to 10 GHz with Kf >1 and B1f <1, as presented in Fig. 9. The formula PDC = IDC ∗ VDD has been used for calculating the power dissipation. For core LNA, it has a value of 65 mW (32.5mA@2V). Table I summarizes the results discussed above.

A comparison of the post-layout simulation results of our proposed LNA with other state-of-the-art LNAs is presented in Table II. It is evident that our design possesses a substantially higher linearity (IIP3) compared to other wideband LNAs without any significant compromise on other parameters.

.

Fig. 3. Layout of the Distributed LNA Design

0 0.5 1 1.5 2

-60

-50

-40

-30

-20

-10

0

10

Frequency (GHz)

S-Pa

ram

eter

s (dB

)

S11 S12 S21 S22

Fig. 4. S-Parameters

0 0.5 1 1.5 24

4.5

5

5.5

6

6.5

7

Frequency (GHz)

Noi

se F

igur

e (d

B)

NF

Fig. 5. Noise Figure (NF)

-40 -30 -20 -10 0 10 20-120

-100

-80

-60

-40

-20

0

20

40

Input Power (dBm)

Out

put P

ower

(dB

m) IIP3 = +3.8 dBm

1dB/dB

3dB/dB

Fig. 6. Input Third Order Intercept Point (IIP3= +3.8 dBm)

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TABLE I. COMPARISON OF SINGLE-ENDED CMOS LNAS

* Measured results **Post-layout simulation results

-40 -30 -20 -10 0 10-35

-30

-25

-20

-15

-10

-5

0

5

10

Input Power (dB)

Out

put P

ower

(dB

)

1-dB CP = -7.72 dBm

Fig. 7. Input referred 1 dB Compression Point

(1dB-CP= -7.72 dB m)

0 0.5 1 1.5 2-8.2

-8

-7.8

-7.6

-7.4

-7.2

-7

-6.8

Frequency (GHz)

1dB

-CP

(dB

m)

1dB-CP

Fig. 8. 1dB-CP versus Frequency

0 2 4 6 8 100

200

400

600

800

Kf

Frequency (GHz)

0 2 4 6 8 100.2

0.4

0.6

0.8

1

B1f

Kf B1f

Fig. 9. Stability Factors Kf and B1f

TABLE II. SUMMARY OF RESULTS

S11 <-11 dB S21 (max) 9.7 dB

S22 <-6 dB Input referred

P1dB -7.72 dBm

IIP3 +3.8 dBm NF (min) 4.37 dB IDD@VDD 32.5mA@2V

Technology IBM 130 nm CMOS

Bandwidth 0.1-1.9 GHz

V. CONCLUSION In this paper, a complete design of a distributed low noise

amplifier with cascode gain cells is demonstrated. The LNA has achieved a bandwidth from 0.1-1.9 GHz and remains unconditionally stable up to 10 GHz. The negative feedback and the operation of transistors in weak/moderate inversion enabled the achievement of high linearity with an IIP3 of +3.8 dBm. The maximum gain in the passband is 9.7 dB.

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Tech nm

90 130 90 65 130

S11 dB <-5 <-10 <-10 <-10 <-11

S21 (max)

dB 12 19 10.6 NA 9.7

NF (min) dB 4 3 4 5.4 4.37

IIP3 dBm -16 1 -8 -10.5 +3.8

Power mW 18 12 8 1.5 65

BW GHz 0.3-2 0.1-

6.5 2.5-4 3.1-5 0.1-1.9

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