A 10 MHz BW 50 fJ/conv. Continuous Time Modulator with High-order Single Opamp Integrator using Optimization-based Design Method

Kazuo Matsukawa, Koji Obata, Yosuke Mitani, and Shiro Dosho

Panasonic Corporation

3-1-1 Yagumo-naka-machi, Moriguchi City, Osaka 570-8501

Introduction Recently, performances of ADCs are greatly improved.

Especially, FOM of low resolution ADCs such as SAR-type has been drastically reduced. However, it is rather difficult to improve FOM of high resolution ADCs like -type.

In this paper, we propose not only new power and area efficient circuit configurations but also an optimization design method for such configurations.

So far, design difficulties of the modulator, such as a trade-off between loop stability and a performance and unknown distortion mechanism, have been serious obstacles to improve the efficiency. Major factors to overcome these obstacles are new high-order single opamp integrators using optimization-based design method and tuning systems for harmonic distortions.

Two design examples for mobile application confirm that those design approach can maximize the performance of various types of modulators. A simple 3rd-order modulator achieved the FOM of 101 fJ/conv. and more complex 4th-order one achieved 50 fJ/conv. which is less than half of ever reported.

Modulator System Design Figure 1 shows the block diagram of the CT-ΔΣ Modulator

with tuning systems. Three calibration systems are embedded to keep the signal quality constant; the RC-constant calibration optimizes both cutoff frequency and zero position of the loopfilter, the opamp calibration minimizes the offset of the 1st integrator to suppress the 2nd harmonic distortion and the flash-ADC calibration suppresses quantization noise and harmonic distortions.

Filter Design for Efficient FOM Figure 2 illustrates the circuit configurations of the loopfilter.

So far, filter topologies are limited by the classical filter theory. In this paper, two types of new simple loopfilters are fabricated. Adaption of the loopfilters is power- and area-efficient way, but the technique to design has not been established.

One of the filters is a 3rd-order integrator with single opamp for mobile TV-tuners (Modulator-A), and the other is 4th-order one (Modulator-B) for wide-band mobile receivers. The former is suitable for narrower signal band with higher oversample rate and the latter is for wider signal band with lower oversample rate, respectively. Both filters use single opamp configuration to decrease the phase delay due to finite gain bandwidth of the opamp, which contributes to reduce the power consumption. In addition, the phase compensation techniques also contribute to the decrease of the power. The newly inserted phase compensation resistor and capacitor draw back the phase within stable region.

Design flow for Optimization

The issue to use these circuit configurations for the loopfilter is that we cannot choose all parameters in the transfer function of the loopfilter independently. It is very difficult to explore a

parameter set to maximize the design performance of the modulator by trial and error.

We have developed a new optimization flow as shown in Fig.3. The design flow is based on the simulated annealing, where the transfer function of the loopfilter with parasitic capacitances and a finite gain and bandwidth opamp model are used to determine the loop stability and SNR of the modulator. In addition, all PVT variations are taken into account for optimization. Figure 4 shows all poles of the loop corresponding to PVT conditions are within unit circle along with minimizing the in-band noise. The stability is analyzed in the z-domain by mapping the transfer function of the filter to it. We use zero-order-hold s-z transformation, because it keeps the step response of the loopfilter when NRZ-type DAC is used. As long as the step response is preserved, the loop stability is also preserved in the z-domain.

Reduction of Harmonic Distortion

Another issue to minimize the FOM is to decrease the harmonic distortions. We have already reported the major source of the harmonic distortion was the interaction of the DWA and the offset voltage of the 1st opamp [2]. We developed calibration system of the offset of the 1st opamp without any additional circuits. The offset is directly measured by the flash ADC through the bypass line in Fig.1. In addition, input referred offset in the flash-ADC, which is also the source of high order harmonic distortions, is minimized by the offset calibration.

Chip Fabrication and Measurement Result Mod.-A and Mod.-B were fabricated in 65nm and 40nm

CMOS processes, respectively. Figure 5 shows the FFT spectra of the output streams. Quantization noise spectra confirm that high order integrations are realized by the new filter topologies. The measured SNDR reaches to 68.6 dB (Mod.-A) and 70.0 dB (Mod.-B), respectively. Figure 6 also shows the effect of the calibrations in Mod.-B. Over 21dB improvement was achieved in the right graph with all calibration as compared with the left one without any calibrations. The calibration of the flash ADC improves both harmonic distortions and the noise floor. Remaining even order harmonic distortions are minmized by the opamp calibration. Figure 7(a) shows the SNR and SNDR against the input signal power (Mod.-B). The comparison of the measured performances with recent top five CT modulators [2,4-7] of efficient FOM is listed on the Table in Fig. 7. Our test chips achieved 50 fJ/conv. and 101 fJ/conv., respectively. The FOM of the Mod.-B is less than half of ever reported. The right figure in Fig.7 also compares the area, which confirms that our test chips are also area efficient. The results show that a new filter exploration with an efficient optimization tool is a very powerful way to develop high efficient ΔΣ modulators.

978-1-4673-0849-6/12/$31.00 ©2012 IEEE 2012 Symposium on VLSI Circuits Digest of Technical Papers 160

References

Imag

inar

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Fig. 4 Optimization results of NTFs and poles under PVT variations.

[1] K. Matsukawa, et al., “A 5th-order delta-sigma modulator with single-opamp resonator,” IEEE J. Solid-state circuits, vol.45, no.4, April 2010. [2] K. Matsukawa, et al., “A 69.8 dB SNDR 3rd-order continuous time delta-sigma modulator with an ultimate low power tuning system for a worldwide digital TV-receiver,” CICC, Sept. 2010. [3] A. Das, et al., “A 4th-order 86dB CT ADC with two amplifiers in 90nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 496–497, Feb. 2005. [4] J. Gealow, et al., “A 2.8 mW ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator,” Symp. VLSI, pp. 42-43, June 2011. [5] G. Mitteregger, et al., “A 14b 20 mW 640 MHz CMOSC ADC with 20 MHz signal bandwidth and 12b ENOB,” IEEE ISSCC Dig. Tech. Papers, pp. 131–140, Feb. 2006. [6] J. G. Kauffman, et al., “An 8 mW 50 MS/s CT modulator with 81 dB SFDR and digital background DAC linearization,” IEEE ISSCC Dig. Tech. Papers, pp. 472–473, Feb. 2011. [7] S-J. Huang, et al., “A 1.2V 2MHz BW 0.084 mm2 CT ADC with -97.7 dBc THD and 80 dB DR using low-latency DEM,” IEEE ISSCC Dig. Tech. Papers, pp. 172–173, Feb. 2009.

Frequency (Hz)

100k 1M 10M 100M

Frequency (Hz)

80dB/dec.

SFDR=79.6dB

SNDR = 70.0dBSNR = 70.6dB

100k 1M 10M 50M-140

-120

-100

-80

-60

-40

-20

0

Mag

nit

ud

e (d

B)

SFDR=81.3dB

SNDR = 68.8dBSNR = 69.3dB

60dB/dec.

(a) Modulator-A (b)Modulator-B Fig. 5 FFT spectrum.

FlashADC

OffsetCalib.

DigtalStream

AnalogInput

RC Const.Calib.

RelaxationOSC.

(Outside)

IntegrationPath

DWA

OffsetCalib.

DAC1 DAC2

PassiveAdder

1st Opamp Output

For Phase Comp.

Mag

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e (d

B)

Mag

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B)

Fig. 6 Effects of calibrations.

Fig. 1 Block diagram of modulator and tuning system.

(a)Modulator-A (b) Modulator-B Fig. 2 Circuit configuration of loopfilter.

-10

0

10

20

30

40

50

60

70

80

-80 -70 -60 -50 -40 -30 -20 -10 0 10

Input signal power (dBFS)

SN

R,

SN

DR

(d

B)

SNR

SNDR

VLSI2011[4] 40nm 0.085 2.80 78.0 83.0 1.92 246 112 171.4

ISSCC2006[5] 130nm 1.2 20.0 74.0 76.0 20 640 122 166.0

ISSCC2011[6] 90nm 0.15 8.0 63.5 70.0 25 500 125 164.9

ISSCC2009[7] 65nm 0.084 4.52 79.1 80.0 2 128 153 166.5

CICC2010[2] 65nm 0.16 3.6 69.8 70.2 4 140 178 160.7

Conference

Modulator-B

Technology

40nm

Area(mm2)

0.051

Power(mW)

2.57

SNDR(dB)

70.0

DR(dB)

70.6

BW(MHz)

10

Fs(MHz)

300

FOM(fJ/conv.)

50

FOM2

166.5

Modulator-A 65nm 0.060 1.36 68.8 69.3 3 186 101 162.0

Mod.-B

0.1

1

0 50 100 150 200

FOM (fJ/conv.)

Are

a (m

m2)

0.01

10

Mod.-A

[4] [7][6] [2]

[5]

This Work

Mod.-B

Fig. 7 Measured chip performance.

START

NTF(z) isAcceptable?

CoolingCriteria

TerminalCriteria

End

No

No

No

RC model with all parasitic caps.

Opamp model with DCgain & GBW

RandomizeParam.

Replace Param.

Circuit Eq. Gen.TFloopfilter(s)

Cooling

Circuit equation generation

BW

Minimize(Thermalnoise+Qnoise)

1

All Poles are within Unit Circle

Frequency (Hz)

Acceptance criteria

NTF

s-z transformation

Fig. 3 Developed design method.

215

um

Flas

h A

DC

Flas

h A

DC

200

um

(a)Modulator-A (b) Modulator-B Fig. 8 Chip layout.

978-1-4673-0849-6/12/$31.00 ©2012 IEEE 2012 Symposium on VLSI Circuits Digest of Technical Papers 161