Lowpass Delta-Sigma Modulator with DigitalUpconversion for Switching-Mode Power Amplifiers

Bjorn Thorsten Thiel, Alp Ozmert, Junqing Guan, Renato NegraMixed-Signal CMOS Circuits,

UMIC Research CentreRWTH Aachen University, D-52056 Aachen, Germany

thiel@umic.rwth-aachen.de

Abstract—This work presents a lowpass ∆Σ based

transmitter frontend suitable for software defined ra-

dios (SDRs). ∆Σ modulation is utilised to generate an

RF signal suitable for driving highly efficient switching-

mode power amplifiers. The whole transmitter frontend is

implemented in the digital domain up to the upconversion.

Thus, high reconfigurability and flexibility necessary for

SDR is achieved. This work presents two implementations

methods for lowpass ∆Σ modulator based transmitter

frontends for SDR applications. The circuit design in

a 90 nm CMOS process and a discrete implementation

utilising a field programmable gate array (FPGA) are

discussed. Feasibility of the concept is demonstrated by

simulation for the integrated implementation and by mea-

surements for the FPGA solution.

Index Terms—Field-programmable gate array (FPGA),

lowpass (LP) delta-sigma (DS), RF transmitter, software

defined radio (SDR).

I. INTRODUCTION

There are two conflicting demands on RF transmitterfrontends: on one hand a high degree of flexibility andon the other hand energy efficiency is desired. Theemerging trend towards software defined radios (SDRs)needs flexible and highly reconfigurable RF frontends inorder to dynamically exploite the entire asigned usablespectrum. Energy efficiency is essential in mobile hand-sets to increase battery life, as well as in base stations toreduce heat dissipation and thus the necessary cooling.Hence, using power efficient circuits will decrease thetotal cost for wireless communications.

One consequence of the growing importance of flexi-bility in wireless communication terminals is an increas-ing digitalisation of the RF front end. Digital signals arepushed further towards the antenna. The decreasing nodesizes of modern nanoscale CMOS processes favours thisdevelopment. Reconfigurability of digital-centric trans-mitters is easily achieved by changing digital settingslike filter coefficients or filter cores.

Quantiseru[n] y[n] v[n]

H1(z)−e[n] = d[n]

Fig. 1. Block diagram of a ∆Σ modulator.

This leads to the question: where to convert the signalfrom the digital to the analogue domain or how farcan the digital signal processing be pushed towards theantenna? A potential answer to this and also a possi-bility to satisfy the demand for high energy efficiency,are switching-mode power amplifiers (SMPAs). Theseamplifiers operates as switches and, thus, require a digitallike driving signal. By using SMPAs, digital one-bitsignals and related techniques can be employed almostup to the antenna.

There are various methods to generate a digital signalwhich can be converted back to the original analoguesignal by filtering. A simple approach is pulse-widthmodulation (PWM), which can be expanded to pulse-width and -position modulation to fit RF-requirementsfor high frequencies. This is even implementable com-pletely in the digital domain as shown in [1]. One possi-bility to implement PWM is a first order ∆Σ modulator(∆ΣM) [2]. ∆Σ modulation allows to transform ananalogue or multilevel signal into a single bit streamwhile reducing the inband quantisation noise throughnoise shaping [3].

II. ∆Σ MODULATOR TOPOLOGIES

The main concept of ∆ΣM is to shift quantisationnoise out of the used band to far-off frequencies. Thereto,the error signal e in Fig. 1 between the quantiser inputy and output v is calculated and after application of a

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FilterInterp.

FilterInterp.

PA

I

Q

DSP

2fc

LP ∆Σ

LP ∆Σ

Fig. 2. Block diagram of the proposed lowpass ∆Σ modulatortransmitter frontend.

filter H(z) fed back to the input of the modulator. Theused filter H(z) determines in which frequency area thenoise is shifted. Furthermore, the order of H(z) definesthe order of the ∆Σ modulator. To fulfil typical spectralmasks it is necessary to suppress this shifted noise withhigh quality factor filters at RF.

Three main topologies of ∆ΣM can be distinguished,lowpass, highpass and bandpass ∆ΣM. The three dif-ferent ∆Σ topologies have – when applied to gigahertztransmitters – some issues which have to be considered.Bandpass ∆ΣM operates with frequencies above the car-rier frequency [4], [5]. Furthermore, multiple switchingoperations during one carrier period are necessary. Thus,this topology is not well suited for gigahertz applicationsdue to high speed requirements leading to significantpower consumption. Also highpass ∆ΣM needs oper-ation frequencies which are at least twice as high as thedesired carrier frequency [6]. In contrast to this lowpass∆ΣM (LP∆ΣM) can operate with frequencies lowerthan the carrier frequency. Hence, a LP∆ΣM is imple-mentable with most standard digital processes or even onan FPGA. The low oversampling of LP∆ΣMs howeverleads to higher out-of-band noise, which lays closer tothe wanted signal – especially for larger bandwidths [7].

III. PROPOSED LOWPASS ∆Σ TOPOLOGY

The presented LP∆ΣM topology, sketched in Fig. 2,is a digital quadrature transmitter frontend. A lowpassapproach was chosen to relax speed requirements on the∆ΣM and allow implementation on a slower digital plat-forms like an FPGAs. Thus, oversampling, ∆Σ modula-tion, and upconversion are implemented, on the FPGA.Additionally, a simplified OFDM signal generator wasadded to generate a sample stimulus. The generateddigital baseband (BB) in-phase (I) and quadrature (Q)signals are modulated to one-bit streams by individual∆Σ modulators. Thereafter, these two streams are first

upconverted by inserting the inverted signal for a halfcarrier period. These two RF streams are then combinedby interleaving with the double carrier frequency result-ing in an IQIQ stream. This operation reflects analoguemixing with two 90◦ phase shifted sinusoids in the digitaldomain. The resulting RF signal can now be amplifiedby a SMPA and converted back to the analogue domainthrough passive bandpass filtering.

IV. IMPLEMENTATION

A. Baseband Processing on FPGA

The signal generation block and the ∆ΣM are im-plemented on an FPGA. Upconversion and interleavingare implemented on a special designed break-out boardutilising off-the-shelf multiplexer (MUX) integrated cir-cuits (ICs).

The sample signal generator generates a broadbandsignal comparable to orthogonal frequency-division mul-tiplexing (OFDM) and single-carrier frequency-divisionmultiple access (SC-FDMA). First a pseudo random datastream is generated using a 24 bit linear feedback shiftregister. This stream is modulated with 16QAM using alook up table. The output symbols of the prior blocks aremapped to sub-carriers. These blocks are implemented asa behaviour description in VHDL. Thereafter, the sub-carriers are transferred to the according offset by aninverse Fast Fourier Transformation (iFFT).

Prior to ∆ΣM, both I and Q signal are oversampledand filtered, to avoid aliases. The oversampling is doneby repeating the sample for four times. The resultingaliases are filtered by a five stage cascaded integratorcomb (CIC) filter which supplies notches at the positionsof the aliases. The iFFT and interpolation are imple-mented using intellectual property (IP)-cores of the usedFPGA design suite.

Thereafter, the ∆ΣM is applied. Thus, a one-bit datastream is generated out of the input signal. The utilisedarchitecture is a second order cascade-of-integratorsfeedback (CIFB) form ∆ΣM. For the given oversam-pling rate of four times, higher ∆ΣM orders than twooffer no significant improvement. The advantage of theCIFB topology is its simple implementation with goodstability. This modulator is also implemented in VHDL.For fast processing all coefficients are factors of 2n.

Clock signals where supplied by an external clock toallow synchronous operation with the carrier frequency.The oversampling ratio and the four times higher clockfrequency for the interpolation and ∆ΣM were achievedby an internal phase lock loop (PLL) circuit of theFPGA.

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Mux

Mux

Mux

Φ2fc

Φfc

sq

fc

si

fc 2fc

2fc

g

4fc

(a) Schematic (b) Layout

Fig. 3. I/Q upconversion of the two LP∆Σ modulated bit streams.

Φfc

Φfc

Φfc Φ2fc

Φfc

Φfc Φ2fc

Φ2fc

Switching

sq

sq

si

si

Inputlogicbuffers

g

Outputbuffer

Fig. 4. Schematic diagram of the described transmission gateupconverter in 90 nm CMOS.

B. Upconversion and interleaving

The single-bit I and Q baseband streams are led outof the FPGA as current mode logic signals to a breakout board. Additionally to the signal, an inverted signal isalso lead out. Thus, the upsampling is done by switchingbetween the signal and its inverted version. A two-to-one current mode logic MUX circuit [8] driven with thecarrier frequency is used for I ,I and Q,Q, respectively.The output signal of both MUXs are combined andinterleaved with a third identical MUX. This MUXis driven with twice the carrier frequency (Fig. 3(a)).Finally, the RF signal is differentially fed to two SMAconnectors for measurement or connection to an externalPA module. All signal lines are designed as microstriptransmission lines (Fig. 3(b)) and verified through electromagnetic field simulations.

V. SIMULATIONS

To explore the concept, a system model was createdfor the whole transmitter frontend. All digital parts wheresimulated and verified with behavioural VHDL models.The analogue part was first designed on transistor levelin an 90 nm CMOS technology. As an example for anintegrated implementation, including ∆ΣM and MUXon-chip, a transmission gate topology for upconversionand interleaving was implemented, see Fig. 4. Whiledigital parts where simulated in an event-driven digitalsimulator the analogue blocks where simulated with aspectre-like analogue simulator. Both blocks were simu-lated together in a mixed-mode simulation.

For observation of the internal behaviour the complexsingle-sideband sinusoid signal in Fig. 5(a) was used.The stimulus signal and spectra of the output signals ofeach block are shown in Fig. 5. In Fig. 5(b) the noiseshaping behaviour of the ∆ΣM is clearly visible. Dueto the single tone stimulus the noise has no continuousshape but appears as spurs. The average level of the spursincreases with increasing frequency, as expected for aLP∆ΣM. In Fig. 5(c) the upconverted signal is visible atthe carrier frequency of fc = 2.5 GHz. Images of it canbe seen at 0.5fc and 1.5fc. In simulations a later ∆ΣMoperation frequency of 833 MHz was assumed, whichis feasible for the chosen 90 nm technology process.The high noise at far-off frequencies demands a highlyselective reconstruction filter.

VI. MEASUREMENT

The operation of the LP∆ΣM transmitter concept wasverified trough measurements on an FPGA implementa-tion as described in Sec. IV. Due to the limited speedof the FPGA the operation of the ∆ΣM was reducedto 277 MHz while the carrier frequency of 2.5 GHzwas kept. Thus, the operation frequency of the signalgeneration and the external clock supply for the FPGAwere set to 79 MHz. The first clock signal for upconver-sion was connected to a 2.5 GHz oscillator, the secondfor interleaving to a synchronous 5 GHz oscillator. Thedifferential output was combined and measured using aspectrum analyser.

The reduced frequency of the ∆ΣM explains theincreased number of aliases in Fig. 6(a) compared toFig. 5(c). In Fig. 6(b) the noise shaping can be observed.In contrast to Fig. 5(b) the noise is continuous due to thecomplex input signal. Comparison with Fig. 5(c) showsthat the selectiveness of the reconstruction filter at RFwill be more relaxed for a higher operation frequency ofthe ∆ΣM.

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0 25 50 75 100t[ns]

−1

0

1

(a) Stimulus

0 0.125 0.25 0.375 0.5 0.625f [GHz]

−50

−40

−30

−20

−10

0

dBFS

(b) Output of the ∆ΣM in the I path

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5f [GHz]

−50

−40

−30

−20

−10

0

dBFS

(c) Upconverted and interleaved signal

Fig. 5. Mixed-mode system simulation results of the designed LP∆ΣM transmitter in 90 nm CMOS.

(a) Wideband spectrum (DC—2fc) (b) Close-up spectrum around fc

Fig. 6. Measurement results on a LP∆ΣM transmitter implemented in a rapid prototyping environment (16QAM OFDM signal).

VII. CONCLUSION

A topology of a fully digital lowpass ∆Σ modulatortransmitter frontend is presented. An integrated imple-mentation of the concept was verified by system andtransistor level simulations. The operation of the conceptwas demonstrated using a concrete implementation. Thisimplementation utilises a field programmable gate arrayand off-the-shelf multiplexer ICs. For this implementa-tion the performance is degraded due to the lower opera-tional speed compared to the integrated implementationpresented in simulations. In both implementations thecarrier frequency can be varied in a large range and isonly limited by the interleaving multiplexer.

Thus, this transmitter topology can easily cover mul-tiple bands using a tuneable or multiband switching-mode power amplifier or multiple SMPAs tuned todifferent bands. The presented concept is suitable fordriving switching-mode amplifiers in an multistandardand multiband software defined radio environment.

ACKNOWLEDGEMENT

This work has been funded by the ‘Ultra-high speedMobile Information and Communication’ (UMIC) Re-search Center.

REFERENCES

[1] B. Thiel, S. Dietrich, N. Zimmermann, and R. Negra, “Sys-tem architecture of an all-digital GHz transmitter using pulse-width/position-modulation for switching-mode PAs,” in Proc.IEEE Asia-Pacific Microw. Conf., 2009, pp. 2340 –2343.

[2] J. Keyzer et al., “Generation of RF pulsewidth modulated mi-crowave signals using delta-sigma modulation,” in IEEE MTT-SInt. Microw. Symp. Dig., vol. 1, 2002, pp. 397–400.

[3] R. Schreier, G. Temes, and Institute of Electrical and ElectronicsEngineers, Understanding delta-sigma data converters. IEEEpress Piscataway, NJ, 2005.

[4] J. Rode, J. Hinrichs, and P. Asbeck, “Transmitter architectureusing digital generation of RF signals,” in Proc. IEEE Radioand Wireless Conf., Aug. 2003, pp. 245–248.

[5] J. Keyzer et al., “Digital generation of RF signals for wirelesscommunications with band-pass delta-sigma modulation,” inIEEE MTT-S Int. Microw. Symp. Dig., vol. 3, 2001, pp. 2127–2130 vol.3.

[6] S. Ralph and R. Farrell, “Using high pass sigma-delta modulationfor class-S power amplifiers,” in Proc. IEEE European Conf.Circuit Theory and Design, Aug. 2007, pp. 707–710.

[7] M. Helaoui, S. Hatami, R. Negra, and F. Ghannouchi, “Anovel architecture of delta-sigma modulator enabling all-digitalmultiband multistandard RF transmitters design,” IEEE Trans.Circuits Syst. II, vol. 55, no. 11, pp. 1129–1133, Nov. 2008.

[8] “NB7L86M data sheet,” ON Semiconductor, P.O. Box 5163,Denver, Colorado 80217 USA, Aug. 2009.

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