A GSM/EDGE Transmitter in 0.13-μm CMOS Using Offset Phase Locked Loop and Direct Conversion Architecture

S. F. Chen, Y. B. Lee, Bosen Tzeng, C. C. Tang, Charles Chiu, Rickey Yu, Ovid Lin, L. W. Ke, C. P. Wu, C. W. Yeh, P. Y. Chen, G. K. Dehng

MediaTek Inc., No. 1, Dusing Rd. 1, Hsinchu Science Park, Hsinchu, Taiwan 300, R.O.C.

Abstract — A GSM/EDGE transmitter implemented in

0.13-μm CMOS using offset phase locked loop and direct conversion architecture is presented. The transmitter consists of a DCT, an OPLL with a TXVCO, a fractional-N synthesizer with a RFVCO and LDO regulators. The transmitter delivers 1.5dBm output power with 1.2o rms phase error and the modulation spectrum at 400kHz offset is better than -62dBc in high band GSM mode. In high band EDGE mode, it has maximum 4dBm output power with 0.5dB gain step per bit for 36dB dynamic range and 2% rms error vector magnitude. The current consumption of high band is 171mA at GSM mode and 169mA at EDGE mode under proper output power level for PA. This chip is housed in a 56-pin QFN package.

Index Terms — DCT, OPLL, GSM, EDGE, Transceiver, VCO, CMOS, Divider, Modulator, PGA.

I. INTRODUCTION

Nowadays most GSM transmitters (TX) adopt offset phase locked loop (OPLL) architecture because this architecture doesn’t need the TX SAW filter [1]-[3]. The output noise floor is dominant by the transmit voltage controlled oscillator (TXVCO) and it also can be shaped by the frequency response of the LC tank. The main drawback of the OPLL is the spurious problem. With a careful frequency plan, this can be avoided. To pass the out-band-noise specification with 3dB margin, 165dBc/Hz carrier over noise (C/N) at 20MHz offset is required at the transmitter’s output as equation (1). However, it is a big challenge for the direct conversion transmitter (DCT). Regarding of the noise issue, DCT has some advantages over OPLL, such as less circuit complexity, simpler frequency plan and support of non-constant envelope modulation scheme. With these advantages, DCT becomes more popular in 3G application. Because OPLL can only support the constant envelope modulation scheme, some EDGE radio frequency (RF) transceiver manufactures use the polar architecture to support the EDGE application. The large signal polar transmitter also has some challenges, for examples: delay mismatch issue between the amplitude and phase paths and necessity of a customized power amplifier (PA) [4]. Therefore, an OPLL combined with

DCT architecture is the one which takes the advantage between them. The block diagram of the OPLL/DCT transmitter is shown in Fig. 1.

HzdBcNC /1653)10log(10)79(33/ 5 =+⋅+−−= (1)

Fig. 1. Block diagram of the OPLL/DCT transmitter.

II. OFFSET PHASE LOCKED LOOP TRANSMITTER

OPLL is based on a frequency translation loop. It consists of an IF I/Q modulator, filters, a dual mode phase frequency detector (PFD), a low-noise TXVCO, frequency dividers, a poly-phase RC phase shifter, a reference phase locked RFVCO and an offset mixer. The baseband modulation signal enters the IF I/Q modulator and is up-converted to the carrier frequency by the translation loop.

The close-in and unwanted spurs must be taken into consideration in the frequency plan. To get rid of close-in spur such as fractional spur is achieved by changing the dividing ratio of the frequency divider. If fractional spurs of the phase locked RFVCO fall into 2MHz range, the default divider setting will be switched to another, keeping the spurs away from the carrier frequency.

In order to minimize the chip area, a TXVCO combined with the frequency divider is adopted instead of two oscillators for quad band applications. In GSM850 and GSM900 bands, the output of TXVCO enters a low noise divider divided by four and an RF programmable gain amplifier (PGA) of DCT to ensure good out-of-band C/N performance. In DCS1800 and PCS1900 bands, the output of TXVCO passes through DCT high band (HB) chain and the I/Q modulator operates as an amplifier.

TXVCO

PD&CP

LoopFilter

1/D1 or1/D2

RFVCO

LPF2

IFIQ-MOD

HBIQ-MOD

RFPGA

1/2

RFPGA

LB

HBPPRC

LPFDIV

LBIQ-MOD

VCC: 2.8V

VCC: 1.5V1/4 1/4

1 or1/2

Cap.Divider

LPF1

1

IQ

DCTOPLL

1/2

978-1-4244-1808-4/978-1-4244-1809-1/08/$25.00 © 2008 IEEE 2008 IEEE Radio Frequency Integrated Circuits Symposium

RTUIF-02

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A. Low noise divider

The low noise divide-by-four circuit consists of two divide-by-two circuits and input/output inverter buffers, as shown in Fig. 2. The divide-by-two circuit consists of inverter based dynamic latches. With the advanced process, the operation frequency of the divider can reach 4.8GHz over process and temperature variations in post-simulation. Fig. 2. The low noise divide-by-four circuit.

B. TXVCO

TXVCO consists of a NMOS cross coupled pair, the LC tank, varactors and 7-bits switch capacitor array (SCA). In order to ensure good C/N and device reliability, higher than 1.5-V supply voltage and non-minimum channel length devices for the cross coupled pair are chosen. The output buffer uses 1.5-V supply voltage and is AC coupled from TXVCO core circuit.

C. OPLL locking process

The procedure to complete OPLL locking is sub-band calibration for 35uS first, entering frequency acquisition with dual mode PFD for 15uS and finally phase locked with analog phase detector (APD) only [5]. The digital PFD helps to accelerate the pull-in time effectively while the APD helps to sustain closed-loop operations with low-noise performance. In order to maintain a constant loop bandwidth, Kvco variation is minimized in the TXVCO design by the combination of varactor arrays for different sub-band groups, as shown in Fig. 3. Fig. 3. Differential varactor arrays of TXVCO.

III. DIRECT CONVERSION TRANSMITTER

DCT converts the baseband signal directly to carrier frequency. It consists of I/Q modulators, frequency dividers and RF PGAs. The frequency plan of the local oscillator (LO) is chosen by the dividing ratio of frequency dividers. The dividing ratio is chosen at four in GSM850 and GSM900 bands and two in DCS1800 and PCS1900 bands, respectively. Even the VCO frequency differs from the RF output frequency, it might still suffer pulling effect because the RF transceiver and the PA will generate harmonics, especially 2nd and 4th terms. To relieve the pulling effect, increasing the loop bandwidth of the LO PLL is one of the methods to approach [6]. In EDGE mode, the OPLL operates as the LO of DCT. Since the loop bandwidth of the OPLL is around 1.2~1.5MHz, the pulling effect is minimized.

A. I/Q Modulator

The I/Q modulator consists of a voltage to current (V/I) converter, switch quad devices and the LC tank load, as shown in Fig. 4. The V/I converter which uses an OPAMP feedback architecture makes the input AC signal voltage be tracked on the degeneration resistor. Therefore, the output AC current is quite linear. However, the C/N is also important in EDGE mode. The C/N of the IF gm cell is improved by adding an RC filter and the LO chain noise is also improved by increasing the slew rate of LO signal. The LC tank adds more rejection on the 3rd harmonic for reducing reciprocal mixing. Fig. 4. I/Q modulator. (Only I path is shown here.)

B. Frequency divider

The frequency divider consists of D latches. The divide-by-two and the buffer between TXVCO and the divider are shown in Fig. 5. To improve C/N, the frequency divider removes the tail current. The first stage of the buffer provides the gain stage and the second stage provides good driving capability to the divider.

1/2

1/2

(Dummy)

To LB PGAFrom VCO

(Dummy)

INV INV

INV

INV

INV

INV

IB I LOI

LOIB

TXVCO subband

Subband

2n+2-1(111) (110) (101) (100)

var3

var2

var1

plus mins

vref

EN

EN

vtune

0.7vVtune

plus mins

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Vref2

AMOS AMOS

AMOS AMOStuningcapacitanceunit

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2n+1+2n-1

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2n+1-1

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2n-1

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0

subband

Subband

2n+2-1(111) (110) (101) (100)

var3var3

var2

var1

plus mins

vref

EN

EN

vtune

0.7vVtune

plus mins

Vref1

Vref2

AMOS AMOS

AMOS AMOStuningcapacitanceunit

Subband

2n+1+2n-1

Subband

2n+1-1

Subband

2n-1

Subband

0

582

(a)

(b) Fig. 5. (a) The divide-by-two circuit. (b) The buffer between TXVCO and the divider.

C. RF PGA

The RF PGA consists of several gm cells and current steering pairs. Through the proper combination of gm cells and the output current path, the gain can be programmable with 0.5dB gain step per bit for 36dB dynamic range. The output signal is converted from differential to signal ended with an on chip balun. The output matching network is also embedded into the chip to reduce the external components.

IV. OPLL/DCT COMBINATION

In order to ensure the proper operation of OPLL/DCT between different modes, some switch and power down circuits should be taken into consideration. In HB GSM mode, the I/Q modulator of DCT performs as a fixed gain amplifier, as shown in Fig. 6. The RF PGA is programmed in a fixed gain with proper output power which is suitable for the input power requirement of PA. The feedback signal of TXVCO is through dividers of DCT. In EDGE mode, baseband modulation signal enters the I/Q modulator of DCT and the IF I/Q modulator of OPLL is switched as a fixed gain amplifier. Fig. 6. I/Q modulator with control switch. (Only I path is shown here.)

V. MEASUREMENT RESULT

The chip is fabricated in a 0.13-μm CMOS process and housed in a 56-pin QFN package. Its chip microphotograph is shown in Fig. 7. The die size is 14.7mm2 and OPLL/DCT including RFVCO and synthesizer occupies 47% chip area.

The measured GSM900 GMSK modulation spectrum is shown in Fig. 8 and PCS1900 8PSK modulation spectrum is shown in Fig. 9. The 20MHz offset out-of-band noise has passed the specification with 3dB margin for GSM900 at maximum output power level, as shown in Fig. 10. The measured rms phase error in all bands is less than 1.2 degree and PCS1900 rms error vector magnitude (EVM) is less than 2%, as shown in Fig. 11. Besides, the maximum output power of both modes is larger than 4dBm. Fig. 7. The chip microphotograph.

VI. CONCLUSION

In this paper, a highly integrated RF transmitter for the quad-band GSM/EDGE applications is presented. The transmitter uses the OPLL architecture in GSM mode and the DCT architecture in EDGE mode. It can meet the specification. Table I summarizes the transmitter performance with the suitable power level requirement for PA.

ACKNOWLEDGEMENT

The authors would like to acknowledge MTK/ACD division for the assistance and support of the chip layout.

Latch 1D

DB

Q

QB

Latch 2D

DB

Q

QBCLK

INB

OUT

OUTB

CLK

IN

From TXVCO

To divider

IB I LOI

LOIB

GSM ON

GSM ON

EDGE ON

EDGE ON

583

Ref Lvl

0 dBm

Ref Lvl

0 dBm

A

RF Att 10 dB

1AP

Unit dBm

RBW 30 kHz

VBW 100 Hz

SWT 3.4 s

Center 914.8 MHz Span 4 MHz400 kHz/

-90

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Delta 1 [T1]

-67.02 dB

400.00000000 kHz

1 [T1] -5.04 dBm

914.80400802 MHz

1 [T1] -67.02 dB

400.00000000 kHz

2 [T1] -67.41 dB

-400.00000000 kHz

3 [T1] -71.08 dB

1.20000000 MHz

4 [T1] -75.34 dB

1.80000000 MHz

Date: 29.FEB.2008 10:03:35

Fig. 8. The GSM900 modulation spectrum at GSM mode.

Ref Lvl

0 dBm

Ref Lvl

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RF Att 10 dB

1AP

Unit dBm

Center 1.9098064 GHz Span 4 MHz400 kHz/

RBW 30 kHz

VBW 100 Hz

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1.90981041 GHz

1 [T1] -63.47 dB

400.00000000 kHz

2 [T1] -63.11 dB

-400.00000000 kHz

3 [T1] -70.46 dB

1.20000000 MHz

4 [T1] -74.06 dB

1.80000000 MHz

Date: 29.FEB.2008 09:57:56

Fig. 9. The PCS1900 modulation spectrum at EDGE mode.

Fig. 10. The GSM900 out-of-band noise at GSM mode.

%

Vector Error

Magnitude

Standard EDGE

MAG

T1

A

Symbol/Errors

Standard EDGE

B

Ref Lvl

0 dBm

Ref Lvl

0 dBm

Ref Lvl

0 dBm

Ref Lvl

0 dBm

0 147.75SYMBOLS

CF 1.9098064 GHz

SR 270.833 kHz

CF 1.9098064 GHz

SR 270.833 kHz

0

20

Symbol Table

0 01110001 11011010 00110001 11111001 10011110

40 11011111 01100111 00111111 10001000 11110101

80 11011000 00010000 10111101 01110110 00110111

Error Summary

Error Vector Mag 1.40 % rms 4.55 % Pk at sym 128

Magnitude Error 0.53 % rms -1.63 % Pk at sym 128

Phase Error 1.37 deg rms -13.50 deg Pk at sym 125

Freq Error 97.70 Hz 97.70 Hz Pk

Amplitude Droop 6.71 dB/sym Rho Factor 0.9998

IQ Offset 0.13 % IQ Imbalance 1.04 %

TS1TS2

Date: 29.FEB.2008 09:54:55

Fig. 11. The PCS1900 EVM performance at EDGE mode.

TABLE I PERFORMANCE SUMMARY

Technology 0.13-μm CMOS Package 56-pin QFN Supply voltage (V) 1.5 & 2.8 Operation mode GSM EDGE Icc (mA) 182/182/171/171 187/187/169/169 Output power (dBm) 2.6/2.6/1.5/1.5 -1.5/-1.5/-3.5/-3.5 Output spectrum at 400kHz offset (dBc)

-67/-66/-63/-62 -65.5/-65/-63/-62

RMS phase error (o) 0.9/0.9/1.2/1.2 - Peak phase error (o) 3/3/4/4 - RMS EVM (%) - 1.4/1.4/2/2 Peak EVM (%) - 4/4/7/7 Original offset suppression (dBc)

- -50/-50/-50/-50

C/N at 20MHz offset (dBc/Hz)

165/164/159/157 162/161/158/157

* All numbers are listed in 850/900/1800/1900MHz order.

REFERENCES

[1] T. Yamawaki et al., “A 2.7-V GSM RF transceiver IC” IEEE J. Solid-State Circuits, pp. 2089-2096, vol. 32, no. 12, Dec. 1997.

[2] J. M. Hsu, “A 0.18-um CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter,” IEEE J. Solid-State Circuits, pp. 603-613, vol. 38, no. 4, Apr. 2003.

[3] O. E. Erdogan et al, “A single-chip quad-band GSM/GPRS transceiver in 0.18um standard CMOS,” in ISSCC Dig. of Tech. Papers, pp. 318-319, 2005.

[4] K. Konanur, “CMOS RF transceiver chip tackles multiband 3.5G radio system,” RF Design, pp. 22-30, Apr. 2006.

[5] G. K. Dehng et al, “A single-chip RF transceiver for quad-band GSM/GPRS application” IEEE RFIC Symp., pp. 427-430, June 2004.

[6] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, pp. 1415-1424, vol. 39, no. 9, Sept. 2004.

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