IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 6, JUNE 2006 479

Gate-First Germanium nMOSFET With CVD HfO2

Gate Dielectric and Silicon Surface PassivationNan Wu, Qingchun Zhang, D. S. H. Chan, Senior Member, IEEE, N. Balasubramanian, Member, IEEE,

and Chunxiang Zhu, Member, IEEE

Abstract—A gate-first self-aligned Ge n-channel MOSFET(nMOSFET) with chemical vapor deposited (CVD) high-κ gatedielectric HfO2 was demonstrated. By tuning the thickness ofthe ultrathin silicon-passivation layer on top of the germanium,it is found that increasing the silicon thickness helps to reducethe hysteresis, fixed charge in the gate dielectric, and interfacetrap density at the oxide/semiconductor interface. About 61%improvement in peak electron mobility of the Ge nMOSFET witha thick silicon-passivation layer over the CVD HfO2/Si systemwas achieved.

Index Terms—Chemical vapor deposited (CVD), germanium(Ge), HfO2, high-κ, MOSFET, surface passivation.

I. INTRODUCTION

IN ORDER to increase drive currents of MOSFETs formodern very large scale integration (VLSI) [1], there have

been intensive interests of using germanium as channel materialrecently, because germanium can potentially provide highercarrier mobility than silicon. In this application, one of thetechnical challenges is to form a high-quality gate stack ongermanium crystal. Using high-κ as gate dielectrics on ger-manium is attractive due to the poor electrical property ofthermal germanium oxide and the increasing requirement ofgate capacitance according to The International TechnologyRoadmap for Semiconductors (ITRS) [1]. In such a case, chem-ical vapor deposited (CVD) high-κ is preferable to physicalvapor deposited (PVD) high-κ due to its good repeatability,uniformity, and purity, etc. Germanium p-channel MOSFETswith CVD high-κ gate dielectrics have been successfullydemonstrated recently with enhanced hole mobility [2], [3],whereas for Ge nMOSFETs, the high electron mobility wasonly demonstrated using PVD high-κ gate dielectrics [4]. Sofar, Ge n-channel MOSFETs (nMOSFETS) with CVD high-κare with very limited electron mobility [2], [5], [6]. In thisletter, germanium nMOSFETS with much improved electronmobility is successfully demonstrated using CVD HfO2 as thegate dielectric and silicon surface-passivation technique [7].In addition to the improvement of gate leakage performance

Manuscript received January 16, 2006. This work was supported by theSingapore ASTAR under Grant R-263-000-267-305. The review of this letterwas arranged by Editor M. Ostling.

N. Wu, Q. Zhang, D. S. H. Chan, and C. Zhu are with the Silicon NanoDevice Laboratory, Department of Electrical and Computer Engineering,National University of Singapore, Singapore 119260 (e-mail: elezhucx@nus.edu.sg).

N. Balasubramanian is with the Institute of Microelectronics, Singapore117685.

Digital Object Identifier 10.1109/LED.2006.874209

[2], [3], [5]–[7], surface passivation is found vital for properoperation of the Ge nMOSFET.

II. EXPERIMENT

A conventional gate-first self-aligned process sequence wasemployed for the MOSFET fabrication. The starting Ge wafers(100) were Ga-doped p-type wafers (ρ = 0.16−0.27 Ω · cm).The wafers were subject to the silicon surface passivation byannealing in SiH4 ambient right after dilute HF cleaning [7].The ultrathin silicon layer on the germanium surface was oxi-dized during the subsequent in situ MOCVD HfO2 depositionand contributed to the HfSiOx interfacial layer (IL) of the gatedielectric between the HfO2 and the germanium. Two differentSiH4 surface passivation durations were employed: one with athin silicon layer and the other with a thick silicon layer. Thethicknesses, measured by X-ray photoelectron spectroscopy(XPS), are ∼ 0.38 and ∼ 0.48 nm for the thin and the thicksilicon layer, respectively. After that, postdeposition annealing(PDA) was performed in a rapid thermal processor at 500 C. A150-nm layer of TaN as the gate electrode was then reactivelysputtered at room temperature and patterned using conventionallithography and dry etching. A 100-Å e-beam SiO2 was thendeposited. Following that, phosphorus was implanted with adose of 1 × 1015 cm−2 (50 keV). The dopant activation wasperformed at 450 C using rapid thermal annealing (RTA).After forming gas annealing at 350 C, contact metal (Al–Si)was deposited and patterned. An HfO2/Si control sample withsimilar equivalent oxide thickness (EOT) was fabricated in thesame sequence but with higher PDA and source/drain (S/D)activation annealing temperatures.

III. RESULTS AND DISCUSSION

The silicon layer works in such a manner that it is consumedto form an IL before the germanium underneath is oxidized.Fig. 1 shows the Ge 2p3 and Si 2p XPS spectra collected fromthe monitoring sample with thick silicon and HfO2 deposition.The observation of the elemental chemical state of germaniumindicates the oxide/semiconductor interface is under analy-sis. Silicon is fully consumed as only an Si–O peak is ob-served, which also leads to additional oxidation of germanium(Ge–O peak).

Fig. 2 shows the capacitance–voltage (C–V ) characteristicsof Ge nMOSFETSs fabricated with the two different silicon-passivation conditions. The EOTs of the devices are 13 Å withquantum-mechanics correction. From Fig. 2, no “kink” in theaccumulation region for all the curves can be observed, which

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480 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 6, JUNE 2006

Fig. 1. Ge 2p3 and Si 2p core-level XPS spectra were taken from the samplewith thick silicon and HfO2 deposition. The full consumption of the siliconinterlayer is confirmed.

Fig. 2. C–V characteristics of the Ge nMOSFETs with silicon surfacepassivation and MOCVD HfO2. The devices were fabricated with differentamounts of the silicon interlayer.

also implies that the silicon layer is oxidized and contributedto the IL, and the MOSFETs are surface channel devices.Besides, it is also observed that there is a positive shift ofthe curves with thin silicon passivation, suggesting that thereis a significant negative fixed charge (∼ 3.82 × 1012 cm−2) inthe gate dielectric. Such a Vfb shift is possibly due to the Geoutdiffusion from the substrate into the gate dielectric duringthe thermal process (deposition, PDA, S/D anneal) [7]–[9]. ThisGe outdiffusion is dependent on the amount of germaniumoxide in contact with HfO2 at the interface [8]. Therefore,a thicker silicon layer could reduce the Ge outdiffusion [7]significantly in two ways: 1) reducing the amount of germa-nium oxide and 2) separating HfO2 from germanium oxide bya silicatelike IL. Consequently, a less positive Vfb shift canbe observed, as shown in Fig. 2. Moreover, it is found thatthe large hysteresis (121 mV) of the device with thin silicon

Fig. 3. (a) Id–Vd and (b) Id–Vg characteristics of the Ge nMOSFETs withsilicon surface passivation and CVD HfO2. The device with a thicker siliconinterlayer yields higher drive current than that with a thinner silicon interlayer.A silicon nMOSFET with the same EOT HfO2 is included for comparison.

passivation can be effectively reduced to 17 mV for the devicewith thick silicon passivation, again probably attributed to lessGe concentration in the high-κ bulk. At the same time, thethick silicon passivation also effectively reduces the interfacetrap density evidenced by the less frequency dispersion between10 and 100 kHz, which could be attributed to less formation ofgermanium oxide at the interface. The interface trap density canbe reduced to 3.2 × 1011 cm−1 · eV−1, which is measured by acharge-pumping technique.

The gate leakage currents at Vg = Vfb + 1 V are 5.01 × 10−2

and 1.27 × 10−1 A/µm2, for the thick Si sample and thethin Si sample, respectively. The output characteristics of thenMOSFETSs (Lg = 20 µm) are shown in Fig. 3(a), plotted atthe same Vg–Vth. The transistor with the thick silicon layer hasa significantly higher Id than that that with the thin silicon layer.Nonetheless, it is lower than the HfO2/Si control device due tothe dampening in the linear region. This suggests that there isa considerable series resistance in Ge MOSFETs, which maybedue to insufficient dopant activation at 450 C. Fig. 3(b) showsthe Id–Vg characteristics of the transistors. Due to the reductionof negative charge, which is observed in the C–V curve, thetransistor with the thick silicon layer has a smaller Vth (0.6V) than its counterpart (0.9 V). In addition, it also exhibits asmaller subthreshold swing (SS) than that with the thin silicon-passivation layer. This agrees well with the discussion that theinterface trap density reduces when there is more silicon at thegermanium surface prior to CVD HfO2 deposition.

Fig. 4 inset shows the split C–V measurement results ofthe two transistors. They match the full C–V result in Fig. 2well and enable the accurate extraction of depletion charge QB

and inversion charge Qn, respectively. The extracted mobilityis shown in Fig. 4. The channel vertical electric field wasestimated by Eeff = (QB + 0.5 · Qn)/κGeε0, where κGe is theGe dielectric constant, and ε0 is the permittivity of vacuum.The silicon nMOSFETS with the same MOCVD HfO2 is alsocharacterized for comparison. For the thin silicon passivation,the Ge transistor exhibits lower electron mobility than the sili-con device. This is probably due to the significant negativefixed charge in the dielectric and the high interface trap densityat the oxide/semiconductor interface, both leading to seriousCoulomb scattering of the channel carriers. Increasing the

WU et al.: GERMANIUM nMOSFET WITH CVD HfO2 GATE DIELECTRIC AND SILICON SURFACE PASSIVATION 481

Fig. 4. Electron mobility of the Ge nMOSFETs. The electron mobility of theHfO2/Si system is included for comparison. The inset shows the split C–Vresult for mobility extraction.

silicon amount helps to improve the mobility significantly. Thepeak mobility is improved by ∼ 55%. As a result, the Getransistor shows ∼ 61% higher peak electron mobility than thatof the silicon control. Furthermore, it should be mentioned thatthe thick silicon in this experiment may not be the optimizedcondition as germanium oxide is still observed (Fig. 1). Sincethe charge centroid of channel carriers are ∼ 10 Å or evenfarther away from the interface, which is larger than the silicon-layer thickness, there must be an optimum amount of siliconin that when there is no germanium oxide yet, the majorityof electrons are kept in germanium for further drive-currentenhancement.

It should also be noticed that, in the high-electric-fieldregime, the Ge transistor shows comparable electron mobilityas the Si control. It is found that the drive current (Id) does notincrease proportional to 1/L. For instance, the drive current is0.347 µA/µm for a thick SP transistor of 20-µm channel lengthat VD = 0.05 V and VG–Vth= 1.0 V (linear region), while thedrive current for a 10-µm transistor is 0.502 µA/µm. This alsosuggests that there could be a considerable series resistance inthe S/D region, which limits the drive current significantly. Thishigh S/D series resistance is likely due to the relatively lowtemperature of activation anneal, and it consequently leads toan underestimation of electron mobility. Therefore, the electron

mobility at the high electric field can be further improved if theS/D series resistance can be reduced.

IV. CONCLUSION

In summary, a self-aligned Ge nMOSFET with CVD high-κgate dielectric was demonstrated with a conventional gate-firstprocess sequence. The silicon passivation by SiH4 annealingprior to the gate dielectric deposition plays a critical role inthe device performance. Provided that the silicon-passivation-layer thickness is small enough to be oxidized during the ther-mal process of gate stack formation, increasing the siliconthickness helps to reduce hysteresis, fixed charge in the gatedielectric, and interface trap density at the oxide/semiconductorinterface. As a result, a high-electron-mobility Ge nMOSFETwith CVD HfO2 is demonstrated with ∼ 61% higher peakmobility and comparable mobility at the high electrical fieldregime in comparison to the silicon counterpart under the samedeposition of HfO2.

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