Fractional-N PLL with multi-element fractional divider for...
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Fractional-N PLL with multi-element fractional divider for noise reduction Arindam Sanyal ✉ , Xueyi Yu, Yanlong Zhang and Nan Sun A novel technique to suppress quantisation noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fine-resolution multi-element frac- tional divider is presented. The proposed technique suppresses noise uniformly over the entire frequency range. It is mostly digital and is applicable for both analogue and digital PLLs. The proposed technique with an eight-element fractional divider can suppress the quantisation noise by 18 dB compared with a conventional fractional-N PLL. Introduction: Unlike integer-N phase-locked loops (PLLs), fractional-N PLLs allow synthesis of frequencies that are a fraction of the reference. Thus, it allows a higher reference frequency and a wider PLL band- width, which leads to faster settling time and stronger suppression of voltage controlled oscillator (VCO) noise. However, fractional-N PLL have an additional noise source in the form of quantisation error from ΔΣ modulator used to generate the fractional division ratio. For example, to implement a division ratio of 10.6, a conventional fractional-N PLL switches between integer division ratios of 10 and 11. It relies on the loop filter to suppress the quantisation noise. However, for a wide-band PLL, this quantisation noise can easily dominate the PLL phase noise [1] and cause large spurs. There have been several techniques to address this issue. An analogue approach is to inject current into the charge pump to cancel out the quan- tisation noise. However, it requires a high-resolution DAC along with accurate gain and offset calibration techniques [2]. A multi-phase ring VCO can also be used to cancel the quantisation noise [3], but it requires complicated phase realignment technique. Another approach is to use a finite impulse response (FIR) filter at the ΔΣ modulator output [1]. Its merit is that it is mostly digital, but it is effective only at high frequen- cies. For a wide-band PLL, a large number of FIR filter taps are required to adequately suppress the quantisation noise. This Letter presents a simple and mostly digital technique that signifi- cantly reduces the quantisation noise at all frequencies. Compared with the FIR filtering technique of [1], the proposed technique achieves a significant improvement in performance while incurring only a small increase in hardware complexity. Proposed technique: The core idea of the proposed technique is to reduce the quantisation noise by increasing the ΔΣ modulator resolution. Again taking the division ratio of 10.6 as an example, if we can implement finer division ratios, such as 10.5 and 10.625, then we can just switch between these two division ratios. This way, our effective quantisation step is 1/8, and thus, the quantisation noise is 18 dB smaller than that of a conventional fractional-N PLL. Now, the key question is how to implement an instantaneous frac- tional divider in hardware. Only one divider is not adequate as it can only count integer cycles, but we can arrange multiple of them running in parallel. For example, to implement the division ratio of 10.625, we can arrange 8 dividers, and choose 5 of them with the modulus of 11 and the remaining 3 of them with the modulus of 10. By combining these dividers’ outputs, we effectively build a divider with a division ratio of 10.625. To get other fractional division ratios (e.g. 10.5), we can simply change the number of dividers with modulus 10 or 11. In a more general sense, to implement a division ratio of N+k/M, where N, k, and M are integers, we can arrange in total M dividers, and have k of them with modulus of N+1 and M–k of them with modulus of N. The circuit architecture implementing the proposed technique is shown in Fig. 1. As mentioned earlier, the proposed fractional divider consists of eight conventional multi-modulus dividers. They are con- trolled by the ΔΣ modulator to realise fractional division ratios. A key difference from a conventional fractional-N PLL is that the quantisation steps of the ΔΣ modulator are not integer value (e.g. 0 and 1) but frac- tional values (e.g. 1/8, 2/8,…, and 7/8) in the proposed technique. The decrease in the quantisation step size is the key to the noise reduction. In order to combine the outputs of the multi-element divider array, the phase-frequency detector (PFD) and the charge pump are also split into eight identical slices. This way, the eight divider outputs are effec- tively summed up in the charge domain. Note that each slice of the charge pump consumes only 1/8 of the original charge pump current, so that the total charge pump current remains the same as in the conven- tional fractional-N PLL. As a result, the PLL loop behaviour is unchanged. MMD PFD DEM 8 Up Dn 8 1 f ref f div f vco multi-element fractional divider loop filter VCO CP 8 8 d DS H(z) eight-level 0 1 –G(z) vector quantiser d 8 fractional DS modulator DEM a a Fig. 1 Architecture of proposed technique with an eight-element fractional divider To ensure that the PLL is locked, each divider slice has to maintain an average division ratio of N + α, where N is integer part and α is the frac- tional part. This is done by inserting a dynamic element matching (DEM) block after the ΔΣ modulator. The DEM block scrambles the divider selection to ensure that average of the division ratio for each divider is identical. Note that the DEM also brings a key benefit in that the mismatch error among each charge-pump slice is greatly suppressed. This is similar to a multi-bit DAC where DEM can address the DAC element mismatch. A popular way to implement the DEM is to use a barrel shifter to high-pass shape the mismatch errors to the first order or to use a vector quantiser to shape the mismatch errors to higher orders [4]. Fig. 2 compares the phase noise for a classic fractional-N PLL, a PLL with an eight-tap FIR filter [1], and the proposed technique with an eight-element fractional divider, using a linear phase-domain PLL model. The fractional-N PLL is designed to have a third-order loop filter, a closed-loop bandwidth of 1 MHz, and a reference frequency of 20 MHz. It can be seen from Fig. 2 that the FIR filter only suppresses the quantisation noise beyond 1 MHz. By contrast, the proposed technique suppresses the quantisation noise by 18 dB over the entire frequency range and substantially outperforms the FIR filtering technique of [1]. 10 3 classic fractional-N PLL PLL with eight-tap FIR filter [1] proposed PLL with eight-element fractional divider –100 –50 –150 –200 spectral density, dBc/Hz –250 10 4 10 5 frequency, Hz 10 6 10 7 Fig. 2 Fractional-N PLL phase noise with different techniques Another important advantage of the proposed technique is that the ripple in the VCO control voltage is much smaller than that in a conven- tional fractional-N PLL. This is because the quantisation error has been greatly reduced. This can greatly relax the linearity requirement for the charge pump and the VCO, leading to significantly reduced quantisation noise folding effect and spur. The hardware cost for the proposed technique is the fine-resolution quantiser in the ΔΣ modulator, the DEM block, and multiple copies of the divider and PFD. The increased hardware is entirely digital and entails very low cost in terms of design effort as well as area and ELECTRONICS LETTERS 12th May 2016 Vol. 52 No. 10 pp. 809–810
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Transcript of Fractional-N PLL with multi-element fractional divider for...
Fractional-N PLL with multi-elementfractional divider for noise reduction
Arindam Sanyal✉, Xueyi Yu, Yanlong Zhang and Nan Sun
ELECT
A novel technique to suppress quantisation noise in a ΔΣ fractional-Nphase-locked loop (PLL) using a fine-resolution multi-element frac-tional divider is presented. The proposed technique suppresses noiseuniformly over the entire frequency range. It is mostly digital and isapplicable for both analogue and digital PLLs. The proposed techniquewith an eight-element fractional divider can suppress the quantisationnoise by 18 dB compared with a conventional fractional-N PLL.
Introduction: Unlike integer-N phase-locked loops (PLLs), fractional-NPLLs allow synthesis of frequencies that are a fraction of the reference.Thus, it allows a higher reference frequency and a wider PLL band-width, which leads to faster settling time and stronger suppression ofvoltage controlled oscillator (VCO) noise. However, fractional-N PLLhave an additional noise source in the form of quantisation error fromΔΣ modulator used to generate the fractional division ratio. Forexample, to implement a division ratio of 10.6, a conventionalfractional-N PLL switches between integer division ratios of 10 and11. It relies on the loop filter to suppress the quantisation noise.However, for a wide-band PLL, this quantisation noise can easilydominate the PLL phase noise [1] and cause large spurs.
There have been several techniques to address this issue. An analogueapproach is to inject current into the charge pump to cancel out the quan-tisation noise. However, it requires a high-resolution DAC along withaccurate gain and offset calibration techniques [2]. A multi-phase ringVCO can also be used to cancel the quantisation noise [3], but it requirescomplicated phase realignment technique. Another approach is to use afinite impulse response (FIR) filter at the ΔΣ modulator output [1]. Itsmerit is that it is mostly digital, but it is effective only at high frequen-cies. For a wide-band PLL, a large number of FIR filter taps are requiredto adequately suppress the quantisation noise.
This Letter presents a simple and mostly digital technique that signifi-cantly reduces the quantisation noise at all frequencies. Compared withthe FIR filtering technique of [1], the proposed technique achieves asignificant improvement in performance while incurring only a smallincrease in hardware complexity.
Proposed technique: The core idea of the proposed technique is toreduce the quantisation noise by increasing the ΔΣmodulator resolution.Again taking the division ratio of 10.6 as an example, if we canimplement finer division ratios, such as 10.5 and 10.625, then we canjust switch between these two division ratios. This way, our effectivequantisation step is 1/8, and thus, the quantisation noise is 18 dBsmaller than that of a conventional fractional-N PLL.
Now, the key question is how to implement an instantaneous frac-tional divider in hardware. Only one divider is not adequate as it canonly count integer cycles, but we can arrange multiple of themrunning in parallel. For example, to implement the division ratio of10.625, we can arrange 8 dividers, and choose 5 of them with themodulus of 11 and the remaining 3 of them with the modulus of 10.By combining these dividers’ outputs, we effectively build a dividerwith a division ratio of 10.625. To get other fractional division ratios(e.g. 10.5), we can simply change the number of dividers withmodulus 10 or 11. In a more general sense, to implement a divisionratio of N+k/M, where N, k, and M are integers, we can arrange intotal M dividers, and have k of them with modulus of N+1 and M–kof them with modulus of N.
The circuit architecture implementing the proposed technique isshown in Fig. 1. As mentioned earlier, the proposed fractional dividerconsists of eight conventional multi-modulus dividers. They are con-trolled by the ΔΣ modulator to realise fractional division ratios. A keydifference from a conventional fractional-N PLL is that the quantisationsteps of the ΔΣ modulator are not integer value (e.g. 0 and 1) but frac-tional values (e.g. 1/8, 2/8,…, and 7/8) in the proposed technique. Thedecrease in the quantisation step size is the key to the noise reduction. Inorder to combine the outputs of the multi-element divider array, thephase-frequency detector (PFD) and the charge pump are also splitinto eight identical slices. This way, the eight divider outputs are effec-tively summed up in the charge domain. Note that each slice of thecharge pump consumes only 1/8 of the original charge pump current,
RONICS LETTERS 12th May 2016 Vol. 52 N
so that the total charge pump current remains the same as in the conven-tional fractional-N PLL. As a result, the PLL loop behaviour isunchanged.
MMD
PFD
DEM8
Up
Dn
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fdiv fvco
multi-element fractional divider
loop filter VCO
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fractional DS modulator
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Fig. 1 Architecture of proposed technique with an eight-element fractionaldivider
To ensure that the PLL is locked, each divider slice has to maintain anaverage division ratio of N + α, where N is integer part and α is the frac-tional part. This is done by inserting a dynamic element matching(DEM) block after the ΔΣ modulator. The DEM block scrambles thedivider selection to ensure that average of the division ratio for eachdivider is identical. Note that the DEM also brings a key benefit inthat the mismatch error among each charge-pump slice is greatlysuppressed. This is similar to a multi-bit DAC where DEM canaddress the DAC element mismatch. A popular way to implement theDEM is to use a barrel shifter to high-pass shape the mismatch errorsto the first order or to use a vector quantiser to shape the mismatcherrors to higher orders [4].
Fig. 2 compares the phase noise for a classic fractional-N PLL, a PLLwith an eight-tap FIR filter [1], and the proposed technique with aneight-element fractional divider, using a linear phase-domain PLLmodel. The fractional-N PLL is designed to have a third-order loopfilter, a closed-loop bandwidth of 1 MHz, and a reference frequencyof 20 MHz. It can be seen from Fig. 2 that the FIR filter only suppressesthe quantisation noise beyond 1 MHz. By contrast, the proposedtechnique suppresses the quantisation noise by 18 dB over the entirefrequency range and substantially outperforms the FIR filteringtechnique of [1].
103
classic fractional-N PLLPLL with eight-tap FIR filter [1]proposed PLL with eight-element fractional divider
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106 107
Fig. 2 Fractional-N PLL phase noise with different techniques
Another important advantage of the proposed technique is that theripple in the VCO control voltage is much smaller than that in a conven-tional fractional-N PLL. This is because the quantisation error has beengreatly reduced. This can greatly relax the linearity requirement for thecharge pump and the VCO, leading to significantly reduced quantisationnoise folding effect and spur.
The hardware cost for the proposed technique is the fine-resolutionquantiser in the ΔΣ modulator, the DEM block, and multiple copies ofthe divider and PFD. The increased hardware is entirely digital andentails very low cost in terms of design effort as well as area and
o. 10 pp. 809–810
power especially for designs in advanced technology. Compared withthe FIR-filtering technique of [1], the only changes in hardware arethe DEM block and the quantiser.
Simulation results: To verify the proposed technique, a type-II,third-order ΔΣ fractional-N PLL is implemented in Simulink. Thereference frequency is 20 MHz and the PLL bandwidth is 1 MHz. Athird-order ΔΣ modulator was used to generate a division ratio of10.57. For simplicity, quantisation noise from the ΔΣ modulator is theonly source of noise in the simulations. The VCO frequency is down-converted to 20 MHz and the output spectra for different techniquesare plotted in Fig. 3. As can be seen from Fig. 3a, the conventionalfractional-N PLL has large quantisation noise and appreciable spur.The FIR filtering technique can suppress the quantisation noise butonly at high frequencies [see Fig. 3b]. By contrast, the proposed tech-nique with eight-element divider suppresses noise across all frequenciesby 18 dB, which matches the analysis using linear model (see Fig. 2). Tofurther validate the proposed technique in the presence of devicemismatches, a 3σ mismatch of 15% is added to the charge pumpslices. The simulation result of Fig. 3d shows no noticeable degradation,which is enabled by the DEM block. The simulated root mean squarejitters for the conventional fractional-N PLL, the FIR filtering technique,our proposed technique with and without mismatches, are 188, 126, 25,and 23 ps, respectively. This again shows that our proposed techniquecan reduce jitter by eight times. Note that the phase noise and jittercan be further reduced by increasing the number of slices and thefractional divider resolution. The trade-off is hardware complexity.
15 20 25
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Fig. 3 VCO output spectrum for
a Conventional fractional-N PLLb PLL with eight-tap FIR filtering [1]c Proposed technique with eight-element fractional dividerd Proposed technique with 3σ mismatch of 15%
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proposed PLL with eight-element fractional divider
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ge, m
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Fig. 4 VCO control voltage transient at lock
ELECTRONICS LETTERS
Fig. 4 shows the VCO control voltage at lock for three different cases:the conventional fractional-N PLL, the FIR filtering technique, and ourproposed technique. As expected, the ripple of the proposed technique isonly 1/8 of the conventional PLL, and is also significantly smaller thanthat of the FIR filtering technique.
Conclusion: A mostly digital technique has been presented to suppressΔΣ quantisation noise in a wide-band fractional-N PLLs. It is based onthe use of a fine-resolution fractional divider. The proposed techniquehas a low hardware cost due to its mostly digital nature especially inadvanced CMOS processes. It can be applied to both analogue anddigital fractional-N PLLs.
Acknowledgement: This work was supported by the NSF grants1254459, 1509767, and 1527320.
© The Institution of Engineering and Technology 2016Submitted: 7 March 2016 E-first: 22 April 2016doi: 10.1049/el.2016.0680One or more of the Figures in this Letter are available in colour online.
Arindam Sanyal and Nan Sun (Department of Electrical and ComputerEngineering, The University of Texas at Austin, TX, USA)
✉ E-mail: [email protected]
Xueyi Yu (Spintrol Ltd., Shanghai, People’s Republic of China)Yanlong Zhang (School of Microelectronics, The University of Texas atAustin, TX, USA)
Yanlong Zhang: Also with School of Microelectronics, XidianUniversity, Shaanxi, People’s Republic of China
References
1 Yu, X., Sun, Y., Rhee, W., andWang, Z.: ‘An FIR-embedded noise filter-ing method for ΔΣ fractional-N PLL clock generators’, IEEE JSSC, 2009,44, (9), pp. 2426–2436
2 Swaminathan, A., Wang, K.J., and Galton, I.: ‘A widebandwidth2.4 GHz ISM-band fractional-N PLL with adaptive phase noise cancella-tion’, IEEE JSSC, 2007, 42, (12), pp. 2639–2650
3 Sidiropoulos, S., and Horowitz, M.A.: ‘A semidigital dual delay-lockedloop’, IEEE JSSC, 1997, 32, (11), pp. 1683–1692
4 Sun, N.: ‘High-order mismatch-shaping in multibit DACs’, IEEE TCAS–II, 2011, 58, (6), pp. 346–350
12th May 2016 Vol. 52 No. 10 pp. 809–810
