ELEN 6901ELEN 6901ELEN 6901 ELEN 6901 PLL Phase Noise/Jitter Modeling PLL Phase Noise/Jitter Modeling

Chun-Wei HsuKarthik Tripurari

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Introduction of Phase NoiseIntroduction of Phase Noise

• The oscillator output Vo with the phase noise Φn

)sin()cos()cos()sin()sin( 000 nnn twAtwAtwAVo φφφ +=+=where A is the amplitude and w0 is the frequency

• For small noise termntwAtwAVo φ)cos()sin( 00 +≅

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Introduction of Phase NoiseIntroduction of Phase Noise

• Phase perturbation from device noise includes white and flicker noise

• Power spectral density SΦ of phase noise Φn

• Extracting noise parameters– Single-sided PSD L(f)

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– L(∆f)=(1/2)SΦ(∆f)Lee, T.H.; Hajimiri, A., "Oscillator phase noise: a tutorial," Solid-State Circuits, IEEE Journal of , vol.35, no.3, pp.326-336, Mar 2000

Impact of Phase NoiseImpact of Phase Noise

• Phase Noise– Reduce SNR of the signal– Tx: Out-of band emission

– Rx: Reciprocal mixing

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Phase JitterPhase Jitter

• Jitter issues– Sampling cases

Degrade SNR of ADC/DAC– Data recovery considerations

Reduce the eye-openingDecrease BER

• Definition of phase jitter– Difference between the measured time and the

ideal bit period

dfSfsig

jitterphase ∫ Φ= 2_

2 )2

1(π

σ

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PLL Noise ModelingPLL Noise Modeling

• Phase domain model– Simple and Linear model– Sampling nature of PLL ignored– Efficient for the noise analysis when the

PLL is in locked state

• Voltage domain model– A complete but complex model– No quiescent operating points and only

periodic operating points– Describes phenomena like cycle slipping,

false locking and lock captureL i l ti ti

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– Long simulation time

Phase Domain ModelPhase Domain Model

• Noise Sources– Reference– PFD/CP– Loop filter– VCO– Divider

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CPPLL Type II 3CPPLL Type II 3rdrd OrderOrder

• Transfer function of loop filter (R-C//Cp))1/()( zwssZ +

=

11

)1/)(()(

pp wsCCssZ

++=

)/(1,1

pppz CCRCC

wRC

w+

==

• Transfer function of loop gain (two poles at s=0)

NwsCCswsKvcoIcp

NsKvcosZIcpsL z 1

)1/)(()1/(

21)(

2)( 2 ++

+==

ππ NwsCCsNs pp )1/)((22 ++ππ

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Noise Transfer Function of Type II CPPLLNoise Transfer Function of Type II CPPLL

• Noise from the reference

)()( sHsNLoutHref ==Φ

=

where H(s) is the closed-loop transfer function of PLL

)()(1

sHsLnref

Href+Φ

• Noise from PFD/CP

sKvco

sLsZ

IncpoutHpfdcp

)(1)(

+=

Φ=

• Noise from VCO

)(11

sLnvcooutHvco

+=

ΦΦ

=

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)(

Noise Transfer FunctionNoise Transfer Function

• PLL parameters– Fout=2.4GHz, Fref=16MHz– Icp=1mA, Kvco=2π*300MHz– R=300Ω, C=200nF, Cp=10nF

150Noise Transfer Function

HrefHpfdcpHvco

50

100

e (d

B)

Hvco

0

Mag

nitu

de

100

-50

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102 103 104 105 106 107-100

Frequceny (Hz)

VCO ModelVCO Model

• Fundamental function

∫∫ ×==Φ dtVKfdt cvco )(

• Noise model

∫∫ f cvco )(

– Flicker/White noise added to the frequency)(tvVKf ncvco +×=

– 1/f3 and 1/f2 regions of the phase noise plot

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White Noise Generating in VerilogWhite Noise Generating in Verilog--AA

• white_noise(PSD,”name”)– PSD is Power Spectral Density in units of V2/Hz or

A2/HA2/Hz– “name” identifies the source while analyzing the

i i l ti ltnoise simulation results

E l• Examples– V(res) <+

white noise(4*`P K*$temperature*Rs ”thermal”)white_noise(4* P_K*$temperature*Rs, thermal )– I(diode) <+ white_noise(2*`P_Q*Id,”shot”)

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Flicker Noise Generating in VerilogFlicker Noise Generating in Verilog--AA

flicker_noise(pow,n,”name”)– pow is Power Spectral Density of the source at

1H i i f V2/H A2/H1Hz in units of V2/Hz or A2/Hz– n is the order of the frequency i.e. 1/fn is modeled– “name” is to identify the source while analyzing

the noise simulation results

• Example of 1/f roll-off noisef fli k f– f_flicker: corner frequency

– wn: Desired white noise level– V(out) <+ flicker_noise(wn*f_flicker, 1, “fn”)

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VCO/Divider Test BenchVCO/Divider Test Bench

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VCO PSS Simulation SetupVCO PSS Simulation Setup

Check this for any autonomous osciallator

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Fundamental Oscillation Frequency of the oscillator

VCO VCO PnoisePnoise Simulation SetupSimulation SetupNoise

FoldingFolding

How toHow to choose

this?

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VCO Simulation ResultsVCO Simulation Results

Flicker corner

1/f2 –Region1/f Region.Slope = -20dB/dec1/f3 – Region

Slope = -30dB/dec

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Alternate VCO Model for Phase NoiseAlternate VCO Model for Phase Noise

Whit i (1/f2)

V(out) instead of Theta(out).

White noise (1/f2)

Flicker noise (1/f3)( ) ( )Discipline of “out” should be

electrical/ voltage

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Source: www.designers-guide.org

Divider VerilogDivider Verilog--A Model A Model

Region of Interest Sampling Effects

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Divider Noise Simulation SetupDivider Noise Simulation Setup

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Divider Simulation ResultDivider Simulation Result

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PFD/CP Test BenchPFD/CP Test Bench

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PFD/CP VerilogPFD/CP Verilog--A ModelA Model

Region of Interest

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PFD Phase Noise Simulation ResultPFD Phase Noise Simulation Result

Flicker Noise

White Noise

Flicker Noise Corner = 10kHz

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PLL Simulation Test BenchPLL Simulation Test Bench

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PLL PSS Analysis SetupPLL PSS Analysis Setup

• PLL is a driven system so the oscillator option h ld b t d OFFshould be turned OFF

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PLL Simulation ResultsPLL Simulation Results

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SummarySummary

• Phase noise and its effects on RF transceiver systems were introduced

• Phase domain and voltage domain models were dcompared

V il A d l f th diff t b ildi bl k• Verilog-A models for the different building blocks of a PLL were discussed

• Simulation setup for running phase noise simulation was demonstratedsimulation was demonstrated

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AcknowledgementsAcknowledgements

• We would like to thank Prof. Peter Kinget for the helpful discussions on the content of this presentation and Shih An for teaching us techniques to improve theShih-An for teaching us techniques to improve the simulation speed

• The Verilog-A code used for this presentation and those we have ever written are derived from the ones inthose we have ever written are derived from the ones in www.designers-guide.org

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