EE 321 Analog Electronics, Fall 2013Homework #11 solution

4.43. For each of the circuits in Fig. P4.43, find the labeled node voltages. Forall transistors, k′

nW

L= 0.4mA/V2, Vt = 1V, λ = 0.

(a) Figure P3.43a

Since vDS = vGS + V , (V = 5V) we are in the triode region. Insert expression for vDS

to get

iD = k′

n

W

L

[

(vGS − Vt) (vGS − Vt)−(vGS − Vt)

2

2

]

=k′

n

2

W

L(vGS − Vt)

2

which gives

V1 =− vGS = −

√

2iD

(

k′

n

W

L

)

−1

− Vt

=−√

2×10× 10−6

0.4× 10−3− 1

=− 1.22V

(b) Figure P3.43b

Same as (a), except larger current, so we get

1

V2 =−√

2× 100× 10−6

0.4× 10−3− 1

=− 1.71V

(c) Figure P3.43c

Same as (a), except larger current still, so we get

V3 =−√

2× 1× 10−3

0.4× 10−3− 1

=− 3.24V

(d) Figure P3.43d

In this case we are in the saturation region because vDS > vGS − Vt,

iD =k′

n

2

W

L(vGS − Vt)

2

2

V4 =vGS =

√

2iD

(

k′

n

W

L

)

−1

+ Vt

=

√

2× 10× 10−6

0.4× 10−3+ 1

=1.22V

(e) Figure P3.43e

Same as previous case except larger current.

V5 =vGS =

√

2× 10−3

0.4× 10−3+ 1

=3.24V

(f) Figure P3.43f

Saturation mode, so

iD =k′

n

2

W

L(vGS − Vt)

2

and

3

iD =V − vGS

R

V − vGS = Rk′

n

2

W

L

[

v2GS + V 2

t − 2vGSVt

]

V − vGS = Av2GS + AV 2

t − 2AvGSVt

Av2GS + vGS (1− 2AVt) + AV 2

t − V = 0

Av2GS +BvGS + C = 0

vGS =−B ±

√B2 − 4AC

2A

where

A =R

2k′

n

W

L= 20V−1 B = 1− 2AVt = 1− 2× 20× 1 = −39

C = AV 2

t − V = 20× 12 − 5 = 15V

so that

vGS =39±

√392 − 4× 20× 15

2× 20

vGS = 1.43V or vGS = 0.53V

Only one of these solutions is correct. We assume non-zero current and thus conductingmode, which is only true for vGS > Vt. Therefore the correct solution is

vGS = 1.43V

(g) Figure P3.43g

4

This is the same problem except a different resistance. In this case we have

A =R

2k′

n

W

L= 0.2V−1 B = 1− 2AVt = 1− 2× 0.2× 1 = 0.6

C = AV 2

t − V = 0.2× 12 − 5 = −4.8V

vGS =−B ±

√B2 − 4AC

2A

vGS = 3.62V or vGS = −6.6V

The first potential solution is the correct one as we assumed vGS > Vt.

(h) Figure P3.43h

In this case we have

vDS + iDRD = 2V V8 = iDR− V = −vGS

since vDS = vGS + V > vGS − Vt, it is operating in the saturation region

iD =k′

n

2

W

L(vGS − Vt)

2

5

Inserting the expression for iD in terms of vGS above,

iD =V − vGS

R

we get

V − vGS

R=

k′

n

2

W

L(vGS − Vt)

2

This is identical to the expression in problem (f) above, so the solution is the same,vGS = 1.43V, and

V8 = −vGS = −1.43V

4.44. For each of the circuits shown in Fig P4.44, find the labeled node voltages.The NMOS transistors have Vt = 1V, and k′

nW

L= 2mA/V2. Assume λ = 0.

(a) For Figure P4.44a

We have vDS1 = 2V − V1, and vGS1 = V − V1, where V = 5V. Thus, transistor 1 isoperating in saturation. Also notice that V2 = iDR − V . If we assume that transistor2 is also operating in saturation then vGS1 = vGS2. And since vGS2 = −V2, we have

−vGS1 = iDR− V = Rk′

n

2

W

L(vGS1 − Vt)

2 − V

Choose A = Rk′n2

WL, we get

6

−vGS1 = Av2GS1 + AV 2

t − 2AvGS1Vt − V

Av2GS1 + AV 2

t − 2AvGS1Vt + vGS1 − V = 0

or

Av2GS1 +BvGS + C = 0

where

A = Rk′

n

2

W

L=

1× 103

2× 2× 10−3 = 1

1

V

B = 1− 2AVt = 1− 2 = −1 C = AV 2

t − V = −4V

vGS1 =−B ±

√B2 − 4AC

2A=

1±√1 + 4× 4

2

vGS1 = 2.56V or vGS1 = −1.56V

The second cannot be a solution, because we assumed vGS1 > Vt to be conducting. Inthe first case we get

V1 = V − vGS1 = 5− 2.56 = 2.44V

which puts the second transistor in saturation mode, so that assumption is OK. Thus,

V2 = −vGS2 = −vGS1 = −2.56V

(b) For Figure P4.44b

Both transistors are operationg in saturation, and are identical. We have

vDS1 = vDS2 = vDS = vGS1 = vGS2 = vGS

Thus,

2vGS + 2iDR = V

(V = 10V). We also have

iD =k′

n

2

W

L(vGS − Vt)

2

7

Thus

V − 2vGS

2R= iD =

k′

n

2

W

L(vGS − Vt)

2

Choosing A = k′n2

WL, we get

V − 2vGS

2R= Av2GS + AV 2

t − 2AvGSVt

Av2GS + AV 2

t − 2AvGSVt +vGS

R−

V

2R= 0

Av2GS +BvGS + C = 0

where

A =k′

n

2

W

L= 1× 10−3

A

V2B = −2AVt +

1

R= −1× 10−3Ω−1

C = AV 2

t −V

2R= −4 × 10−3A

vGS =−B ±

√B2 − 4AC

2A=

1× 10−3 ±√1× 10−6 + 4× 10−3 × 4× 10−3

2× 10−3

vGS = 2.56V or vGS = −1.56V

The first solution is the correct one because we assumed vGS > Vt. In that case,

iD =k′

n

2

W

L(vGS − Vt)

2 = 1× 10−3 (2.56− 1)2 = 2.43× 10−3A

and

V3 =V − iDR = 10− 2.43 = 7.57V

V4 =V3 − vGS = 7.57− 2.56 = 5.01V

V5 =V4 − vGS = 5.01− 2.56 = 2.45V

V5 should also be V5 = 0+iDR = 2.43V, which is close to within a few rounding errors.

8

4.45. For the PMOS transistor in the circuit shown in Fig. P4.45, k′

p = 8µA/V2,

W

L= 25, and |Vtp| = 1V. For I = 100µA, find the voltages VSD and VSG for

R = 0, 10 kΩ, 30 kΩ, and 100 kΩ. For what value of R is VSD = VSG? VSD =VSG

2?

VSD =VSG

10?

We are being asked about both saturation and triode mode operation. Choose Vt = 1V.First we determine the operating mode of the device. That depends on the relative valuesof VSD and VSG. When VSD < VSG − Vt, or VSG − VSD > Vt, then we are operating in triodemode. Otherwise saturation mode. But VSG − VSD = IR, so the cirterium is IR > Vt fortriode mode. Here is a table

R (kΩ) 0 10 30 100I (µA) 100Vt (V) 1IR (V) 0 1 3 10Mode Saturation Saturation Triode Triode

For the two saturation mode cases we have

iD =k′

p

2

W

L(vSG − Vt)

which gives us

vSG =

√

2iDL

Wk′

p

+ Vt =

√

2× 100× 10−6

25× 8× 10−6+ 1 = 2V

And vSD = vSG − IR. For R = 0 we get vSD = vSG = 2V, whereas for R = 10 kΩ we getvSD = 2− 100× 10−6 × 10× 103 = 1V.For the triode region we have

iD =W

Lk′

p

[

(vSG − Vt) vSD −v2SD2

]

9

In this case we can substitute VSD = VSG − IR and get

iD =W

Lk′

p

[

(VSG − Vt) (VSG − IR)−(VSG − IR)2

2

]

iDL

Wk′

p

=

[

V 2

SG − VSGIR− VSGVt + VtIR−V 2

SG

2−

I2R2

2+

VSGIR

2

]

V 2

SG

2+ VSG

(

−IR− Vt +IR

2

)

+ VtIR−I2R2

2−

iDL

Wk′

p

= 0

V 2

SG

2+ VSG

(

−Vt −IR

2

)

+ VtIR−I2R2

2−

iDL

Wk′

p

= 0

Making

A =1

2B = −Vt −

IR

2C = VtIR−

I2R2

2−

iDL

Wk′

p

We can solve the quadratic equation as

VSG =−B ±

√B2 − 4AC

2A

R (kΩ) 30 100A 1

2

1

2

B (V) -2.5 -6C (V2) -2 -40.5VSG (V) 5.7/-0.7 11.2/-7.2VSD (V) 2.7 1.25

Only the positive solutions are physical and those are the answer. As a final check we shouldverify that these voltage do indeed correspond to triode region operation. That is the caseif VSD − VSG < Vt. That is indeed the case.

Next we are asked the values of R for which there is a particular reltionshiop betweenVSD and VSG. First, for the case where VSD = VSG, that can only be the case when R = 0.Secondly, the value for which VSD = VSG

2. We already found that is the case for R = 10 kΩ.

Third, for vSD = vSG

10, we must be operating in the triode mode.

iD =W

Lk′

p

[

(vSG − Vt) vSD −v2SD2

]

and inserting vSD = vSG

10(and iD = I),

I =W

Lk′

p

[

(vSG − Vt)vSG10

−v2SG200

]

=W

Lk′

p

[

v2SG10

−vSGVt

10−

v2SG200

]

=W

Lk′

p

[

19

200v2SG −

1

10vSGVt

]

10

19

200v2SG −

1

10VtvSG −

IL

Wk′

p

= 0

A =19

100B = −

Vt

10= −0.1V C = −

IL

Wk′

p

= −100× 10−6

25× 8× 10−6= −0.5V2

vSG =−B ±

√B2 − 4AC

2A= 2.880 or − 1.827

The second solution is not valid, so we continue with the first solution,

R =vSG − vSD

I=

vSG − vSG

10

I=

9vSG10I

=9× 2.880

10× 100× 10−6= 25.92 kΩ

4.53. The expression for the incremental voltage gain Av given in Eq (4.4) canbe written as

Av = −2 (VDD − VDS)

VOV

where VDS is the bias voltage at the drain (called VOQ in the text). This expres-sion indicates that for given values of VDD and VOV , the gain magnitude can beincreased by biasing the transistor at a lower VDS. This, however, reduces theallowable output signal swing in the negative direction. Assuming linear opera-tion around the bias point, show that the largest possible negative output signalpeak vo that is achievable while the transistor remains saturated is

vo =VDS − VOV

1 + 1

Av

For VDD = 5V and VOV = 0.5V, provide a table of values for Av, vo, and thecorresponding vi for VDS = 1V, 1.5V, 2V, and 2.5V. If k′

nW

L= 1mA/V2, find

ID and RD for the design for which VDS = 1V.Here is an illustration of the problem in which we are to determine vo:

vDS

iD

vO

VGS

VDS

DI

11

We are looking for the point, as we travel up the straight line, where vDSSat = vGS − Vt,which is the edge of the saturation region. Then vo = VDS − vDSSat. Let’s model linearly

vDS = VDS + vds vGS = VGS +vdsAv

At the maximum excursion we can write

vDSSat = VDS − vo vGSSat = VGS −voAv

Now we just set vDSSat = vGSSat − Vt and solve for vo.

VDS − vo = VGS −voAv

− Vt = VOV −voAv

vo =VDS − VOV

1− 1

Av

This is not the same expression as is given in the book. Nevertheless, I will continue withthis expression, and tabulate for VDD = 5V, and VOV = 0.5V

VDS (V) Av vo (V) vi (V)1 −16 0.47 0.0291.5 −14 0.93 0.0662 −12 1.38 0.122.5 −10 1.82 0.18

4.54. Figure P4.54 shows a CS amplifier in which the load resistor RD has beenreplaced with another NMOS transistor Q2 connected as a two-terminal device.Note that because vDG of Q2 is zero, it will be operating in saturation at alltimes, even when vI = 0 and iD2 = iD1 = 0. Noe also that the two transistorsconduct equal drain currents. Using iD1 = iD2, show that for the range of vI

over which Q1 is operating in saturation, that is for

Vt1 ≤ vI ≤ vO + Vt1

the output voltage will be given by

vo = VDD − Vt +

√

(W/L)1

(W/L)2

Vt −

√

(W/L)1

(W/L)2

vI

where we have assumed Vt1 = Vt2 = Vt. Thus the circuit functions as a lin-ear amplifier, even for large input signals. For (W/L)

1= (50µm/0.5µm) and

(W/L)2= (5µm/0.5µm), find the voltage gain.

12

For Q2 we have

iD =1

2

W2

L2

k′

n (VDD − vo − Vt)2

and for Q1 we have

iD =W1

L1

k′

n

[

(vI − Vt) vo −v2o2

]

We want to find vo, so we eliminate iD between the two equations.

1

2

W2

L2

(VDD − vo − Vt)2 =

W1

L1

[

(vI − Vt) vo −v2o2

]

This is a quadratic equation in vo. Solving it is straightforward but tedious. You will get twosolutions of which one is not physical and the other one is the one shown.

The voltage gain is the factor in front of vI , so

Av = −

√

W1/L1

W2/L2

= −

√

50/0.5

5/0.5= −3.2

13