[ECS 209th ECS Meeting - Denver, Colorado (May 7-May 12, 2006)] ECS Transactions - Charge Trapping...
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209th ECS Meeting, Abstract #407, copyright ECS Charge Trapping in High-κ Gate Dielectrics: A Recent Understanding D. Misra and N. A. Chowdhury ECE Dept., NJIT, Newark, NJ 07102 [email protected] Initially it was believed that threshold voltage shift (∆V T ), observed during constant voltage stress (CVS), does not represent the reliability of various gate stacks with high-κ dielectrics [1]. It is because the charge trapping is very transient and can be eliminated by applying a reverse direction electric field. This behavior was observed due to the presence of a large number of shallow traps in Hf-based gate dielectrics. Recent findings, however, suggest that deep traps significantly contribute to the reliability of various Hf-based high-κ gate stacks [2], [3]. In this paper, recent findings related to the charge trapping in Hf-based films will be reviewed. Origin of the deep traps and their dependence on O vacancy formation during dielectric deposition will be discussed. ∆V FB and leakage current dependence on these deep traps will also be outlined. Fig. 1 shows that post-CVS relaxation can quickly recover most of the trapping at shallow levels [1]. But, it is ~25% of the total trapped charge. Trapping at deep levels inhibits fast ∆V T recovery. O vacancies (V ++ /V + /V 0 ) are known to be responsible for deep trapping. Calculations show that V ++ lies at a shallow level within high-κ bandgap [4]. Being a negative-U center, it successively captures two electrons (V ++ + e → V + ; V + + e → V 0 ), and relaxes to deeper levels due to the strong electron-lattice interaction. For high-κ oxides subjected to high temperature PDA (e.g. Hf- silicates), the existence of V ++ /V + is possible due to the calculated defect reactions between interstitials and vacancies (O 0 + V 0 ⇒ O − + V + ; O − + V + ⇒ O − − + V ++ ) [5]. V 0 level was experimentally observed from low temperature measurements [3] assuring the presence of O vacancies in Hf-silicate based films. Substrate hot electron (SHE) injection with incident carrier energies, E inc above the calculated O vacancy formation threshold (~7eV) [3] gives rise to significant electron trapping at stress-induced defects as shown in Fig. 2. E inc ≈q|V s |, where q is electron charge and V s is the substrate bias. Slow post-stress recovery under ‘negative bias’ conditions confirms that O vacancy induced deep defects determine the transient behavior in Hf-silicate based high-κ gate dielectrics. It is further shown that negative-U transition to deep defects is responsible for trap assisted tunneling under substrate injection. A fraction of the injected electrons remains trapped at the deep defects and gives rise to significant ∆V FB . This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-κ gate dielectrics. We thank Dr. B. H. Lee and Dr. R. Choi of International SEMATECH, Austin, Texas for research collaboration. This work was partially supported by a National Science Foundation grant (#ECS-0140584). Fig. 1. ∆V T during CVS and relaxation for NMOS with poly gate/HfSiO 3.5nm stack and 1nm interfacial layer (IL), and W/L=10µm/1µm (from [1]). Relaxation at ‘zero bias’ recovers trapping at shallow levels, which is ~25% of the total trapped charge. Fig.2. ∆V FB during SHE stress, during post-stress recovery under different negative gate bias (V g ) conditions, and after post-recovery relaxation at ‘no bias’ condition for n + -ringed nMOS-Capacitor with 3.5nm HfSiO and 1nm IL (from [3]). 30% of trapping occurs at shallow levels. Electrons detrap slowly from laterally distributed deep traps under ‘bias condition’. ∆V FB < 0 after 54hrs of post-recovery relaxation shows that recovery at negative bias conditions causes hole trapping, which partially reduces ∆V FB during recovery. References: 1. Lee et al., IEEE TDMR, 5, 20(2005). 2. Harris et al., IEEE EDL, 26, 839(2005). 3. Chowdhury et al., submitted to Solid State Electronics, 2005. 4. Torii et al., IEEE IEDM, 5, 129(2004). 5. Foster et al., Phys. Rev. B, 65, 174117(2002). -0.005 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0 200 400 600 800 Bias time (sec) ∆ V FB (V) SHH st. Vg=0.75V Vs= − 9V Vinj= − 11V dtrap Vg= − 1V dtrap Vg= − 1.5V dtrap Vg= −2 V 54hr relaxation@ 'no bias' TiN/HfSiO/IL/p-Si ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 129.81.226.78 Downloaded on 2014-10-12 to IP
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209th ECS Meeting, Abstract #407, copyright ECS
Charge Trapping in High-κ Gate Dielectrics: A Recent Understanding
D. Misra and N. A. Chowdhury
ECE Dept., NJIT, Newark, NJ 07102 [email protected]
Initially it was believed that threshold voltage shift (∆VT), observed during constant voltage stress (CVS), does not represent the reliability of various gate stacks with high-κ dielectrics [1]. It is because the charge trapping is very transient and can be eliminated by applying a reverse direction electric field. This behavior was observed due to the presence of a large number of shallow traps in Hf-based gate dielectrics. Recent findings, however, suggest that deep traps significantly contribute to the reliability of various Hf-based high-κ gate stacks [2], [3]. In this paper, recent findings related to the charge trapping in Hf-based films will be reviewed. Origin of the deep traps and their dependence on O vacancy formation during dielectric deposition will be discussed. ∆VFB and leakage current dependence on these deep traps will also be outlined. Fig. 1 shows that post-CVS relaxation can quickly recover most of the trapping at shallow levels [1]. But, it is ~25% of the total trapped charge. Trapping at deep levels inhibits fast ∆VT recovery. O vacancies (V++/V+/V0) are known to be responsible for deep trapping. Calculations show that V++ lies at a shallow level within high-κ bandgap [4]. Being a negative-U center, it successively captures two electrons (V++ + e → V+; V+ + e → V0), and relaxes to deeper levels due to the strong electron-lattice interaction. For high-κ oxides subjected to high temperature PDA (e.g. Hf-silicates), the existence of V++/V+ is possible due to the calculated defect reactions between interstitials and vacancies (O0 + V0 ⇒ O− + V+; O− + V+ ⇒ O− −
+ V++) [5]. V0 level was experimentally observed from low temperature measurements [3] assuring the presence of O vacancies in Hf-silicate based films. Substrate hot electron (SHE) injection with incident carrier energies, Einc above the calculated O vacancy formation threshold (~7eV) [3] gives rise to significant electron trapping at stress-induced defects as shown in Fig. 2. Einc≈q|Vs|, where q is electron charge and Vs is the substrate bias. Slow post-stress recovery under ‘negative bias’ conditions confirms that O vacancy induced deep defects determine the transient behavior in Hf-silicate based high-κ gate dielectrics. It is further shown that negative-U transition to deep defects is responsible for trap assisted tunneling under substrate injection. A fraction of the injected electrons remains trapped at the deep defects and gives rise to significant ∆VFB. This has the potential to be the ultimate limiting factor for the long-term reliability of Hf-based high-κ gate dielectrics. We thank Dr. B. H. Lee and Dr. R. Choi of International SEMATECH, Austin, Texas for research collaboration. This work was partially supported by a National Science Foundation grant (#ECS-0140584).
Fig. 1. ∆VT during CVS and relaxation for NMOS with poly gate/HfSiO 3.5nm stack and 1nm interfacial layer (IL), and W/L=10µm/1µm (from [1]). Relaxation at ‘zero bias’ recovers trapping at shallow levels, which is ~25% of the total trapped charge. Fig.2. ∆VFB during SHE stress, during post-stress recovery under different negative gate bias (Vg) conditions, and after post-recovery relaxation at ‘no bias’ condition for n+-ringed nMOS-Capacitor with 3.5nm HfSiO and 1nm IL (from [3]). 30% of trapping occurs at shallow levels. Electrons detrap slowly from laterally distributed deep traps under ‘bias condition’. ∆VFB < 0 after 54hrs of post-recovery relaxation shows that recovery at negative bias conditions causes hole trapping, which partially reduces ∆VFB during recovery. References: 1. Lee et al., IEEE TDMR, 5, 20(2005). 2. Harris et al., IEEE EDL, 26, 839(2005). 3. Chowdhury et al., submitted to Solid State Electronics, 2005. 4. Torii et al., IEEE IEDM, 5, 129(2004). 5. Foster et al., Phys. Rev. B, 65, 174117(2002).
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∆V F
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SHH st.
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54hr relaxation@ 'no bias'
TiN/HfSiO/IL/p-Si
) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 129.81.226.78Downloaded on 2014-10-12 to IP
