Dynamic aging simulation of Smart Power circuits

Dynamic aging simulation of Smart Power circuits

Patricia Joris

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 2

Bringing reliability knowledge in the design process

Bringing reliability knowledge in the design process

• Introduction

• Modeling

• Implementation

• Validation

• Conclusion

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 3

Bringing reliability knowledge in the design process

Bringing reliability knowledge in the design process

• Introduction

– When/why is dynamic aging simulation useful?

– Principle of aging simulation

– Mechanism and devices under investigation

• Modeling

• Implementation

• Validation

• Conclusion

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 4

IntroductionIntroductionIntroduction

Two types of failure: (1) Catastrophic failure(2) Wear out

Ids

Vds

Vgs = 12V

Vgs = 8V

Vgs = 4V

Vgs = 2V

65 V 100 V

25 years

10K hours

100 hours

Wear out of DMOS-hot carrier degradation-Gate stress-Reverse bias

Forbidden area: bipolarturn-on for NDMOS

Equi-tfail lines for thermal damage

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 5

IntroductionIntroductionIntroduction

• Two degradation modes:

– Catastrophic failure

• Criterion = maximum defect density, minimum MTTF

• Design limitation : Safe Operating Area

– Wear out

• Criterion = maximum parametric drift

• Design limitation :

– Lifetime Dependent Safe Operating Area

– Dynamic Aging Simulation

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 6

Principle of dynamic aging simulation

Principle of dynamic Principle of dynamic

aging simulationaging simulation

• Monitor aging per device • Schematic back annotation• Aged model cards

• Netlist

• Stimuli

• Operational time tstress

• Operational temperature T

Transient circuit

simulation

Device Models

Reliability Models

•Key operation characteristic drift:

•Compact model parameter drift:

dt)T,t),t(Vg),t(Vd(AP

stresst

⋅=∆ ∫

( )( )

( )Pcorrp

....

Pcorrp

Pcorrp

n

2

1

∆=∆

∆=∆

∆=∆

Aged performance

Circuit simulation

•Identify weak spots

•Verify relevant reliability criteria

•Fully integrated, fastand easy

Learn about good design practices

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 7

Mechanism and devices under investigation

Mechanism and devices Mechanism and devices

under investigationunder investigation

Bosch:

•lateral NDMOS

•0.35um based CMOS

•Vds,max = 40V

•Vgs,max = 3.3V

Psubstrate

Ntub

Burried layer

Hot carrier injection

P+ N+ N+

PbodyNwell

B S G D

FOX

AMIS:

•lateral NDMOS

•0.7um based CMOS

•Vds,max = 40V

•Vgs,max = 12V

Pepi

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 8

Model 1: Key operation characteristic (Ron) drift

Model 1: Key operation Model 1: Key operation

characteristic (Rcharacteristic (Ronon) drift) drift

• Monitor key operation characteristics during DC stress experiments.

• Modified Goo model :

Age ~

• Step 1 : Extraction of α and β : non-linear least square fit

Cost function

nnnn2222

nnnn1111

on,0on,0on,0on,0onononon

AgeAgeAgeAgeCCCC1111AgeAgeAgeAgeCCCC

RRRRΔRΔRΔRΔR

⋅+

⋅=

( ) ( )∑ ≠

βαβα

∂

∂

−

∂

∂

⋅⋅−⋅⋅

ji),j,i(meas

jj,dj,subii,di,sub

measmeas

tIItII

jjjjon,0on,0on,0on,0ononononiiiion,0on,0on,0on,0onononon

ttttRRRR

ΔRΔRΔRΔR

ttttRRRR

ΔRΔRΔRΔR

ttttIIIIIIII ββββdddd

ααααsubsubsubsub ⋅⋅

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 9

Model 1: Key operation characteristic (Ron) drift

Model 1: Key operation Model 1: Key operation

characteristic (Rcharacteristic (Ronon) drift) drift

• Step 2 : Extraction of C1, C2 and n : non-linear least square fit

Cost function

– AMIS : C1, C2, n are Vg dependent

– Bosch : Fixed C1, C2 and n

• Step 3 : Polynomial fit through C1, C2 and n (AMIS)

))))RRRRΔRΔRΔRΔRmeasmeasmeasmeas

AAAACCCC1111AAAACCCC((((

iiiion,0on,0on,0on,0onononon

iiii nnnniiii2222

nnnniiii1111

−

⋅+

⋅∑

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 10

Model 1: Key operation characteristic (Ron) drift

Model 1: Key operation Model 1: Key operation

characteristic (Rcharacteristic (Ronon) drift) drift

• AMIS device:

RMS error = 3.3%

Step 1Step 2+3

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 11

Model 1: Key operation characteristic (Ron) drift

Model 1: Key operation Model 1: Key operation

characteristic (Rcharacteristic (Ronon) drift) drift

• Bosch results:

RMS error = 5.05%

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 12

Model 2: Compact model parameter drift

Model 2: Compact model Model 2: Compact model

parameter driftparameter drift

• Two methods to extract compact model parameters from key operation characteristics:

Neural Network

Approach

Controlled Source

Approach

Conclusion:

ononononserserserser ΔRΔRΔRΔRΔRΔRΔRΔR ∝

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 13

ImplementationImplementationImplementation

• Operation time and sampling period:

Operation time = period * #pulses

period

period

period

Simulation time

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 14

Implementation Implementation Implementation

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 15

ImplementationImplementationImplementation

• After each simulation event i, for each transistor j:– Calculate the Age rate of the last simulation interval δtj

– At the end of the operation time, the age of transistor j due tothe condition during this interval is

– Calculate the contribution of the condition to the total degradation

– Calculate the shift of the resistivity from the shift of the on-resistance:

( )( ) j,i

j,i

njij,ij,i,2

njij,ij,i,1

j,ipulses_rtrate_ageC1

pulses_rtrate_ageCP

⋅δ⋅⋅+

⋅δ⋅⋅=∆

βα⋅= j,ij,ij,i IdIsubrate_age

jij,ij,ij,i pulses_rtIdIsubage ⋅δ⋅⋅=βα

onres RCteR ∆⋅=∆

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 16

ImplementationImplementationImplementation

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 17

Validation (DC)Validation (DC)Validation (DC)

• Validation:

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 18

Validation (AC)Validation (AC)Validation (AC)

• Aging monitor:Experiment 1:

Vd=40V, Vg=0 – 12V, fVg =12.5KHz,

duty cycle = 80%, inductive load

Experiment 2:

Vd=40V, Vg = 0 – 12V, fVg =10KHz,

duty cycle = 50%, resistive load

Cum. stress duration =

88h

Cum. stress duration =

35h

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 19

Validation (AC)Validation (AC)Validation (AC)

• Aged performance:

Conclusion:

Resistive load: ∆∆∆∆Id,lin, sim = 1.4% vs ∆∆∆∆Id,lin, meas = 1.15%

Inductive load: ∆∆∆∆Id,lin, sim = 1.8% vs ∆∆∆∆Id,lin, meas = 1.55%

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 20

ConclusionConclusionConclusion

• Dynamic aging simulation is used to be bring reliability knowledge on wear out mechanisms in the design process

• The advantages of dynamic aging simulation are

– Reliability criteria in line with the application can be verified.

– Weak point in the design are indicated and this helps for identifying design failure mechanisms.

– The aged circuit simulation learns designers about good design practices.

– The tool is integrated in the design environment which makes it fast and easy to use.

• Degradation models and aged model cards are constructed based on DC data.

• The models are implemented in the software and are able to predict the shift of the degradation monitor and the aged devicebehavior after DC and AC stress experiments.

ESSDERC ’06, Montreux ROBUSPIC Workshop P. Joris – Slide 21

AcknowledgementsAcknowledgementsAcknowledgements

Many thanks to…

• C. Maier, H. Heinisch (Robert Bosch) and O. Jovic(UZag) for the Bosch contributions

• A. Baguenier (Cadence) for his participation in the coding of the reliability models

• Y. Singh (EPFL) for modeling and implementation of Isub

• S. Frère (AMIS) for the extraction of aged model parameters

• IWT Compose team for providing valuable

measurement data on the AMIS device

Questions?Questions?Questions?