Analog and Mixed-Signal Design for SOC in Emerging Digital...

EE 505

Lecture 25

SAR ADC Design

Oversampled ADCs

2

Aperture Uncertainty

1REF

IN

VV ( sinωt)

2

n

1

ω2T

Example: If fCLK=200MHz, n=14 determine the aperture uncertainty

05

14

14.86E-14 . psec

2 2E8 2T

Aperture uncertainty requirements can be very stringent !

Review from Last Lecture

3

Elimination of Input S/HStage 1

<b1>

n1

r1 Stage 2

<b2>

n2

r2 Stage k

<bk>

nk

rk Stage m

<bm>

nm

rmXIN

S/H

nPipelined Assembler

(Shift Register Array) XOUT

CLK

Stage 1

<b1>

n1

r1 Stage 2

<b2>

n2

r2 Stage k

<bk>

nk

rk Stage m

<bm>

nm

rmXIN


(Shift Register Array) XOUT

CLK

Advance sampling clock a little so that sample is taken at quiet time but not too

much to loose over-range protection

• This simply skews the sampling times

• Probably need to bootstrap the input sampling switch

• Bottom plate sampling


4

Fully Differential Architectues

• All even-ordered spectral components are eliminated with fully-differential

symmetric structures

• Common mode noise is rejected with fully-differential symmetric structures

Second-order spectral component is often most significant contributor to

SFDR and THD limitations in single-ended structures

Noise from ADC and other components, coupled through the substrate,

often source of considerable noise in an ADC

Almost all implementations of Pipelined ADCs are fully-differential

Straightforward modification of the single-ended concepts discussed here

Authors often present structures in single-ended mode and then just mention

that differential structure was used

Modest (but small) increase in area and power for fully differential structures

Signal level increases by factor of 2 and device noise typically increases by

√2 as well


5

Pipelined Data Converter Design

GuidelinesIssue

1. ADC offsets, Amp Offsets, Finite Op Amp

Gain, DAC errors, Finite Gain Errors all

cause amplifiers to saturate

2. Op Amp Gain causes finite gain errors

and introduces noninearity

3. Op amp settling must can cause errors

4. Power dissipation strongly dependent

upon GB of Op Amps

5. Choice of FB Amplifier Architecture

seriously impacts performance

6. Correct interpretation of αk’s is critical

Strategy1. Out-range protection circuitry will remove this

problem and can make pipeline robust to these

effects if αk’s correctly interpreted

a) Use Extra Comparators

b) Use sub-radix structures

2. a) Select op amp architecture that has

acceptable signal swing

b) Select gain large enough at boundary of range to

minimize nonlinearity and gain errors

3. Select GB to meet settling requirements

(degrade modestly to account for slewing)

4. Minimize CL, use energy efficient op amps, share or

shut down op amp when not used,scale power in

latter stages, eliminate input S/H if possible,

interleave at high frequencies. Good (near optimal)

noise distribution strategy should be followed.

5. Bottom plate sampling, bootatrapping, clock

advance to reduce aperature uncertainty,critical GB,

parasitic insensitivity needed, β dependent upon

architecture and phase, compensation for worst-

case β, TG if needed

6. a) Accurately set αk values

b) Use analog or digital calibration


6

Pipelined Data Converter Design

GuidelinesIssue

7. Sampling operation inherently introduces a

sampled-noise due to noise in resistors

8. Signal-dependent tracking errors at input

introduce linearity degradation

9. Aperature uncertainty can cause serious errors

10. Input S/H major contributor to nonlinearity and

power dissipation

11. Data converters often have stringent SNR and

SNDR requirements

Strategy7. Select the capacitor sizes to meet noise requirements.

Continuous-time noise can also be present but is often

dominated by sampled noise. Size switches to meet

settling and noise requirements. Excessive GB will

cause noise degradation in some applications, include

noise from all stages (not just first stage) .

8. Bootstrapped switches almost always used at input

stage. Must avoid stressing oxide on bootstrapped

switches

9. Since latency usually of little concern, be sure that a

clean clock is used to control all sampling.

10. Eliminate S/H but provide adequate over-range

protection for this removal. Reduces power dissipation

and improves linearity!

11. Use fully differential structures to obtain dramatic

improvements in SNR and SNDR


7

Cyclic (Algorithmic) ADCs

Stage 1

<b1>

n1,n1,...n1

r1,r2,.rm-1

<b2> <bm>

XINS/H


(Shift Register Array)

CLK

Stage 1

n1

r

XINS/H

n

Pipelined Assembler


CLK

Stage 1

n1

rXIN

n

Pipelined Assembler


CLK

Can bypass bootstrap after initial sample is taken


8

SAR ADC

• DAC Controller stores estimates of input in Successive

Approximation Register (SAR)

• At end of successive approximation process, ADC output is in SAR

• Eliminates the power-consuming amplifiers of the pipelined ADC

• Much slower than pipelined ADC

• S/H at the input is essential

• Can have excellent power performance

• Widely used structure with renewed attention in recent years

VIN

n

CLK

DAC

Controller

VREF

SampleHold

DAC


9

SAR ADCVIN

n

CLK

DAC

Controller

VREF

SampleHold

DAC

C1

S1

C2

S2

C3

S3

Cn

Sn

Cn

RST

VRFF

VOUT

Charge Redistribution DAC could be used in SAR ADCs

• Capacitors usually binary weighted

• With this DAC, typical common-mode input required for comparator

• Standard S/H also required


10

SAR ADC VIN

n

CLK

DAC

Controller

VREF

SampleHold

DACAlternate Charge Redistribution DAC

• During sampling phase, input is sampled on all capacitors

• During successive approximation process, capacitors are alternately connected

to ground or VREF

• Voltage on common node will converge to 0

• Comparator is always comparing to ground thus reducing common-mode

nonlinearity errors

• Note input sample is not held independently throughout the entire conversion

process

• Bootstrapped switch is critical during sampling phase

• Parasitic capacitances on VC node do not affect final output (Bottom plate)

• Major source of power dissipation is in the charge redistribution process

VREF

2n-1

C 2n-2

C 2n-3

C 2C C C

VIN

DAC

ControllerφS φS φS φS φS φS φS

d1 d2 d3 dndn-1

φXg1 g2 g3

gngn-1

VC

C1 C2 C3 CnCn-1

i ig = d


SAR ADC

• Single-ended VREF

• Single-ended Differential Input +VREF, -VREF

• Differential Input

• Concepts are often expressed in single-ended structures

• Fully differential structures widely used

• Distinction between reference voltages often not clearly stated

Is Common-Mode input 0 or VREF/2?

Is maximum input VREF, 2VREF or 4VREF:

0

VREF

Inpu

t R

ange

0 IN REFV V

Single Ended

0

VREF1

Inp

ut

Ran

ge1 1REF IN REFV V V

Single EndedSymmetric

-VREF1

0

VREF2

Inp

ut

Ran

ge

2 22 2REF IND REFV V V

Fully Differential

-VREF2

2REF

CM

VV

VCMVCM

0CMV

13

Example of Fully Differential Implementation

14

Another example of Fully Differential Implementation

with different switching sequence and different

references.

SAR ADCCharge Redistribution ADC with reduced charge redistribution energy

Goal: Reduce unnecessary switching inherent in the original process by first

switching all capacitors to VREF and then returning to ground if test fails.

Goal: Only switch if needed!

Reduced Switching

Standard Switching

Samples input on array connected

between VIN and VREF

Only change state if output must

be decreased

For 10-bit ADC, reported switching energy

and total capacitance reduced by about

81% and 50%, respectively

Does not consider kT/C noise

since resolution is small

550 (April 2017 I believe)

788 (4/17/2019)

SAR ADCCharge Redistribution ADC with reduced charge redistribution energy

Goal: Only switch if needed!

SAR ADC

SAR ADCCharge Sharing ADC with reduced charge redistribution energy

Goal: Have only passive switching

SAR ADCLots of ongoing activity in SAR ADCs

Data Converter Type Chart

Speed

Re

so

lutio

n

4

8

12

16

20

24

1K 10K 100K 1M 10M 100M 1G 10G

Oversampled

Nyquist

Over-Sampled Data Converters

• Single-bit

• Multi-bit

• First-order

• Higher-order

• Continuous-time

General Classes

Nyquist RateTSIG

Sampling Clock

t

Over-Sampled

Quantizer Levels

Effective Decimated

Quantizer Levels

Sampling Clock

Effective Sampling Clock

Over-sampling ratios of 128:1 or 64:1 are common

Dramatic reduction in quantization noise effects

Limited to relatively low frequencies

Recall:

MatLab Results

fSIG=50Hz

fNYQ=100Hz

fSAMP=2.3KHz

Oversampled: 23:1

Quantization Effects

Simulation environment:

NP=23

fSIG=50Hz

Recall:

Quantization EffectsRes = 4 bits

fSIG=50Hz

fNYQ=100Hz

fSAMP=1113KHz

Oversampled: 11:1

Recall:

LSB RMSE

12X


Quantization noise is much lower but still significant

fSIG=50Hz

fNYQ=100Hz

fSAMP=1113KHz

Oversampled: 11:1

LSB RMSE

12X

Recall:


Compared to the previous slide, it appears that the quantization noise has gone

down but really hasn’t

LSB RMSE

12X

fSIG=50Hz

fNYQ=100Hz

fSAMP=8904KHz

Oversampled: 89:1

Recall:


Can any additional useful information about the input be obtained since we have

many more samples than are needed?

LSB RMSE

12X

fSIG=50Hz

fNYQ=100Hz

fSAMP=8904KHz

Oversampled: 89:1

Recall:

Over-Sampling

Res = 10 bits

What would happen if we break the 4096 samples into groups of 20 samples and form?

LSB RMSE

12X

fSIG=50Hz

fNYQ=100Hz

fSAMP=8904KHz

Oversampled: 89:1

XINADC

nXOUT

20

1

1ˆ ( 20 ) 2020

OUT SAMP OUT SAMP SAMP

j

X k T x jT kT

• Though the individual samples have been quantized to 10 bits, the arithmetic operations

will have many more bits

• The effective sampling rate has been reduced by a factor of 20 but is still over 4 times the

Nyquist rate

• Has the quantization noise been reduced (or equivalently has the resolution of the ADC

been improved?

• Is there more information available about the signal?

? RMSE

Over-Sampling

Res = 10 bits

Since the quantization noise is at high frequencies, what would happen if filtered the

Boolean output signal?

LSB RMSE

12X

fSIG=50Hz

fNYQ=100Hz

fSAMP=8904KHz

Oversampled: 89:1

XINADC

nXOUT

0

( )m

OUT SAMP j OUT SAMP

j

Y kT a x k jT

XINADC

n

XOUT Digital Filter n=?

YOUT

0 1

( )m h

OUT SAMP j OUT SAMP j OUT SAMP

j j

Y kT a x k jT b Y k jT

Or

? RMSE

Over-Sampling

Res = 10 bits

Since the quantization noise is at high frequencies, what would happen if filtered and

decimated the Boolean output signal?

LSB RMSE

12X

fSIG=50Hz

fNYQ=100Hz

fSAMP=8904KHz

Oversampled: 89:1

XINADC

nXOUT

0

0 1

( )

( )

m

OUT SAMP j OUT SAMP

j

m h

OUT SAMP j OUT SAMP j OUT SAMP

j j

Y kT a x k jT

Y kT a x k jT b Y k jT

XINADC

n


YOUT

Decimatorn=?

ZOUT

? RMSE

Over-Sampling

LSB RMSE

12XXIN

ADCn

XOUT

XINADC

n


YOUT

Decimatorn=?

ZOUT

ADCn

XOUT Sliding Averager n=?

XINYOUT(mTSAMP)

? RMSE

? RMSE

• What is the overhead?

• What is the performance potential?

• How can these or related over-sampling approaches be designed?

• Though this approach may help quantization noise, will not improve ADC linearity

Over-SamplingXIN

ADCn


YOUT

f0

f

0.5fs

Quantization Noise122

LSB

S

X

f

f0

f

0.5fs

1

j TH e

f0

f

0.5fs

Quantization Noise

122

LSB

S

X

f

0

1

2SfOSR

f

fS=fSAMP

With ideal lowpass filter with band-edge at f0

1

12

LSBQrms

VV

OSR

For sinusoidal input with p-p value VREF

6.02 1.76 10log( )SNR n OSR

Improvement of 3dB/octave or 0.5bits/octave

Types of ADCsOver-sampled ΔΣ ADC (Delta-Sigma)

XIN Filter

DAC

XOUT

nADC

Decimator /

Filter

n1

CLK

Oversampled ADC

• Anti-aliasing filter at the input (not shown), if needed, to limit bandwidth of

input signal

• ADC is often simply a comparator

• CLK is much higher in frequency than effective sampling rate (maybe

128:1 though lower OSR also widely used)

• Can obtain very high resolution but effective sampling rate is small

• With clever design, this approach can reduce quantization effects

and improve linearity

Types of ADCsOver-sampled ΔΣ ADC (Delta-Sigma)

XIN Filter

DAC

XOUT

nADC

Decimator /

Filter

n1

CLK

Oversampled ADC

• Linearity performance almost entirely determined by the of DAC

• 1-bit DAC (i.e. only a comparator for ADC) is inherently linear and

widely used

• 20-bit linearity is achievable without any trimming using 1-bit DAC

Example: To obtain 16-bit linearity with a 10-bit DAC, the 10-bit DAC must be

linear to at least the 16-bit level. This would usually require tedious trimming

of the DAC

End of Lecture 25

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