AN 49 Multiple Output Design Considerations for the … · · 2008-12-28Multiple Output Design...
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DECEMBER 1995
Application Note 42031Multiple Output Design Considerations for the ML4863
CURRENT SENSE RESISTOR VALUE
4a. Determine the value of the sense resistor, RSENSE5:
R
V
5 V
150mV
I
V
20 V I
SENSE5
IN(MIN)
IN(MIN) 5V(MAX)
IN(MIN)
IN(MAX) 5V(MAX)
=
+× +
× ×
×η
4b. Determine the value of the other sense resistors,RSENSEn:
RV
5VR
SENSEn
n
SENSE5=
TRANSFORMER DESIGN
5. Specify the minimum primary inductance:
L(25x10 ) V R
2PRI(MIN)
6
IN(MAX) SENSE5=
× ×−
6. Calculate the minimum inductor current ratingrequired. The peak inductor current is determined by thefollowing formula:
I220mV
R
V (2.5 10 )
LL(PEAK)
SENSE5
IN(MAX)
6
PRI
= +× × −
7. Specify the DC winding resistance for thetransformer. A good rule of thumb for the primaryresistance is to allow 5 mΩ of resistance for each µH ofinductance. For the secondary windings, the resistanceshould be on the order of the sense resistor value.
8. Determine the transformer turns ratio:
N :N 1:V5VPRI OUTn
OUTn=
INPUT CAPACITOR SELECTION
The choice of the input capacitor is based on its ripplecurrent and voltage ratings rather than its capacitor value.The input capacitor should be a low ESR type and locatedas close to the primary winding of the transformer aspossible.
INTRODUCTIONThe ML4863 is designed for flyback operation with aminimum number of external components. Highefficiency is maintained over a wide load range with theuse of synchronous rectification and pulse frequencymodulation. The circuit is ideal for power conversion frombattery packs whose voltage varies both above and belowthe 5V output voltage.
It is possible to modify the single output circuit of theML4863 to meet a wide range of applications withmultiple output voltage requirements. By simply addingan additional winding to the transformer, and theappropriate FET, resistor, and capacitor, a second outputvoltage can be generated without a significant increase incost or space.
This application note provides the user with a step-by-stepprocedure to design multiple output converters using theML4863.
DESIGN CONSIDERATIONSThe following design procedure results in values that areclose enough for a magnetics manufacturer to do an initialtransformer design and to build a breadboard to prove outthe design. The formulas are not intended to give finalvalues, but to provide a good starting point.
DESIGN SPECIFICATIONS
1. Define the design specifications:• The minimum input voltage.• The maximum input voltage.• The output voltage for each output.• The maximum output current for each output.
2. Calculate the maximum output power:
P V I V I
V I
TOT OUT1 OUT1(MAX) OUT2 OUT2(MAX)
OUTn OUTn(MAX)
= × + × +
+ ×
....
3. Calculate the maximum output current referencedto a 5V output:
I5V(MAX) = PTOT
5V
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Application Note 49
2 REV. 1.0 10/25/2000
9a. Calculate the input capacitor’s ripple current.
( ) ( ) ( )
I
DCA AI I
3DC4
A I
where,
A220mV
R
and,
DC5V
5V V
RMS(CIN )
2L(PEAK) L(PEAK)
2
L(PEAK)
21/ 2
SENSE5
IN(MIN)
=
+ +− +
=
=+
9b. Derate the capacitor voltage rating by 20% to 50%for aluminum electrolytic types and 100% for tantalumtypes.
In high current applications it may be necessary to add asmall 0.1 µF ceramic capacitor to bypass VIN (pin 1) rightat the ML4863.
OUTPUT CAPACITOR SELECTION
In general, the ESR and voltage rating requirementsdetermine the capacitor value rather than the capacitancerequired for loop stability. Low ESR capacitors arerecommended for all input and output capacitors due tothe high switch currents in a flyback converter. The AVX“TPS” series and the Sprague “593D” series of tantalumcapacitors are a good choice.
10a. Calculate the minimum output capacitancerequired:
C I5V V
5V
2.5 10
Vn OUTn(MAX)
IN(max)
6
OUTn
= ×+
×
×−
∆
10b. Estimate the required ESR of the output capacitorusing:
RV R
150mVESRn
OUTn SENSEn≤×∆
Usually the ESR will be the determining factor in theselection of tantalum and aluminum electrolyticcapacitors.
SELECTING MOSFET SWITCHES
The switching FETs must be logic level types with the ONresistance specified at VGS = 4.5V. In general, the ONresistance - gate charge product provides a good figure ofmerit by which to compare various MOSFETs, the lowerthe figure the better.
The internal gate drivers of the ML4863 can drive over 100nC of total gate charge, but 60 nC to 70 nC is a morepractical limit to ensure good switching times.
The drain to source breakdown voltage ratings aredetermined as follows:
11a. Determine the primary side switch FET’s VDS rating.
( )V V 5V FDS(PRI) IN(MAX) DS= + ×
11b. Determine the output synchronous rectifier FET’sVDS rating.
V 2 V FDS(OUTn) OUTn DS= × ×
A safety derating factor, FDS, in the range of 1.5 to 2.0 isrecommended due to the voltage spikes caused by theleakage inductance of a transformer. Note that theleakage inductance of a winding increases with thenumber of turns. For a more reliable design look for FET’sthat are avalanche rated.
In high current applications, the MOSFET’s powerdissipation often becomes a major design factor. The I2Rlosses generate the largest portion of heat in the FETpackage. Make sure that the MOSFETs are within theirrated junction temperature at the maximum ambienttemperature by calculating the temperature rise using thethermal resistance specifications.
12a. The worst case power dissipation for the primaryside switch is determined as follows.
P I R
where,
I
5V5V V
A AI I
3
and,
A220mVR
D(PRI) RMS(PRI)2
DS(ON)
RMS(PRI)
IN(MIN)
2L(PEAK) L(PEAK)
21/2
SENSE5
= ×
=
+
+ +
=
12b. The worst case power dissipation for the outputswitches are determined as before using the IRMS(OUTn).
P = I R
where,
I
BV
5V V
A AI I
3
B5V
V
D(OUTn) RMS(OUTn)2
DS(ON)
RMS(OUTn)
IN(MAX)
IN(MAX)
2L(PEAK) L(PEAK)
21/2
OUTn
×
=
×+
+ +
=
PC BOARD LAYOUT CONSIDERATIONSFigure 4 shows a sample board layout. Proximity ofpassive devices and adequate power and ground planesare critical for reliable operation of the circuit. In general,use the top layer for the high current connections and thebottom layer for the quiet connections such as GND.
Application Note 49
REV. 1.0 10/25/2000 3
Some more specific guidelines follow.
1. The connection from the current sense resistor toSENSE should be made by a separate trace and located asclose to the lead of the resistor as possible. The tracelength from the SENSE resistor to the ML4863 should bekept as short as possible.
2. The VCC bypass capacitor needs to be located closeto the ML4863 for adequate filtering of the IC’s internalbias voltage.
3. The trace lengths from the input and outputcapacitors to the transformer, from the transformer to theFETs, and from the FETs to the SENSE resistors should beas short as possible to minimize noise and ground bounce.
4. The high current ground paths need to be keptseparate from the signal ground paths. The GNDconnection should be made at a single-point star ground.It is very important that the ground for the ML4863 groundpin (pin 8) be made using a separate path.
DESIGN EXAMPLE1. Define the design specifications:
• VIN(MIN) = 4.0V.• VIN(MAX) = 6.0V.• 5VOUT at 400 mA (MAX).• 12VOUT at 100 mA (MAX).• 3.3VOUT at 200 mA (MAX)..
2. Calculate the maximum output power:
P
5V 400mA 12V 100mA 3.3V 200mA
P 3.86W
TOT
TOT
=× + × + ×
=
3. Calculate the maximum output current referencedto a 5V output:
I3.86W
5VI 772mA
5V(MAX)
5V(MAX)
=
=
CURRENT SENSE RESISTOR VALUE
4a. Determine the value of the sense resistor, RSENSE5:
R
4V5 4V
150mV772mA
4V20 6V 772mA
0.80
SENSE5 =
+× +
× ×
×
R 84.4mSENSE5 = Ω
so choose 90 mΩ
4b. Determine the value of the other sense resistors:
R3.3V5V
84.4m = 55.7mSENSE3.3 = Ω Ω
so choose 60 mΩ
R12V5V
84.4mW = 203mSENSE12 = Ω
so choose 200 mΩ
TRANSFORMER DESIGN
5. Specify the minimum primary inductance:
L(25x10 ) 6 90 10
2L 6.75 H
PRI(MIN)
6 -3
PRI(MIN)
=× × ×
=
−
µ
Since this is a minimum specification a good starting pointof 1.5X is recommended, or 10 µH.
6. Calculate the minimum inductor current ratingrequired.
I220mV90m
6V (2.5 10 )10 10
I 2.59A
L(PEAK)
6
-6
L(PEAK)
= +× ×
×=
−
Ω
7. Specify the DC winding resistance for thetransformer.
DCR5m
H10 H 50m
DCR 90m
DCR 60m
DCR 200m
5
3.3
12
= × =
≅≅≅
ΩΩ
ΩΩΩ
µµ
8. Determine the transformer turns ratio:
N :N 1:5V5V
1:1
N :N 1:3.3V5V
1:0.66
N :N 1:12V5V
1:2.40
PRI 5
PRI 3.3
PRI 12
= =
= =
= =
Application Note 49
4 REV. 1.0 10/25/2000
and,
C115
2.5 10F3.3
6
= ×
×
×=
−
0 20 06
18..
µ
RmV150mV
mESR3.3 ≤×
≤60 0 06
24. Ω
Ω
SELECTING MOSFET SWITCHES
11a. Determine the primary side switch FET’s VDS rating.
( )V 6V 5V 2 22VDS(PRI) = + × =
11b. Determine the output synchronous rectifier FET’sVDS rating:
V 2 5V 2 20V
V 2 V 2 V
V 2 V 2 V
DS(OUT5)
DS(OUT3.3)
DS(OUT12)
= × × =
= × × == × × =
3 3 13
12 48
.
12a. Use the worst case power dissipation for theprimary side switch to determine the ON resistance asfollows:
( )
RP
I1W
1.88 A
where,
I5V
5V V
22090
3
I 1.88A
DS(ON)
D(PRI)
RMS(PRI)2 2
RMS(PRI)
212
RMS(PRI)
= = =
=+
+ +
=
+ +
=
0 28
4
22090
2 59 2 59
59
5 98 6 33 6 713
2
12
.
. .
. . .
Ω
12b. Use the worst case power dissipation for the outputside switches to determine the ON resistance as follows:
( )
R =P
I1W
1.86 A
where,
I
6V5V V
22090
22090
3
I6V
11V 31.86A
DS(ON)5
D
RMS(OUT5)2 2
RMS(OUT5)
21/2
RMS(OUT5)
1/2
= =
=
×+
+ +
=
+ +
=
0 29
55 6
2 59 2 59
5 98 6 33 6 71
2
.
. .
. . .
Ω
INPUT CAPACITOR SELECTION
9a. Calculate the input capacitor’s ripple current.
( )
( )( )
I
0.56
2.44
3
0.56
42.44
I 1.25A
where,
A220mV
R
and,
DC5V
5V V
RMS(CIN )
2
2
1/ 2
RMS(CIN )
SENSE5
IN(MIN)
=
×
+ × +− +
=
= = =
=+
=+
=
2 44 2 59 2 592 59
220
902 44
5
5 40 56
2. . ..
.
.
9b. Derate the capacitor voltage rating by 20% to 50%for aluminum electrolytic types and 100% for tantalumtypes.
In order to meet the ripple current and voltage rating, two33 µF, 20V tantalum capacitors were chosen for the inputfiltering.
OUTPUT CAPACITOR SELECTION
10a. Calculate the minimum output capacitance requiredfor the 5V output:
C5 = 0.4 × ( 5V + 6V ) × 2.5 × 10-4 = 22 µF
5V 0.1
10b. Estimate the required ESR of the output capacitorusing:
RESR5 ≤ 100 mV × 0.09Ω ≤ 60 mΩ150 mV
So use two 100 µF, 10V tantalum capacitors to meet boththe capacitance and ESR requirements for the 5V output.
Repeating the calculations for the other outputs:
C12 = 0.1 × ( 11 ) × 2.5 × 10-6 = 4.6 µF
5 0.12
RESR12 ≤ 120 mV × 0.2Ω ≤ 160 mΩ150 mV
Application Note 49
REV. 1.0 10/25/2000 5
Repeating the calculations for the other outputs:
R =P
I
1W
2.82 A
where,
I6V
11V 3
I A
and,
R =P
I
1W
0.775 A
where,
I6V
11V 3
I A
DS(ON)3.3
D
RMS(OUT3.3)
2 2
RMS(OUT3.3)
1/2
RMS(OUT3.3)
DS(ON)12
D
RMS(OUT12)
2 2
RMS(OUT12)
1/ 2
RMS(OUT12)
= =
=
+ +
=
= =
=
+ +
=
0 13
5
3 3
5 98 6 33 6 71
2 82
166
5
12
5 98 6 33 6 71
0 775
.
.
. . .
.
.
. . .
.
Ω
Ω
Using the calculations to specify two Dual FETs, we canchoose a 50V, 0.28 ohm Dual FET for the primary and 12Vswitches, and a 20V or 30V, 0.13 ohm Dual FET for the3.3V and 5V switches.
PERFORMANCE DATAUsing the selected devices and values from the abovecalculations the circuit of Figure 1 was built and tested.This section discusses the design trade-offs made and thetest results. See Tables 1 and 2 for the parts list of the finalvalues used.
CURRENT SENSE RESISTORS
The sense resistor needs to represent the total resistanceseen by each output to ground. The sense resistor networkis built as shown in the schematic of Figure 1. First,connect the lowest value sense resistor between groundand the corresponding synchronous rectifier for it’s output;or in this case the 3.3V output: R3 = RSENSE3.3 = 60mΩ.Next, determine the next largest value sense resistor; or forthis example the 5V output: RSENSE5 = 90 mΩ. Since thesense resistor R2 is in series with R3 to ground, the valueof R2 = RSENSE5 - R3 = 30 mΩ. R2 is connected betweenR3 and the 5V synchronous rectifier. Finally, since the12V sense resistor is in series with R2 and R3 to ground,the value of R1 = RSENSE12 - R2 - R3 = 110 mΩ.However, a 110 mΩ resistor was not available forbreadboarding, so a 100mΩ resistor was used instead, andconnected between R2 and the 12V synchronous rectifier.
TRANSFORMER DESIGN
The transformer was built using a TDK PC40ER14.5/6-Zcore and bobbin set. and wound as follows:• 1st: 9T of 31 AWG magnet wire; start pin 1, end pin 10• 2nd: 9T of 28 AWG magnet wire; start pin 2, end pin 9• 3rd: 6T of 28 AWG magnet wire; start pin 3, end pin 8• 4th: 21T of 31 AWG magnet wire; start pin 4, end pin 7• 5th: 9T of 31 AWG magnet wire; start pin 5, end pin 6Gap the core for 11 µH + 10%
Note the order of the windings, with the primary windingsplit between the 1st and 5th windings. This constructiontraps the secondary windings in between the primaries tolower the leakage inductance and to minimize the DCwinding resistance.
The actual DC winding resistance versus the specifiedvalues is tabulated below.
Table 3: Winding Resistance Comparison
Winding Specified DCR Actual DCR
5v 50 mΩ 65 mΩ
3.3V 60 mΩ 46 mΩ
12V 200 mΩ 345 mΩ
The table indicates that the windings have been optimizedto meet the specified winding resistance numbers. The 12Vwinding resistance could have been lowered to improvethe cross regulation, but only at the expense of an increasein the primary winding resistance and therefore a loss inefficiency, or an increase in resistance of one of the othersecondary windings and a corresponding degradation incross regulation.
MOSFET SWITCHES
A National Semiconductor NDS9955 was selected for theprimary and 12V output switches. The NDS9955 is ratedfor 50V and has an RDS(ON) = 0.2 ohms.
A Motorola MMFD3N03 was selected for the 3.3V and 5voutput switches. The MMDF3N03 is rated for 30V and hasan RDS(ON) = 0.075 ohms.
The selected FET’s meet the design parameters of theprevious section. If lower RDS(ON) FET’s are used the crossregulation and the efficiency can be improved.
TEST RESULTS
The cross regulation and efficiency test results are given inTables 4 to 6. Typical switching waveforms are shown inFigures 2 and 3.
Application Note 49
6 REV. 1.0 10/25/2000
VIN
SENSE
ON/OFF
VOUT
GND
OUT2
OUT1
VCC
8
7
6
5
1
2
3
4
ML4863
U1
C233 µF20V
+C133 µF20V
+
Vin
ON/OFF
GND
C31 µF20V
R30.06 Ω
R20.03 Ω
R10.10 Ω
Q1A
Q1B Q2A Q2B
Q2 = MMFD3N03
1
10
5
6
7
4
9
2
8
3
T1
Q1 = NDS9955
C533 µF20V
+C433 µF20V
+
C7100 µF6.3V
+C6100 µF6.3V
+
C10, 11, 12, 13 = 100 µF, 6.3V
+
C10
+ ++
Vout 12V, 0.25A
Vout 5V, 1A
Vout 3.3V, 1A
C11 C13C12
Figure 1 — Test Circuit Schematic
Application Note 49
REV. 1.0 10/25/2000 7
TABLE 1: PARTS LIST
ITEM DESIGNATOR QTY DESCRIPTION MANUFACTURER
Capacitor
1 C1, C2 2 33 µF, 20V, Tantalum SMD Sprague 593D Series
AVX TPS Series
2 C3 1 1 µF, 25V, Ceramic, 1206 surface mount Various
3 C4, C5 2 33 µF, 20V, Tantalum SMD Sprague 593D Series
AVX TPS Series
4 C6, C7 2 100 µF, 6.3V, Tantalum SMD Sprague 593D Series
AVX TPS Series
5 C10, C11, 4 100 µF, 6.3V, Tantalum SMD Sprague 593D Series
C12, C13 AVX TPS Series
Resistor
6 R1 1 100 mΩ, 1/2W. 1%, 2010 surface mount Dale WSL Series
IRC LRC Series
7 R2 1 30 mΩ, 1/2W. 1%, 2010 surface mount Dale WSL Series
IRC LRC Series
8 R3 1 60 mΩ, 1/2W. 1%, 2010 surface mount Dale WSL Series
IRC LRC Series
Semiconductor
9 Q1 1 MOSFET, 3A, 50V, Dual N-Channel Motorola MMDF1N05E
National Semiconductor NDS 9955
10 Q2 1 MOSFET, 3A, 30V, Dual N-Channel Motorola MMDF3N03HD
National Semiconductor NDS 9936
11 U1 1 ML4863CS Micro Linear
Transformer
12 T1 1 Coupled Inductor Dale LPE-6562-A145
Coilcraft R4999-B
TABLE 2: VENDOR LIST
AVX (207) 282-5111Coilcraft (708) 639-6400Dale (Inductors) (605) 665-9301Dale (Resistors) (402) 563-6506IRC (512) 992-7900Motorola (408) 749-0510National Semiconductor (800) 272-9959Sprague (207) 324-4140
Application Note 49
8 REV. 1.0 10/25/2000
Figure 3: Typical Switching Waveforms — Full Load
Test Equipment: Tektronix TDS 540 Digitizing ScopeTest Conditions: VIN = 5V
IOUT 5 = 400 mAIOUT 3.3 = 200 mAIOUT 12 = 100 mA
CH1 - VQ1B-Drain: 10 V/DIVCH2 - VSENSE: 200 mV/DIVHoriz: 1 µs/DIV
Figure 2: Typical Switching Waveforms — Min Load
Test Equipment: Tektronix TDS 540 Digitizing ScopeTest Conditions: VIN = 5V
IOUT 5 = 4 mAIOUT 3.3 = 2 mAIOUT 12 = 1 mA
CH1 - VQ1B-Drain: 5 V/DIVCH2 - VSENSE: 100 mV/DIVHoriz: 20 µs/DIV
Table 4: Multiple Output Cross Regulation at 4V Input
I5V (mA) 5VOUT (V) I3.3V (mA) 3.3VOUT (V) I12V (mA) 12VOUT (V) Efficiency (%)
0 4.989 0 3.299 0 12.213 *
400 4.945 0 3.364 0 12.779 84
0 4.990 200 3.109 0 11.972 83
0 4.963 0 3.210 100 11.499 87
400 4.923 200 3.217 0 12.854 83
400 4.910 0 3.310 100 12.254 82
0 4.949 200 3.074 100 11.514 86
400 4.967 200 3.133 100 12.230 79
* No load input current = 140 µA
Application Note 49
REV. 1.0 10/25/2000 9
Table 5: Multiple Output Cross Regulation at 5V Input
I5V (mA) 5VOUT (V) I3.3V (mA) 3.3VOUT (V) I12V (mA) 12VOUT (V) Efficiency (%)
0 4.986 0 3.305 0 12.272 *
400 4.952 0 3.340 0 12.600 87
0 4.973 200 3.101 0 12.000 85
0 4.965 0 3.218 100 11.607 88
400 4.938 200 3.228 0 12.646 86
400 4.930 0 3.303 100 12.224 86
0 4.955 200 3.113 100 11.642 88
400 4.908 200 3.180 100 12.236 84
* No load input current = 110 µA
Table 6: Multiple Output Cross Regulation at 6V Input
I5V (mA) 5VOUT (V) I3.3V (mA) 3.3VOUT (V) I12V (mA) 12VOUT (V) Efficiency (%)
0 4.989 0 3.313 0 12.325 *
400 4.960 0 3.326 0 12.497 88
0 4.976 200 3.092 0 12.029 86
0 4.972 0 3.222 100 11.622 88
400 4.949 200 3.234 0 12.532 87
400 4.942 0 3.298 100 12.207 88
0 4.962 200 3.139 100 11.726 89
400 4.927 200 3.200 100 12.220 87
* No load input current = 90 µA
Application Note 49
10 REV. 1.0 10/25/2000
Top Silkscreen
Bottom Trace
Top Trace
Figure 4 — Sample Layout
Application Note 49
REV. 1.0 10/25/2000 11
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