A.   Pena   Perez,   E.   Bonizzoni,   F.   Maloberti:   "A   Low-­‐Power   Third-­‐Order   ΣΔ  Modulator  Using  a  Single  Operational  Amplifier";  IEEE  International  Symposium  on  Circuits,  ISCAS  2011,  Rio  de  Janeiro,  15-­‐18  May  2011,  pp.  1371-­‐1374.  

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A Low-Power Third-Order Σ∆ ModulatorUsing a Single Operational Amplifier

Aldo Pena Perez, Edoardo Bonizzoni, and Franco Maloberti

Department of Electronics, University of PaviaVia Ferrata, 1 - 27100 Pavia - ITALY

E-mail: [aldo.perez, edoardo.bonizzoni, franco.maloberti]@unipv.it

Abstract— An architecture for low-power Σ∆ modulators suit-able for high-resolution portable sensor systems is presented. Thecircuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boostingtechnique that increases by 5 the slew-rate. The circuit, simulatedat the transistor level using a conventional 0.18-µm CMOStechnology, obtains a peak SNDR of 88 dB over an input signalbandwidth of 100 kHz. The simulated power consumption is125 µW with a 1.5-V supply voltage. The achieved Figure ofMerit (FoM) is 31 fJ/conversion-level.

I. INTRODUCTION

An increasing number of portable sensors with readoutcircuits uses on-chip low power analog-to-digital converter(ADC). Applications like wireless sensor nodes and medi-cal diagnose always require at least 12-13-bit accuracy andextremely low power consumption (less than 200 µW) toimprove battery life. Furthermore, the ADCs must occupysmall silicon area.

Σ∆ modulators, typically used in telecommunication ap-plications such as audio-signal processing, exploit, as known,oversampling and noise shaping to achieve high resolution,[1]. This paper describes a third-order multi-bit Σ∆ modulatorthat obtains 14-bit accuracy with 100-kHz signal bandwidth.To meet low power requirements, this design optimizes theoutput swing of integrators and uses only one operationalamplifier (op-amp) working in time interleaved fashion. Thesingle op-amp is a conventional two-stage scheme and anauxiliary circuit boosts its slew-rate only when required.

The circuit, fully simulated at the transistor level with a0.18-µm CMOS technology, obtains 88-dB signal-to-noise anddistortion ratio (SNDR) and dynamic range of 93 dB. Thesimulated overall power consumption is 125 µW, thus resultingin a Figure of Merit (FoM) of 31 fJ/conversion-step.

This paper is organized as follows. In Section II, a noiseenhancement technique in a conventional second order Σ∆modulator is presented. Section III and Section IV describe thecircuital details of the modulator implementation and the useof resistive based digital-to-analog converters (DACs), respec-tively. Section V presents the simulation results at transistorlevel of the proposed modulator architecture. Finally, someconclusions are given in Section VI.

∑+_

1st Integrator

1/2 z-1

1-z-1∑+_

2nd Integrator

z-1

1-z-1

DAC1

DAC2

∑+

_H(z)

NoiseEnhancement

2

εq

+ VOUTVIN ADC

εq

Fig. 1. Enhancement of the NTF in a conventional second-order Σ∆modulator.

II. THIRD-ORDER Σ∆ ARCHITECTURE

The suitable injection of shaped quantization noise at thesecond integrator input of a Σ∆ scheme enhances the noiseshaping to third order, as shown in Fig. 1. The scheme uses asecond order modulator with two delayed integrators and thenoise enhancer block with transfer function H(z).

The noise shaping of a second and third-order Σ∆ modu-lators are, respectively

εq(1 − z−1)2 = εq(1 − 2z−1 + z−2) (1)

εq(1 − z−1)3 = εq(1 − 3z−1 + 3z−2 − z−3) (2)

where εq is the quantization error.The subtraction between (1) and (2) gives

εq(−z−1 + 2z−2 − z−3) = −z−1εq(1 − z−1)(1 − z−1) (3)

which rearranged yields

εq[2z−1(1 − z−1)︸ ︷︷ ︸

STF2

(−(1 − z−1)/2)︸ ︷︷ ︸H(z)

] (4)

that is the missing part needed to obtain third order noiseshaping. The transfer function from the second integrator inputis 2z−1(1−z−1). Therefore, the missing term is εq(1−z−1)/2,injected into the second integrator input. The operation doesnot require active blocks because the subtraction of analog andquantized signal is done with two separate paths, as shown inFig. 2. The analog injection uses passive switched capacitor(SC) structures that obtain the z−1 analog delay.

978-1-4244-9472-9/11/$26.00 ©2011 IEEE 1371

Third-Order Terms Injection

+_2∑

_

+

Analog Path

Digital Path

∑

2nd Integrator

z-1

1-z-1

1-z-1

1/2

DAC2

DAC1

+ VOUT

1/2

1-z-1

∑+_

1st Integrator

1/2 z-1

1-z-1VIN ADC

εq

Fig. 2. Proposed third-order Σ∆ architecture.

Another relevant feature of this design is the reduction ofthe operational amplifiers output voltage swing. It ensures areduction in the modulator power consumption, since the slew-rate requirements can be relaxed, and reduces the harmonicdistortion. The scheme of Fig. 3 uses an analog feedforwardpath to limit the output swing of the first integrator. The corre-lation between successive output samples enables a reductionof the second operational amplifier swing, [2], from V2(nT )to V2(nT ) − 1/2 · VDAC3(nT − T ). A lower V2 moderatesthe power of the op-amp and limits to 18 the number ofcomparators of the flash. The gain by two of the secondintegrator, transferred to the flash converter, compensates forthe 1/2 feedback factor of the analog path and reduces theswing of the op-amp at expenses of higher flash sensitivity.A 5-bit flash converter makes relatively low the quantizationerror and gives robustness to the loop. Suitable topologicalmodifications save the active sum at the input of the flashconverter, leading the final third-order Σ∆ architecture ofFig. 4.

III. SINGLE OP-AMP IMPLEMENTATION

A single operational amplifier working in time interleavedfashion, [3], realizes both integrators of Fig. 4. Fig. 5 showshalf schematic diagram of the Σ∆ modulator fully differentialsampled data implementation. The operational amplifier real-izes the first integrator during phase 1. The second integration,the injection of the (1 − z−1) term, the input feedforwardingand the conversion of DAC2 and DAC3 take place duringphase two. Fig. 5 also shows the phases scheme used to control

∑+_ +_∑

_

+

Digital Path

∑

2nd Integrator

z-1

1-z-1

1st Integrator

1/2 z-1

1-z-1

Analog Path

1-z-1

1/2

+ VOUTVIN 2+

+∑+_

DAC3

z-1

z-1

DAC1

DAC2

1-z-1

V2ADC

εq

1/2

Fig. 3. Σ∆ modulator with analog feedforward path and flash converterwith reduced input range.

VOUT2 +

z-1

+

_∑

+

Analog Path

∑

2nd Integrator

z-1

1-z-1

1-z-1

+ _+

1/2

z-1

DAC2

DAC1

DAC3

+

VOUT'

∑+_

1st Integrator

1/2 z-1

1-z-1VIN ADC

εq

Single Kelvin Divider

Fig. 4. Final architecture of the proposed third-order Σ∆ modulator.

switches.The first integrator uses 10CU for the input capacitor and

20CU for the feedback capacitor. For limiting the kT/C noise,the unity capacitance, CU , is 80 fF. The second integratoruses a unity capacitance for the 1/2 z−1 path that comes fromconversion of DAC2, and two unity capacitances for the otherbranches, namely feedforward and analog path respectively.The use of feedback capacitors with significant different valuesis not problematic because the operational amplifier can drivethe largest value.

The path feeding back the analog part of the quantization

+

_VOUTP

2Cu

2Cu

2Cu

2Cu

CuDAC2N

DAC3P

VINP

PHASES

Feedforward path

DAC1P

20Cu

2CuVOUTP

DAC1P

10CuVINP

OPAMPTWO-STAGE

+

_

1st. Integrator

2nd. Integrator

z-1

VOUTN

1

Φ2 Φ1

Φ1 Φ2

Φ1Φ2Φ1aΦ1b

Φ2aΦ2bΦ2c

Φ1

Φ2

Φ1 Φ2

Φ2 Φ1

Φ2 Φ2

Φ1 Φ1

Φ1 Φ2

Φ2 Φ1

Φ1a

Φ1aΦ1b

Φ1b

Φ1aΦ1b Φ1b

Φ1a

Φ2aΦ2bΦ2c

Φ2bΦ2cΦ2a

Φ2a

Φ2b Φ2a

Φ2b

Fig. 5. Half sampled data implementation of the modulator.

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VINN VINP

VB

MM1 MM2

VB2

IB

αIB αIB

MM9

VS1

VS3

MM5

1:1MM7 MM3 MM4

MM10

VS2

VS4

MM6

1:1MM8

VINN VINP

VB1

VBMB

M1 M2

M3 M4

M5

MH

VOUTN

VB VS3 VS4

M6

VOUTP

VB

MFVS1

M7 M8

MI

MDVS4

MG

ME VS3

CcRc

MA MC

VS1

VS2

VS2

Cc Rc

Fig. 6. Schematic diagram of the auxiliary circuit (top). Two-stage mainamplifier (bottom).

error needs two analog delays. They enables the time multi-plexing operation of the op-amp. The first uses two switched-capacitors structures, controlled by phases Φ1a and Φ1b thatoperate in a ping-pong fashion. The other needs three SCstructures that work under the control of phases Φ2a, Φ2b,and Φ2c. An extra SC structure enables the implementation ofthe required delay.

Fig. 6 shows the schematic diagram of the operationalamplifier suitable for this design. It ensures high slew-ratewithout requiring high power. Indeed, the multiplexed opera-tion performed by the op-amp and the foreseen clock speedrequire a slew rate much higher than the scheme obtains. Anauxiliary circuit (scheme at the top of Fig. 6) boosts the currentwhen required, [4].

The bias current, IB , of the differential pair MM1-MM2 islower than the one of the two active loads MM3-MM4. Innormal conditions, they are in the triode region and keep offthe diode connected elements MM5 and MM6.

During slewing, the differential pair MM1-MM2 completelyunbalances and the current IB(1 − α) flows through one ofthe diode connected devices. This current, suitably mirrored,boosts the currents in the main amplifier. The auxiliary circuithas four outputs for boosting the bias currents in both the mainamplifier first and second stage.

IV. USE OF RESISTIVE DACS

Conventional Σ∆ modulators use capacitive based DACswith, when necessary, dynamic elements matching (DEM),[5]. The matching accuracy increases with the area of thecomponents. However, to avoid DEM, it is often necessary toover design the unity capacitor well above the value requiredby the kT/C limit, thus increasing the power consumption.

It can be convenient using a resistive based DAC becauseenlarging the unity resistance does not affect the power con-sumption and does not limit the speed of operation. Large

DAC1

VOUT

z-1 VOUT'

DAC2

DAC3

Vref

Ru

Ru

Ru

-Vref

Kelvin Divider32-levels

Ru

Ru

Ru

Bus

with

Vol

tage

Ref

eren

ces

VOUT'DAC2N

DAC2P

DAC1N

DAC1P

DAC3N

DAC3P

Fig. 7. Single Kelvin divider for all DACs.

area in the resistors costs an error due to the gradient of theresistive properties of the divider. However, the use of thesame resistive string to generate differential voltages cancelsthe gradient error at the first order.

Supposing that the value of the generic k-th resistor is Rk =Ru + kδR, the differential voltage becomes

Vdiff = Vref(N − i)Ru + δR(N − i)(N − i+ 1) − iRu + δRi(i+ 1)

NRu + δRN(N + 1)(5)

that is independent on δR. Therefore, it is possible using alinear string of resistors with area that satisfies the matchingrequirements without caring about gradient limits. Unity resis-tors with area equal to 250 µm2 ensure a matching better than0.1% and leads to harmonic distortion of more than 86 dBwithout the need of calibration.

A single Kelvin divider realizes the three DACs of Fig. 4providing 32 voltage levels. Digital signals VOUT , z−1V

′

OUT ,

5

1.0

Out

put V

olta

ge [V

]

Time [μs]5.2 5.4 5.6 5.8 64.8

0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

Output with BoostingSR=15.5 V/μs

Output without BoostingSR=3 V/μs

Fig. 8. Simulated slew rate response.

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TABLE ISIMULATED OP-AMP PERFORMANCE

Supply Voltage = 1.5 V, IB = 10 µA

Parameter Symbol [Unit] Value

DC Gain Av [dB] 65

Slew-Rate (with Booster) SR [V/µs] 3 (15.5)

Unit Frequency GBW [MHz] 25

Phase Margin Φ [Degree] 67

Power Consumption PW [µW] 60

and V′

OUT control the three selection networks to obtain theDACs differential outputs, as shown in Fig. 7.

V. SIMULATION RESULTS

The single op-amp third-order Σ∆ modulator has beensimulated at the transistor level by using a 0.18-µm CMOStechnology. The nominal supply voltage and sampling fre-quency, FS , are 1.5 V and 3.2 MHz, respectively.

The bias current of the differential pair in both circuits ofFig. 6 is IB =10 µA. The top current generators of the auxiliarycircuit is 7 µA. When the inputs are unbalanced, the slewingcondition directs 3 µA toward one of the diode connectedtransistors. The amplified mirroring of this current augmentsthe slew rate goes from 3 to 15.5 V/µs, as shown in Fig. 8.Table I summarizes the performance of the op-amp.

Fig. 9 shows the simulated output spectrum of the Σ∆modulator. The input signal is at -4 dBFS and its frequency is98.56 kHz. With an oversampling ratio of 16, the modulatorachieves a signal to noise and distortion ratio (SNDR) of 88 dBover a signal bandwidth of 100 kHz.

Fig. 10 depicts the simulated SNDR versus the input am-plitude. The achieved dynamic range is 93 dB. The estimatedoverall power consumption is 125 µW, which would lead to aFoM equal to 31 fJ/conversion-level. Table II summarizes thesimulated results.

−140

−120

−100

−80

−60

−40

−20

0

Frequency [Hz]

PSD

[dB

]

100 k 1 M10 k

FFT points = 2046OSR = 16 @ Fs = 3.2 MHz

-4 dBFS

Fig. 9. Simulated power spectral density.

−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0−20

0

20

40

60

80

100

SND

R [d

B]

Input Amplitude [dB]

Peak SNDR = 88 dB @ -4 dBFS

DR = 93 dB

Fig. 10. Simulated SNDR vs input amplitude.

TABLE IISIMULATED MODULATOR PERFORMANCE

0.18-µm CMOS technology, Supply Voltage = 1.5 V

Parameter Symbol [Unit] Value

Signal Bandwidth BW [kHz] 100

Clock Frequency FS [MHz] 3.2

Oversampling Ratio OSR [–] 16

Peak SNDR SNDR [dB] 88

Dynamic Range DR [dB] 93

Power Consumption PW [µW] 125

Figure of Merit FoM [fJ/Conversion-Level] 31

VI. CONCLUSIONS

A single op-amp low-power third-order Σ∆ modulator hasbeen presented. The modulator achieves 88 dB SNDR and93 dB dynamic range. The 125 µW power consumption yieldsa FoM of 31 fJ/conversion-level. Sampled at 3.2 MHz over a100 kHz signal bandwidth, the modulator is suitable for high-resolution portable sensor systems.

ACKNOWLEDGMENT

This work is partially economically supported by FIRB,Italian National Program #RBAP06L4S5.

REFERENCES

[1] S.R. Norsworthy, R. Schreier, and G.C. Temes “Delta-Sigma DataConverters”, IEEE, Inc. New York, 1997.

[2] E. Bonizzoni, A. Pena-Perez, F. Maloberti, and M. Garcia-Andrade,“Third-Order Σ∆ Modulator with 61-dB SNR and 6-MHz BandwithConsuming 6 mW”, Proc. of the IEEE European Solid-State CircuitsConference (ESSCIRC), pp. 218-221, Sept. 2008.

[3] J. Koh, Y. Choi, and G. Gomez, “A 66dB DR 1.2V 1.2mW Single-Amplifier Double-Sampling 2nd-order Σ∆ ADC for WCDMA in90nm CMOS”, IEEE International Solid-State Circuits Conference(ISSCC) Dig. Tech. Papers, 170-591, Feb. 2005.

[4] A. Pena-Perez, Y.B.N. Kumar, E. Bonizzoni, and F. Maloberti, “Slew-Rate and Gain Enhancement in Two-Stage Operational Amplifiers”,Proc. of the IEEE International Symposium on Circuit and Systems(ISCAS), pp. 2485-2488, May 2009.

[5] R. Schreier and B. Zhang, “Noise-shaped multibit D/A converteremploying unit elements”, Electronics Letters, vol. 31, no. 20, pp.1712-1713, Sept. 1995.

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