I.  Galdi,  E.  Bonizzoni,  F.  Maloberti,  G.  Manganaro,  P.  Malcovati:  "Two-­Path  Band-­Pass   Σ-­Δ   Modulator   with   40-­MHz   IF   72-­dB   DR   at   1-­MHz   Bandwidth  Consuming  16  mW";   33rd  European   Solid   State  Circuits   Conf.,   ESSCIRC  2007,  Munich,  11-­‐13  September  2007,  pp.  248-­‐251.  

 

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Two-Path Band-Pass !" Modulator with 40-MHz IF

72-dB DR at 1-MHz Bandwidth Consuming 16 mW

I. Galdi, E. Bonizzoni, F. Maloberti

University of Pavia

Department of Electronics

Via Ferrata, 1 – 27100 Pavia – ITALY

ivano.galdi@unipv.it

G. Manganaro

National Semiconductor Corporation

1 Stiles Road

Salem, NH 03079 – USA

gabriele.manganaro@nsc.com

P. Malcovati

University of Pavia

Department of Electrical Engineering

Via Ferrata, 1 – 27100 Pavia – ITALY

piero.malcovati@unipv.it

Abstract— A band-pass !" modulator that uses two time

interleaved second-order modulators and cross-coupled paths is

described. Split zeros around the 40-MHz IF provide a signal

band of 1 MHz with 72-dB DR and 65.1-dB peak SNR. The

circuit, integrated in a 0.18-!m CMOS technology, uses a

60-MHz clock per channel. Experimental results show that the

in-band region is not affected by tones caused by mismatches

and that a two-tones input causes an IMD signal of 68 dBc. The

power consumption is 16 mW with 1.8-V supply.

I. INTRODUCTION

The designer of portable communication systems often

examines solutions with !" band-pass converters [1] because

of their low power benefit. However, since the multiple zeros

of the noise transfer function are at the IF, the noise shaping

advantage vanishes when increasing the signal band.

Moreover, the position of the IF frequency is almost locked.

Instead, a Nyquist-rate converter enables any signal bandwidth

and allow positioning the IF anywhere in the Nyquist interval.

Nevertheless, the power consumption is not affordable for

portable applications as, for instance, for sampling frequencies

in the 40 - 80 MHz range, the power of a 12-bit converter is

several tens of mW [2].

This design offers a viable solution to the problem as it

obtains low power while enabling a relatively large bandwidth

(2 MHz) so that the IF can be possibly moved within a

reasonable range, or the granted frequency band can be fully

used for the signal. The used circuit is a 2-path band-pass

architecture with 4-bit quantizers. The used scheme avoids the

well known limits caused by channel mismatches, that,

typically, cause in-band tones. Indeed, the experimental results

show a tone free spectrum with a low noise flat region of

±1 MHz around 40 MHz (less than 125 nV/

!

Hz with a ±1 V

differential reference). Therefore, using a 1-MHz signal band,

the dynamic range is 72 dBFS while the peak SNR is 65.1 dB.

Each path runs at 60 MHz, leading to a 120-MHz sampling

frequency. The power consumption is 16 mW with a 1.8-V

supply.

II. NTF SYNTHESIS

This circuit obtains a band-pass sigma-delta response by

synthesizing the noise transfer function (1+#z-1

+z-2

)2. The

NTF for # =1 gives rise to a pair of zeros on the unity circle

around 1/3fs and 2/3fs and no spur zeros elsewhere. With # !1

but close to the unity value, the pair of zeros moves slightly

apart increasing the region of band-pass noise shaping. This

method is used in this design for trading the noise attenuation

at the IF with an increased signal band. Actually, the zero shift

does not affect the performance until the shaped quantization

noise remains below the floor established by the thermal noise

and the finite performance of the op-amps.

The architecture synthesizes the expected transfer function

starting from a two-path structure. The method is based on the

rewriting of the NTF as follows

!

NTF = (1+ z"2)2 +# 2z"2[ ] + z"1 2#(1+ z"2)[ ] (1)

that outlines two main terms, enclosed in squared brackets,

both function of z2. Therefore, the implementation of those

terms would require a circuit able to achieve a z $ z2

transformation. Moreover, observe that the second term

requires a delay by one clock period. As done in [3], the

transformation z $ z2 is granted by a two-path time-

interleaved scheme with each path running at half of the clock

frequency. In our case each path should generate an NTF

equal to (1 + z-1

)2 + #

2z

-1. The result is obtained by the scheme

shown in Fig. 1 (with the auxiliary inputs set to zero). Notice

that the architecture of Fig. 1 is a second order modulator

employing blocks with 1/(1 + z-1

) transfer functions instead of

the one of a conventional integrator. Moreover, there is an

extra feedback toward the input made by two terms: one is the

analog output and the other is combined with the normal

1-4244-1125-4/07/$25.00 ©2007 IEEE. 248

feedback term that is therefore multiplied by 2 before

exercising the main DAC. The result is that the combination

of the feedbacks yields the quantization error at the input of

the block after a delay by z-1

. This is what required to

implement the last term #2z

-1 of the path’s NTF.

Fig. 1 – Block diagram of the single path.

Fig. 2 – Block diagram of the modulator.

Actually, the block diagram of Fig. 1 obtains # =1. For having

a different value, it is enough to change the capacitance used

in the analog feedback and to adjust the reference voltage of

the main DAC. A possible mismatch between the two

corrective actions is not problematic because, possibly, it

gives rise to a gain error of the entire modulator.

A two-path time-interleaved architecture uses the even

input samples in one path and the odd ones on the other path.

Therefore, there is one clock period delay between the signals

that are processed by the two paths. This delay corresponds to

what required by the z-1

term that multiplies the second term

enclosed in square brackets in (1). Therefore, a cross-coupled

injection of the quantization noises into the auxiliary input

realizes the second brackets because the path transfer function

is 2#(1 + z-1

). By inspection, it is easy to verify that the

transfer function from the auxiliary input to the output is,

actually, (1 + z-1

). Thus, the cross injection of the quantization

noise multiplied by 2 provides the result. The complete block

diagram of the modulator is shown in Fig. 2, where the cross-

coupled quantization errors are distinguished into the analog

and digital components. The output is interpolated at the

output to provide the output bit stream at the foreseen clock

frequency. A possible offset mismatch of the op-amps used in

the first integrators causes a tone at fs/2 while a gain mismatch

is equivalent to an attenuation and a modulation of the input

signal by fs/2. Therefore, the caused tones are far away from

the signal band. Observe that the cross-coupled connections

required for injecting the second term of the NTF create a loop

of two blocks with transfer function z-1

/(1 + z-1

). The effect of

the loop can be easily studied in the time domain and the

result is that a possible DC signal (like the offset mismatch of

the second op-amp) into that loop is transformed into a tone at

fs/4.

Fig. 3 – Implementation of z

-1/(1 + z

-1).

III. CIRCUIT SCHEMATIC

The circuit implementation of the transfer function

1/(1 + z-1

) or z-1

/(1 + z-1

) requires an inversion of the previous

output every clock period. We obtain the same result by

modulating by ±1 at fs/2 both input and output of a

conventional integrator [3]. The circuit that realizes the ±1

modulation at half of the clock frequency at input and output

of an inverting or non inverting integrator is the scheme of

Fig. 3. Actually, the square wave modulation at the output of

the first integrator and the one at the input of the next one

cancels one another just requiring the ±1 switches only at

input and output of the entire scheme and in the cross-coupled

paths. Moreover, for saving power, the first and the second

integrators of the paths share the op-amp [4]. The use of the

same of-amp in the first and in the second path is made

possible by the z-1

delay between the two decimation by two

operations at the input. The integrating capacitors are

disconnected from the op-amp output side with a switch

during the inactive period. The use of the op-amp in both

phases demands for higher bandwidth and slewing, but the

overall power consumption diminishes by about 35% than in

the case with separate op-amps. As a side benefit of the op-

amp sharing, there is no offset mismatch in the cross-coupled

loop and the tone at fs/4 is caused only by the clock

feedthrough associated to the switches connected to the virtual

ground.

The two op-amps have the same scheme but use different

bias currents as requested by the slew-rate and the feedback

factors: they are fully-differential mirrored cascode amplifiers

with switched capacitor common-mode feedback. The key

features are given in Table 1. Observe that the DC gain is

pretty low; this feature is made possible by the moderate

sensitivity on the gain at the expected overall resolution. The

simulation results made at the behavioural level, but

including finite gain, bandwidth and slew-rate of the op-amps

show that a DC gain as low as 40 dB does not degrade the

performance that are, instead, determined by the kT/C limit.

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On the contrary, the bandwidth and the slew-rate must be

relatively high but the request is met by the used scheme at a

reasonable power consumption. The high bandwidth and

slew-rate of the second op-amp depend on the feedback factor

established by the cross-coupled input with gain 2.

TABLE I OP-AMPS PERFORMANCE

Feature First op-amp Second op-amp

DC gain 46 dB 42 dB

Unity gain frequency 200 MHz 250 MHz

Slew-rate 200 V/µs 260 V/µs

Supply voltage 1.8 V 1.8 V

Power consumption 1.2 mW 2.3 mW

The voltage comparators of the two 4-bit flash ADCs are

made by a preamplifier with gain 4 followed by a latch. The

bias current of each preamplifier is 20 µA. A single resistive

divider made by 16 equal 500-% resistors provides the

reference voltages of both flash ADCs. The DACs are

embedded in the input switched capacitor structure made by

16 unity elements equal to 25 fF. The combinatory digital

logics perform the required operations within the clock

period, 16.5 ns. The integration capacitances are slightly

changed (# = 1.003) to ensure a proper NTF zeros separation.

Fig. 4 – Chip microphotograph.

IV. EXPERIMENTAL RESULTS

The modulator was integrated using a 0.18-"m single-poly

5-metal CMOS technology. The die, whose microphotograph

is shown in Fig. 4, has an active area equal to 0.44 mm2. The

reference voltages are external to the circuit and no internal

buffer is used for enforcing the strength of the references. This

is beneficial for limiting the power consumption, but is

problematic for the ringing caused after every switching

because of the bonding inductance of the connection from pin

to pad. The duration of the ringing limits the usable clock

frequency that, for a TQFP package, is about 16 MHz per path

equivalent to an IF of 10.7 MHz. The use of a LLP package,

whose bonding inductance is much lower than the TQFP,

allows a 60 MHz clock per path that increases the IF to 40

MHz. The operation with 16-MHz clock requires an overall

power consumption of 10.5 mW while, with an higher clock

(60 MHz), the required power, accounting for the increased

one consumed in the op-amps for more demanding slew-rate

and bandwidth, is 16 mW.

Fig. 5 – Measured modulator output spectrum.

The measured output spectrum is shown in Fig. 5. The in-

band noise is almost flat over the used range with a floor

equal to 125 nVFS/

!

Hz , that is slightly more than the expected

kT/C contribution (102 nVFS/

!

Hz ), likely because of the

op-amp limits. The spectrum also shows the tone at fN/2 that

is -34 dBFS that, as described before, is due to the clock

feedthrough at the input of the second stages. The associated

amplitude (20 mV) slightly diminishes the full scale of the

modulator, that, indeed, is much more limited by the

quantization noises.

Fig. 6 – SNR versus input signal amplitude.

250

The SNRs as a function of the input amplitude for three

different bandwidths 1 MHz (40 ± 0.5 MHz), 2 MHz

(40 ± 1 MHz) and 4 MHz (40 ± 2 MHz) are shown in Fig. 6.

Since there are no tones, the SNDR equals the SNR. It can be

noted that an increase (as well as a reduction) of the signal

band diminishes the SNR as the square of the increase factor

(i.e., plain oversampling) until remaining within the flat

region, but drops significantly when the signal band reaches

the frequency region where the noise ramps up. The peak of

the SNR occurs around -6 dBFS even if the circuit uses a 4-bit

quantization. The result, predicted by simulations at the

behavioural level, is due to the relatively large amplification

of both quantization errors that show up at the two inputs.

Fig. 7 – IMD test result.

The linearity of the modulator has been evaluated with a

two-tone intermodulation (IMD) test (f1 = 39.474 MHz,

f2 = 39.874 MHz). For two tones at -14 dBFS (as shown in

Fig. 7), the intermodulation tone falling at 2f2 - f1 is visible

above the noise floor and gives an IMD of about 68 dBc. The

result is 3 dB better than the remarkable figure obtained in [5]

that uses a more complex solution and requires four-five

times more of power.

The performance of the modulator are summarized in

Table 2. Obviously, since the IF frequency is a fixed ratio of

the path clock (2/3), scaling down the clock frequency also

scales the IF. Thus, for example, the circuit can meet the

specification for digitizing the AM/FM radio broadcasting

signal, by obtaining 67-dB peak SNR and 72-dB DR, with a

reduced power equal to 10.5 mW, made possible by the

diminished speed request to the op-amps.

V. CONCLUSIONS

In this paper a band-pass !" modulator that uses two time-

interleaved second-order modulators and cross coupled paths

is described. Split zeros around the 40 MHz IF provide a

dynamic range of 72 dB, 69 dB and 50 dB SNR for signal

bands of 1 MHz, 2 MHz, and 4 MHz respectively (full scale

signal ±1 VPP differential). The in-band noise floor is about

125 nV/

!

Hz . The circuit, integrated in a 0.18-"m CMOS

technology, uses a 60-MHz clock per channel. For two tones

at -14 dBFS, the intermodulation is about 68 dBc. The power

consumption is 16 mW with 1.8-V supply and can be

decreased to 10.5 mW with 16-MHz clock per channel.

TABLE II

PERFORMANCE SUMMARY

fs 60 MHz (x 2)

IF 40 MHz

Voltage References ±0.5 V

Signal Bandwidth up to 4 MHz

Peak SNR 65.1 dB @ 1 MHz Band

Active Area 0.44 mm2

Supply Voltage 1.8 V

Power Consumption 16 mW

IMD 68 dBc

DR 72 dB @ 1 MHz Band

ACKNOWLEDGMENT

The authors would like to thank Carlos Hinojosa and

Jacque Margolycz of National Semiconductor Corporation for

their valuable support to this work.

REFERENCES

[1] T. Salo, T. Hollman, S. Lindfors, and K. Halonen, “A dual-mode

80MHz bandpass !" modulator for a GSM WCDMA IF-

receiver”, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap.,

pp. 218-219, 461, Feb. 2002.

[2] T.N. Andersen, B. Hernes, A. Briskemyr, F. Telsto, J. Bjornsen,

T.E. Bonnerud, and O. Moldsvor, “A cost-efficient high-speed

12-bit pipeline ADC in 0.18-"m digital CMOS”, IEEE J. Solid-

State Circuits, vol. 40, no. 7, pp. 1506-1513, July 2005.

[3] F. Ying and F. Maloberti, “A mirror image free two-path

bandpass !" modulator with 72 dB SNR and 86 dB SFDR”,

IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., vol. 1,

pp. 84-85, Feb. 2004.

[4] K. Nagaraj, F.S. Fetterman, J. Anidjar, S.H. Lewis, and

R.G. Renninger, “A 250-mW, 8-b, 52-Msamples/s parallel-

pipelined A/D converter with reduced number of amplifier”,

IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 312-320, March

1997.

[5] V. Colonna, G. Gandolfi, F. Stefani, and A. Baschirotto, “A

10.7-MHz self-calibrated switched-capacitor-based multibit

second-order bandpass !" modulator with on-chip switched

buffer”, IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1341-

1346, August 2004.

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