IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. I, NO. 1, FEBRUARY 1994 53

A Manufacturing Sensitivity Analysis of 0.35 pm LDD MOSFET’s

Khaled Hasnat, Suhail Murtaza, and A1 F. Tasch, Jr., Fellow, IEEE

Abstract- Fundamental to successful manufacturing of integrated circuits is the achievement of sufficient control in all process steps to realize, with very high yield, fully functional circuits whose performance and reliability conform to pre-determined standards. Towards this end, it is increasingly necessary to relate in a quantitative manner the sensitivity of the electrical performance of the final devices and circuits to variations in structural parameters and doping profiles, which in turn can be related to process and tool performance variations. In this paper, we describe the results of an analysis performed to quantify the sensitivity of the electrical parameters of a 0.35pm LDD MOSFET to variations in the doping and structural parameters of the device that are anticipated in manufacturing. A central-composite design was used to develop second-order models for six key device electrical parameters. The resulting models are manifested as second-order equations relating the device electrical parameter variations to random variations in seven key device structure and doping parameters. This set of equations thus allows one to understand quantitatively the source and nature of the device electrical parameter variations. A simple Monte Carlo approach is applied to predict the statistical distributions of the key device electrical parameters which result from the random manufacturing variations in the structure and doping parameters by using the quantitative relationships developed in this paper.

I. INTRODUCTION

UCCESS of an integrated circuit manufacturing process S and its economic viability depends on its ability to produce fully functional circuits whose performance and reliability lie within a specified range while maintaining high yield. Despite continuing improvements in manufacturing tools and in processes, there still exist random variations in each step of integrated circuit manufacturing. Moreover, as technology continues to advance towards smaller device geometries, it is increasingly difficult to scale the manufacturing variations in direct proportion to the device dimensions. As a result, the manufacturing of integrated circuits, particularly in the deep submicron regime, is becoming more and more challenging not only due to the increased complexity of the process, but also due to the tool capability and control requirements which are becoming increasingly difficult to satisfy. Tremendous effort has been devoted over the past two decades to the development of improved process tools and processes, more robust transistor structures, more forgiving circuit designs, and improved methodologies for process optimization and

Manuscript received May 26, 1993; revised September 16, 1993. The authors are with the Microelectronics Research Center, Department

of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712.

IEEE Log Number 9214299.

control. However, in order to make wise choices in the prioritization of these efforts as well as the strategies in these efforts, it is increasingly necessary to relate in a quantitative manner the sensitivity of the electrical performance of the final devices and circuits to variations in structural parameters and doping profiles, which in turn can be related to process and tool performance variations. With such a relationship it is possible to determine quantitatively the process and tool control requirements in order to meet specific structure and doping control requirements that are driven by specific device and circuit electrical parameter control requirements.

The results presented in this paper are aimed at relating quantitatively the sensitivity of the key electrical characteris- tics of 0.35 pm N-channel LDD MOSFETs, representative of 0.35 pm MOS technology, to variations in device structural parameters (i.e. gate length, gate dielectric thickness, junction depth, etc.) and doping profiles. Due to the high cost and long fabrication cycle time associated with the increasingly complex process flow necessary for fabrication of submicron devices, it is highly attractive, if not mandatory, to employ modeling and simulation tools in performing a sensitivity analysis. Moreover, in order to obtain the maximum amount of information with a minimum number of simulations, ex- perimental design techniques have been used to guide the simulations at statistically strategic points. Use of experimental design methodologies along with process/device simulation tools for device design and optimization has been discussed by a number of authors [1]-[7]. The basic approach described by these authors consists of two steps: (a) design of experiments, followed by (b) regression analysis in order obtain the various electrical parameters expressed as analytical functions of the structural and doping parameters. These analytical expressions are then used for device/process analysis and/or optimization.

Aoki et al. [ l ] used a central composite design to relate the electrical characteristics of a 0.5 pm NMOSFET to five device structural parameters and doping profiles. They used the method of least squares to determine the coefficients of polynomial equations relating the responses (device electrical parameters) to input factors (device doping and structural parameters). However, the issue of significance of various terms in the equations is not addressed in their analysis, and the analysis for optimization of the device is performed by using the complete equations rather than using simplified equations containing only the significant terms.

Alvarez et al. [2] used a Box-Behnken experimental design to optimize a BICMOS process. After obtaining a set of second-order equations relating the various process steps and

08946507/94$04.00 0 1994 IEEE

54 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 7, NO. 1, FEBRUARY 1994

the device electrical characteristics, they optimized the process by determining the range of process parameters over which all of the responses meet their specifications. However, they used 1-D device simulator for their analysis, which is not appropriate for our analysis as the inclusion of 2-D effects is mandatory for determining device characteristics of submicron devices. Low et al. [3] used experimental design to build a macromodel to analyze a 3pm CMOS process.

In their paper, the authors have used a reduced number of experiments in order to screen the significant input factors before performing the simulations for the full experimental design. Then simulations were performed considering only the significant input factors. The approach described by the authors is extremely useful for problems with a large number of input factors (> 10). However, the simulator used in their analysis is based on simplified analytical equations for 3 pm devices, which have limitations in physical accuracy for deep submicron devices.

Sharfizadeh er al. [4] used a modified central-composite experimental design for direct estimation of the gradient of a response surface for sensitivity analysis and device optimization. For each point of a central composite design, an additional simulation is conducted at a distance (T away from the design point (where (T is the vector of the standard devi- ation). This direct estimation of the gradient of the response surface is claimed to be better than measuring the sensitivity by taking the derivative of the fitted response. However, the higher accuracy is obtained at the expense of an increased number of simulations.

In [5] Masuda et al. used a central-composite design to relate the threshold voltage and saturation current of a submicron MOSFET to four device structural and doping parameters. They proposed a technique for variable transformation in order to obtain better agreement between the device characteristics predicted by the derived analytical expressions and that mea- sured experimentally. However, exprimental data required by this approach may not always be available, particularly, in the initial stage of the development of a new process.

Cecchetti er al. [7] used experimental design methodologies along with a one-dimensional device simulator in order to determine the effect of the variations in different process steps on the threshold voltage and saturation current of long-channel MOSFET’s. Linear models were applied to fit the responses. Then, using the Monte Carlo method, they predicted the distribution of the two electrical parameters due to variations in the process steps. However, use of a 1-D device simulator limits their analysis to long-channel devices. Also, this analysis is restricted in that it examines the effect of process variations on the threshold voltage and saturation current only. It does not consider the other key device electrical parameters.

Sanders et al. [6] used a factorial design which focused on relating only the base junction depth and sheet resistivity of an NPN transistor to the process steps. They obtained a reduced set of first-order linear equations relating the base junction depth and sheet resistivity to six process parameters. However, linear equations are used by the authors in [6] as well as in [7], and these are more limited than higher order equations in providing an accurate fit for responses.

Applications of experimental design techniques to device analysis and optimization have mostly been limited to con- ventional MOSFETs with a single sourceldrain structure. How- ever, MOSFETs with a lightly doped source/drain (LDD) are predominantly used in manufacturing today in order to ensure reliable device operation in submicron technology. In this paper, we present a detailed manufacturing sensitivity study of submicron LDD MOSFET’s representative of 0.35 pm MOS technology. The representative device has nominal structure and doping parameters based on a detailed simulation analysis in which the goal was to simultaneously satisfy the combined key performance and reliability requirements for 0.35 pm MOS technology.

One approach for analyzing the manufacturing sensitivity of a device is to evaluate the effect of variations in each process step on device electrical parameters. However, findings of such an analysis are really only valid for the particular process flow under study, as the effects of one process step on the electrical parameters depend on the subsequent process steps. In this study, by relating the variations in the electrical parameters of the device to the corresponding variations in the doping profiles and structural parameters, the analysis is independent of the particular process flow. Then the relationships obtained in this analysis can be more widely utilized in a straight- forward way by relating the variations in the device profiles and structural parameters to the process and tool performance variations associated with a particular process. A simple example involving the MOSFET gate length helps to illustrate the point.

The analysis approach in this paper determines the sen- sitivity of various key electrical device parameters to the device gate length variations. Gate length variations can be caused by any combination of random variations in the mask dimensions, the photoresist patterning, the etching step, and perhaps other steps such as poly oxidation after patteming. The relative contributions of these different steps depend, of course, on the particular process. If the analysis in this paper considered a specific set of process steps and tools, its validity would be unnecessarily restricted. However, by relating the electrical parameter variations to the structure and doping variations, the results can be more widely applied to different processes. These results will quantify the sensitivity to structure and doping variations, and they will provide information on not only the major contributors to the device electrical parameter variations, but the required structures and doping control for achieving desired electrical performance windows. Then for a specific process the contributions of the different structure/doping parameter variations can be evaluated, and process/tool control strategies and tradeoffs can be developed which best satisfy the desired structure/doping control as determined by the analysis in this paper.

We have used a central-composite design approach to de- velop a set of second-order equations relating the device electrical characteristics to the doping and structural param- eters. Statistical methods have been applied to determine the accuracy of the quantitative relationships in describing the simulated data. Finally, by using the quantitative relationships derived in this analysis, variations in the electrical character-

HASNAT et al.: A MANUFACTURING SENSITIVITY ANALYSIS OF 0.35pm LDD 55

TABLE I 0.35 p m LDD M o s m STRUCTURAL AND DOPING PARAMETERS AND THEIR ANTICIPATED MANUFACTURING VARIATIONS.

Parameters Nominal Value Standard Deviation (a) 3a Low level (-1) High level (+1) LG (m) 350 20 60 290 410 to, (nm) 9.0 0.25 0.75 8.25 9.75

t s , (m) 160 6.7 20 140 180

N-dose (cmP2) 1 .41~1013 4 . 7 ~ 1011 1.41 x 10” 1 . 2 7 ~ 1 0 ’ ~ 1 . 5 5 ~ 1 0 ~ ~

N,hdose (cm-2) 9 . 3 ~ 1 0 ’ ~ 3 . 1 ~ 1 0 ’ ~ 9.3 X l O l l 8 . 3 7 ~ 1 0 ’ ~ 1 . 0 2 ~ 1 0 ~ ~

;U, (N-) (MI) 100 3.3 10 90 110

x, ( N + ) (m) 200 6.7 20 180 220

istics due to random contributions of variations in the doping and structural parameters can be simulated using Monte Carlo techniques. This allows one to realistically predict the expected distribution of the electrical parameters resulting from the random variations in the structure and doping parameters that are anticipated in the manufacturing process. Examples of this exercise are discussed.

11. SIMULATION STRATEGY

A 0.35pm LDD MOSFET whose doping and structural parameters have been optimized in terms of performance and reliability is used as the representative structure for the manufacturing sensitivity analysis. The doping and structural parameters of this device are illustrated and defined in Fig. 1. The analysis described and performed in this paper deter- mines the sensitivity of the device electrical characteristics to variations of the seven key doping and structural parameters of the device. The nominal values of the seven key doping and structural parameters (input factors) as defined in Fig. 1 and their anticipated manufacturing variations are given in Table I. The choice of these doping and structural parameters is based on an analysis of the device. Reasonable values for the standard deviations of the variations in the input parameters were estimated based on the knowledge of existing process and tool control capabilities. The following six device electrical parameters were monitored for their dependence on the variations of the dopinglstructure parameters:

Threshold Voltage, VT(VD = 50 mV and ID =

Source-drain leakage current, Ileak(VD = 4 V, VG = 0

Saturation current, I,,,(VD = VG = 4V) Drain-induced barrier lowering (DIBL), AV, Subthreshold slope, S Peak substrate current, IBub

Npm)

V, T = 100°C)

These electrical parameters best describe the performance and reliability of the MOSFET. Threshold voltage, source-drain leakage current, and subthreshold slope determine the tum-off characteristics of the MOSFET. Drain-included barrier lower- ing is a measure of the short-channel effects, and saturation current provides a measure of the current drive capability of the MOSFET. The peak substrate current is widely used as a measure of the carrier heating within the device, and is used as a monitor for predicting device lifetime (i.e. reliability).

Experimental design methodologies were employed to ob- tain empirical relationships of the form given in Equation (1)

4; I Gate length to.= Oxide thickness tlP I Sidewall oxide thickness X j (N+) E Source-drain junction depth X j (N-) I LDD junction depth Ghdose I Implant dose for channel region N- dose E Implant dose for LDD region

Fig. 1. Cross section illustrating the 0.35 pm LDD MOSFET structure used in the analysis and the definition of the parameters characterizing the structure.

between each device electrical parameter Y k and the doping and structural parameters Xi

n n n n

F k = b O k + ~ b i k x i + x b i i k x f + x bijkxixj (1) i=l i=l i= l j # im

where the b’s are the estimated coefficients of the approxi- mated equations. The input parameters (doping and structural parameters) Xi’s in the above equation are normalized ac- cording to the following equation

where, is the actual mean value of the ith input parameter, & is the actual value of the ith input parameter, and di is the magnitude of the difference between the two values that ith input parameter can assume in a two-level factorial design. We have used a central composite experimental design [8] in order to determine all of the coefficients in the equations of the form given in (1). This central composite design requires simulations of 79 device structures. The first 64 simulation runs of this central composite design represent a 277-1 fractional factorial design, which was selected in order to reduce the total number of simulations. This fractional- factorial design was developed by first constructing a 26 full-factorial design in LG, to,, Nchdose, t sp , X j ( N - ) , and N-dose. Then the input levels for X j ( N + ) were obtained by using the following confounding equation,

X j ( N + ) = LG x to, x Nchdose x t,, x X j ( N - ) x N- dose (3)

56 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. I, NO. 1, FEBRUARY 1994

The low (-1) and high (+1) levels of each input factor used in this fractional factorial design were obtained by varying the input factor from its nominal value by an amount which corresponds to its 3a value, where a is the sttandard deviation of the anticipated manufacturing variation. The actual values of the parameters corresponding to their normalized +1 or -1 levels are given in Table I.

The next fourteen simulations (65 through 78) where per- formed by setting the level of each of the input parameters at +a and -a, while keeping the rest of the input factors at the zero (nominal) level. The value of a was chosen to be 1.88 in order to maintain rotatability of the experimental design [SI. The last simulation run was performed with all of the input factors at their nominal value. In order to obtain realistic doping profiles, the SUPREM 3 process simulator [9] has been used to obtain the doping profiles of these 79 device structures. The one-dimensional doping profiles obtain from SUPREM 3 were then used in PISCES IIB [lo], a two- dimensional device simulator, to generate I-V characteristics of the devices. Since PISCES IIB is two-dimensional device simulator, the 1-D profiles obtained from SUPREM 3 must be extended in the second dimension in order to account for the lateral extension of the doping profile beneath the edge of the gate. This is accomplished by specifying a lateral diffusion of 52% of the vertical profile obtained from SUPREM 3. This choice of the amount of lateral diffusion is based on SUPREM 4 2-D process simulations [ 111. However, it should be pointed out that there is some uncertainty in the choice of the exact amount of lateral diffusion, especially with low thermal budget processing in which implant-induced damage may result in a different lateral profile. This is an area iq which improved 2-D diffusion models are needed for low thehnal budget processes such as rapid thermal annealing. The electrical parameters of the devices were then extracted from the I-V characteristics calculated by the 2-D device simulator.

111. RESULTS AND DISCUSSION Once the electrical parameters of all of the 79 structures

are extracted, the next step in the analysis is to calculate the coeffcients of the empirical equations for the six electrical parameters. This is accomplished by using the method of least squares [12]. Statistical methods can then be applied to determine the significance of each of the coefficients in the empirical +equations. One of the methods of determining the significant terms in the empirical equations is to plot the coefficients on a normal probability plot [13]. Based on the assumption that the coeffricients that are not significant represent a random sample from a normal noise distribution, the points that correspond to the insignificant coefficients will fall on a straight line. However, coefficients that are signif- icant, represent contaminations in a normal distribution, and points on the normal plot corresponding to these significant coefficients will deviate from the straight line. Fig. 2 shows the normal plot of the coefficients in the equation for VT. It can be easily seen that the coefficients for LG, N,hdose, and to, are significant. However, the significance of all of the coefficients are sometimes not readily determined from these probability

3

-100 0 100 200

Coefficients for V T (mV)

Fig. 2. equation for the threshold voltage V,.

Normal probability plot of the coefficients in the second-order

plots. For example, the significance of the coefficient for the term L& is not clear from Fig. 2. Therefore, this graphical method of determining the significant coefficients is further supplemented by using F-statistics. (For a discussion of F- statistics see [ 121.) Factors for which the effect is found to be significant at a confidence level less than 95% are removed from the model. In this way, a reduced model is obtained for each of the electrical parameters, and the models consist of only those terms which are determined to be significant. The resulting set of six equations for the six electrical parameters is given in Table 11. Table 111 shows the significance of the model and lack of fit for the reduced model (for details of the calculations, refer to [12]). It can be seen that for all the six responses, the regression of these models exceeds 99% significance. At the same time, the significance of the lack of fit is found to be much less than the significance of the regression. In other words, the statistical analysis shows that the derived empirical models can represent the simulated data to a high degreee of accuracy in the range of the anticipated manufacturing variations. Therefore, we can use the analytical equations to determine the effect of variations in the key device doping and structural parameters on the key device electrical parameters for variations of the doping and structural parameters in the neighborhood of their nominal values. For example, in the equation for threshold voltage in Table 11, we see that the input parameters that have significant effect on threshold voltage are LG, to,, and N,hdose. The significance of variations in the above three parameters on threshold voltage can readily be predicted from basic device physics especially for long-channel, single source-drain MOSFETs. However, the equations given in Table I1 provide a simpler quantitative measure of the effect of the variations in input parameters on the key device electrical characteristics of a more complex MOSFET structure. Moreover, as the device dimensions are scaled to the deep submicron regime, due to the dominant 2-D nature of the problem, effects of variations in some of the doping and structural parameters are not readily understood from a simple 1-D analysis.

An examination of the equations in Table I1 reveals that gate length and oxide thickness variations, followed by channel doping variations, generally have the strongest contribution to the variations in most of the electrical characteristics.

HASNAT er al.: A MANUFACTURING SENSITIVITY ANALYSIS OF 0.35fim LDD 57

TABLE I1 SECOND-ORDER MODELS FOR THE ELECTRICAL PARAMETERS

Electrical Parameter Model Equations VT (mV) ~ V T (mV) I s a t ( w W "

S(mV/decade of I D ) IleadLOg A I w )

\% = 679.25 + 3 3 . 8 4 L ~ +67.77t0, + 47.67ivch dose -13.06L: ~ V T = 36.85 - 2 3 . 3 5 L ~ + 6.04tOx -6.31NCh dose+ 15.62L: Isat = 660.77 - 48.66L6-46.67tOx -35.73Nch dose-60.67tS, + 5 2 . 5 5 X J ( N + ) + 25.58Lc x t a p - 2 5 . 7 8 L ~ X ,U,(iV+) S = 95.82 + 1 . 3 3 L ~ + 2.38tOx + 1.05Nc,,dose Iieat = -10.77 - 0.320Lc-0.228tO, -0.294Nch dose + 0 . 1 3 3 X J ( N + ) + 0 . 0 8 9 X J ( N - ) + 0.191L: +0.104Lc X E& dose - 0 . 1 0 9 L ~ x x , ( N - ) Is,,& = 12.47 - 2.73L~-1.77N,hdOse-1.71t,,-1.83,~,(N-) + 1 . 8 6 X J ( N + ) + 1.57N - dose + 1.76t:,-0.92ts, x X J ( N + ) - 1.17X,(A1-) x N - dose- 0.97N - dose xL'i.,(N+) - 0.62Nc,,dose x X , ( N - )

Is U b ( w U m )

TABLE 111 SIGNIFICANCE OF THE REGRESSOR AND THE LACK

OF FIT FOR THE SECOND-ORDER MODELS

Response Significance of the Significance of the lack regressor (%) of fit (%) 99.9 23.0 99.9 99.9 99.9 99.9

37.2 67.2 9.0 22.2

Isub 99.9 89.3

Variations in the spacer oxide thickness(t,,) have a significant effect on Isat and I s & because of the strong influence of t,, on series resistance and the channel peak electric field, respectively. The effect of xj(N+) on I s a t and I S U b can be attributed to the fact that the effective length of the N - region of an LDD MOSFET is strongly dependent on the total amount of lateral diffusion of the N + junction depth under the spacer oxide. Since the lateral diffusion is a fixed percentage of the junction depth, the total length of the N - region is reduced as X j ( N + ) is increased. This fact is manifested as a significant positive coefficient for the X j ( N + ) term in the equations for I sa t and I s&, since a shorter N - region increases Isat and I S u b due to reduced series resistance and increased electric field, respectively.

The set of equations in Table I1 establishes the quantitative relationships between the variations of the key device and doping parameters LG, to,, N,hdose, tsp, X j ( N - ) , N-dose, and X j ( N + ) , and the resulting variations in the key device electrical characteristics, VT, AV,, s, I t e a k , I s a t , and I s&.

With this quantitative relationships, it is then possible to understand the structure/doping variations that have the largest contribution to the device electrical parameter variations. Also, it is desirable to be able to predict the statistical distributions of each of the key electrical parameters for a given range of ran- dom variations in the structure and doping parameters. In the following section, a simple Monte Carlo approach is applied to predict the statistical distribution of key device parameters which ressult from the random manufacturing variations in the structure and doping parameters by using the quantitative relationships developed in this section and given in Table 11.

Iv . STATISTICAL DISTRIBUTION OF ELECTRICAL PARAMETERS

A Monte Carlo approach has been applied to predit the statistical distributions of the key device electrical parameters using the equations in Table 11. In this approach, manufacturing

variations in the structural and doping parameters are assumed to be random with a normal distribution. The mean and standard deviation of the doping and structural parameters are given in Table I. For each Monte Carlo trial, a random generator based on a normal distribution is used to generate a value for each of the input parameters. The equations in Table I1 are then used to calculate the device electrical parameters for that trial. This information is stored, and many trials are executed in order to generate the resulting distributions for the electrical parameters. Then, the distribution of electrical parameters is analyzed to determine the mean and standard deviation of the normal distribution of the normal distribution which best describe the electrical parameters and its varia- tions. The resulting distributions for all of the key electrical parameters are shown in Fig. 3, for which 5000 trials were used to generate the distributions. Also shown in the figure are the fitted normal distribution and its standard deviation for all of the electrical parameters. The normal distributions calculated with the same mean and standard deviation as that of the key device electrical parameters show that most of the distributions for the device electrical parameters are fairly normal. However, the distribution for AV, shows a marked skewness. This is because of the presence of the L& term with a significantly large coefficient, and the square of a normally distri+buted variable tends to have a chi-square distribution.

The above analysis is extremely useful for understanding what improvements in the structural and doping parameters are required to reduce the spread in any electrical parameters. The degree of required improvements in the input parameters, as well as the trade-off among the input parameters can be determined quickly. For example, suppose that it is necessary to reduce the variation in VT by 20%. The equation for VT in Table I1 tells us that the reduction in the standard deviation (a) for VT can be achieved by reducing the manufacturing variations in LG, to, and N,hdose. One possible approach for reducing the standard deviation for VT is to reduce the manufacturing variation of one of the above three structure and doping parameters. The Monte Carlo analysis reveals that the required reduction in (T for VT cannot be achieved by only reducing the standard deviations for LG or for N,hdose. However, by reducing (T for to, by 45%, the a for VT can be reduced by 20%. Such a large reduction in (T for to,, however, may not be feasible with the present technology. Another possible approach is to simultaneously reduce the

58 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. I , NO. 1. FEBRUARY 1994

0.015

Mean = 077 mV Std. dev. (e) = 30 mV -

. Mean = 39 mV 0.m -Std. dev. (e) = 9 mV

0e D

3.0

2.5

h .+ 0.0

8 P h 1.6

s e) - 2 1.0

t 0

0.6

0.0

o,5 1 Mean=90 mv Std. dev.(u)=l.O mV

Yean=10 pA/w Std. dev.(u)=apA/gm

6 e 7 no10 90 50 40 80070110

0.3

h .- a 2 0.0

h .- - a % 0.1

P

0.a

S (mV/dec. of I,)

( 4

Mean=l3 u/jm Std. dev.(e)= 1.0 M/pm

Fig. 3. Predicted distributions of six key derice electrical parameters for the random variations of the structure and doping parameters given in Table I. (a) Threshold voltage V,. (b) AVTdue to drain-induced barrier lowering (DIBL). (c) Saturation current Isat. (d) Subthreshold slope S,(e) Off-state leakage current at 100°C I leak. (f) Peak substrate current I S u b . The solid lines are Monte Carlo calculated distributions, and the dashed lines are normal curves with mean and standard deviation obtained from the calculated distributions.

variations in more than one input parameter. However, it should be kept in mind that the reduction in the manufacturing of a

difficult to achieve. For example, if it is assumed that it is not structural parameters has been analyzed. Process and device possible to reduce the manufacturing variations in LG with simulators along with experimental design methodologies have the present lithographic capabilities, the Monte Carlo analysis can be performed to determine the required reductions in (T for been used to obtain a set of quantitative relationships between Nchdose and to, to reduce the variability in VT. The analysis the key device electrical parameters and the major doping reveals that a 30% reduction in the standard devations for and Structural Pameters. These equations have been used to to, and NchdoSe will reduce for VT by 20%. A similar predict the statistical variations in the electrical parameters analysis can be performed for the other key device electrical due to manufacturing variations in the structure and doping parameters. parameters by utilizing a Monte Carlo approach. Results of our

V. CONCLUSION

In this paper the sensitivity of the Of Some Of the input parameters may be more 0.35 ~ LDD MOSFET to the variations in the doping and

HASNAT er al.: A MANUFACTURING SENSITIVITY ANALYSIS OF 0.35j~m LDD 59

Monte Carlo analysis reveal that even if the input parameters are assumed to have normal distribution, the distributions of some of the key device electrical parameters may show marked skewness due to the presence of pure quadratic terms with a significantly large coefficient in the analytic expressions. In addition, the Monte Carlo analysis can be repeated in order to evaluate the device key electrical parameter distributions that result when the various input parameters are assumed to have different degrees of process control. Such a quantitative analysis provides a much more accurate understanding of the trade-offs of the degress of process control and the electrical parameter control.

REFERENCES

[ l ] Y. Aoki, H. Masuda, S. Shimada, and S. Sato, “A new design-centering methodology for VLSI device development,” IEEE Trans. Computer- Aided Design, vol. CAD-6, no. 3, pp. 452461, 1987.

[2] A. R. Alvarez, B. L. Abdi, B. L. Young, H. D. Weed, J. Teplike, and E. R. Herald, “Application of statistical design and response surface methods to computer-aided VLSI device design,” IEEE Trans. Computer-Aided Design, vol. 7, no. 2, pp. 272-288, 1988.

[3] K. K. Low and S. W. Director, “An efficient methodology for building macromodels of IC fabrication processes,” IEEE Trans. Computer-Aided Design, vol. 8, no. 12, pp. 1299-1313, 1989.

[4] S. Sharifzadeh, J. R. Koehler, A. B. Owen, and J. D. Schott, “Using simulators to model transmitted variability in IC manufacturing,” IEEE Trans. Semicond. Manuf., vol. 2, no. 3, pp. 82-93, 1989.

[ 5 ] H. Masuda, F. Otsuka, Y. Aoki, S. Sato, and S. Shimada, “Response surface methods for submicron MOSFETs characterization with variable transformation technology,” IEICE Transactions,, vol. E 74, no. 6, pp.

[6] T. J. Sanders, K. Rekab, F. M. Rotella, and D. P. Means, “Integrated circuit design for manufacturing through statistical simulation of process steps,” IEEE Trans. Semicond. Manu$, vol. 5 , no. 4, pp. 368-372, 1992.

[7] M. Cecchetti, M. Lissoni, C. Lombardi, and A. Marmiroli, “Process analysis using RSM and simulation,” Microelectron. Eng., vol. 19, pp.

[8] D. Montgomery, Design and Analysis of Experiments. New York: Wiley, 1991, ch. 16.

[9] SUPREM 3, Version 8920. Technical Modeling Association, Inc., Palo Alto, CA, 1989.

[lo] PISCES ZB, Version 8908. Technical Modeling Association, Inc., Palo Alto, CA, 1989.

[ 111 TSUPREM-4, Version 9035. Technical Modeling Association, Inc., Palo Alto, CA, 1990.

[I21 D. Montgomery, Design and Analysis of Experiments. New York: Wiley, 1991, ch. 15.

[I31 C. Daniel, “Use of half-normal plot in integrating factorial two-level experiments,” Technometrics, 1959.

1621-1633, 1991.

511-516, 1992.

Khaled Hasnat was bom in Dhaka, Bangladesh, on July 6, 1964. He received the B.S. degree in elec- trical and electronics engineering from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 1988 and the M.S. degree in elec- trical engineering from the University of Texas at Austin, in 1991. where he is currently working towards the Ph.D. degree in electrical engineering.

His current research interest is in the modeling and simulation of hot-carrier effects in submicrom- eter MOSFETs.

Suhail Murtaza was bom in Aligarh, India, on October 14, 1967. He received the B.S degree in electncal engineenng from the Aligarh Muslim Uruversity, India, in 1988. After working at the same university for one year as a lecturer, he moved to The University of Texas at Austin where he received his M S in manufactunng engineenng in 1991. Currently, he is ais working toward the Ph D degree at the same University in electncal and computer engineenng

His research interests are In the areas of semi- conductor manufactunng and Investigating the physical properties of sill- con-germanium alloys

AI F. Tasch, Jr. (M’77-SM’80-F’84) received the B.S. degree in physics in 1963 from the University of Texas, Austin, and the M.S. and Ph.D. degrees in physics in 1965 and 1969, respectively, from the University of Illinois, Urbana-Champaign. His thesis research in impurities in silicon was the pioneering work that led to the widely known deep- level transient spectroscopy (DLTS) approach for characterizing impurities in semiconductors.

In 1969, he joined Texas Instruments, Dallas, TX. From 1969 to 1970, his research on the surface of

HgCdTe resulted in the first reported demonstration of an MIS structure in HgCdTe, and helped lay the foundation for today’s infrared detector development. In 1970-1971, he was a member of a group at Texas Instruments which worked on the improvement of yield in a revolutionary automated MOS IC manufacturing facility. From 1972 to 1982, he worked on CCD memories, DRAMS and MOS VLSI device technology. He and his group did pioneering work in MOS dynamic memory, silicon-on-insulator, and scaled MOS transistors with sidewall oxides and self-aligned sililcided gates and source-drains. He joined Motorola in 1982 to start-up a new MOS integrated circuit manufacturing facility. In 1984, he was promoted to Director of the MOS technology development laboratory, and he was appointed Vice President of the Technical Staff in 1985. In July 1986, he joined the faculty the Department of Electrical and Computer Engineering at The University of Texas at Austin, occupying the Cockrell Family Regents Chair in Engineering. He holds 34 U.S. Patents.

Dr. Tasch is a member of the Electrochemical Society and the Materials Research Society. In 1978, he was honored as a Texas Instruments Fellow, and in 1983 he was elected an IEEE Fellow. In 1988 he received the J. J. Ebers award from the IEEE for outstanding contributions to electron devices, and in 1989 he was elected to the National Academy of Engineering.