A F R ASIC X SPECTROSCOPY (b) X-rays from Jupiter observed with the Chandra X-ray observatory....

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POLITECNICO DI MILANODEPARTMENT OF ELECTRONICS, INFORMATION AND BIOENGINEERING

DOCTORAL PROGRAM IN INFORMATION TECHNOLOGY

A FAMILY OF READOUT ASICS FOR X AND γ-RAYS

SPECTROSCOPY.

Doctoral Dissertation of:Riccardo Quaglia

Supervisor:Prof. Carlo E. Fiorini

Tutor:Prof. Angelo Geraci

The Chair of the Doctoral Program:Prof. Carlo E. Fiorini

2013 - XXVI

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Abstract

THE aim of my Doctoral activity has been the study, the design, the characteri-zation of integrated circuits designed for different applications in the field ofnuclear electronics.

Nowadays, advanced microelectronics processes have made possible advanced sig-nal processing with dedicated ASICs (Application Specific Integrated Circuit) for thereadout of an increased number of channels, ensuring at the same time compactness,low noise and low power in the systems.

My work in these years has been especially focused on the design of integratedcircuits for Silicon Drift Detectors used both in X-ray and γ-ray applications. SiliconDrift Detectors (SDDs) are relatively recent devices, invented by E. Gatti and P. Rehakin 1983, that are now the de facto standard in low noise, high rate X-ray detection (forinstance EDX, EDS, XRF, etc..) in the typical range 0.2 - 30 keV, but they are also acompetitive alternative to photomultiplier tubes (PMTs) for the readout of light fromscintillators, thanks to their high quantum efficiency and low electronic noise. Thesimultaneous presence of these two important peculiarities makes SDDs in advantagein scintillator readout with respect to other photodetectors, for example PIN diodes(higher noise) or Silicon PhotoMultipliers (huge improvements in the last few years butstill a lower photo detection efficiency) despite of the need to moderate cool them inreal applications. The advantages of SDDs with respect to PMTs are in robustness andcompactness and they allow a simpler use in extreme conditions such as astronomicalobservatories on satellites or interplanetary missions; furthermore the compatibility ofsilicon detectors to high magnetic fields allows also the use of SDDs arrays in nuclearimaging combined to Magnetic Resonance Imaging (MRI).

The first Chapter is the introduction of this work with particular emphasis on themotivations behind the solutions adopted in the design of the circuits presented in thefollowing chapters .

The Second Chapter introduces Silicon Drift Detectors (SDD), with a brief expla-nation of the working principle, and the electronics reading chain used in the radiationsensors readout, with fundamentals of signal processing. In this chapter the readout ofSDD based on CMOS preamplifier is also introduced as alternative of more traditional

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JFET based topologies.The third Chapter describes a first circuit originally developed to be use in the so

called High Time Resolution Spectrometer (HTRS), where strict requirements in timeresolution, system throughput and noise, have required a complicated and innovativedesign.

The fourth Chapter is about the development of a γ-ray spectrometer in the rangeof 150 keV - 15 MeV based on LaBr3(Ce) scintillators read by SDD arrays for fu-ture interplanetary mission, a project funded by the European Space Agency (ESA).This chapter includes also the characterization of SDDs coupled with scintillators, thedescription of the ASIC designed and the preliminaries results of the complete system.

The fifth Chapter describes another integrated circuit for multi-detectors (SDD,PMT, Ge, SiLi, etc..) readout, VERDI - VErsatile Readout for Detector Integration,designed in the previous years in our laboratories and my work in the design and thecharacterization of the third version (VERDI-3) of this ASIC.

The last Chapter is about the ongoing use of the circuits presented in the previouschapters in other projects and a view towards a single ASIC that includes most of thepresented functionalities and innovations .

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Contents

1 Introduction 11.0.1 Motivations of the Dissertation . . . . . . . . . . . . . . . . . . 5

2 Silicon Drift Detector 72.1 Fundamentals of Signal Processing . . . . . . . . . . . . . . . . . . . . 8

2.1.1 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1.2 ENC Optimization . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Silicon Drift Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.1 Working principle . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.2 SDDs for X-ray spectroscopy . . . . . . . . . . . . . . . . . . . 212.2.3 Preamplification of signals from SDD . . . . . . . . . . . . . . . 232.2.4 Silicon Drift Detector as scintillator light sensor . . . . . . . . . 28

3 HTRS: High Time Resolution Spectrometer 353.1 IXO-HTRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.1.1 Requirements for the HTRS instrument . . . . . . . . . . . . . . 363.1.2 Pile-up issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.1.3 Choice of the shaping filter . . . . . . . . . . . . . . . . . . . . 40

3.2 The HTRS chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.2.1 Design: Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . 483.2.2 Design: Shaper Amplifier . . . . . . . . . . . . . . . . . . . . . 543.2.3 Design: Base Line Holder . . . . . . . . . . . . . . . . . . . . . 593.2.4 Design: Peak Stretcher and Pile-Up Rejector . . . . . . . . . . . 693.2.5 Design: Peripheral circuits . . . . . . . . . . . . . . . . . . . . 74

3.3 Experimental Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . 783.4 Experimental Characterization . . . . . . . . . . . . . . . . . . . . . . 78

3.4.1 Tests with CMOS preamplifier. . . . . . . . . . . . . . . . . . . 82

4 ESA project 874.1 Introduction to ESA project . . . . . . . . . . . . . . . . . . . . . . . 884.2 Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Contents

4.2.1 Single Side Biasing . . . . . . . . . . . . . . . . . . . . . . . . 904.2.2 Energy resolution with scintillator and SDD detector . . . . . . . 94

4.3 LaBr3:Ce scintillators . . . . . . . . . . . . . . . . . . . . . . . . . . . 954.4 Detection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974.5 ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.5.1 Dynamic range . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.5.2 Design: Shaper and BLH . . . . . . . . . . . . . . . . . . . . . 1024.5.3 Design: Peak detector . . . . . . . . . . . . . . . . . . . . . . . 1074.5.4 Design: Complete ASIC . . . . . . . . . . . . . . . . . . . . . . 109

4.6 Testing: ASIC set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104.6.1 ASIC characterization . . . . . . . . . . . . . . . . . . . . . . . 112

4.7 Testing: Single Detector . . . . . . . . . . . . . . . . . . . . . . . . . 1154.7.1 X-ray characterization . . . . . . . . . . . . . . . . . . . . . . . 1174.7.2 γ-ray characterization . . . . . . . . . . . . . . . . . . . . . . . 125

4.8 Array and Large LaBr3:Ce Scintillators . . . . . . . . . . . . . . . . . 125

5 VERDI 1315.1 VERDI-3 ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.1.1 Design: Analog Channel . . . . . . . . . . . . . . . . . . . . . 1345.2 Testing and Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.2.1 Tests with detectors . . . . . . . . . . . . . . . . . . . . . . . . 141

6 Other Projects and New Developments 1456.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466.2 SIDDHARTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.2.1 Improvements of CUBE preamplifier . . . . . . . . . . . . . . . 1506.3 GAMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516.4 INSERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546.5 Towards new readout ASICs . . . . . . . . . . . . . . . . . . . . . . . 157

7 Discussion and Conclusions 159

Bibliography 175

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CHAPTER1Introduction

Since their discovery by William Röntgen (Nobel prize for this work), that broughttheir properties to the attention of the scientific community in 1895, X-rays becomingmore and more popular during the twentieth century in many applications includingfor instance medical imaging in hospital or baggage and body scanner at airport secu-rity controls. Other applications developed during the years are not probably knownto the general public but their studies are widely diffused in the many applications likephysics and astrophysics experiments or for elemental analysis of inorganic based mate-rials. Examples of astrophysical applications can be found in the XMM-Newton (X-rayMulti-Mirror Mission-Newton) an orbiting X-ray observatory by the European SpaceAgency (ESA) or in the Chandra X-ray Observatory another space telescope by NASA,both launched in 1999. Fig. 1.1 shows images from Chandra X-ray Observatory.

These observatories are mainly dedicated to X-ray imaging and detectors are CCD(Charge Couple Device) but a new generation of instruments are under study and newrequirements in higher rate, efficiency and better energy resolution open to the devel-opment of new photodetectors. An example of new concept of experiment with SiliconDrift Detectors as device photodetector will be briefly described during the thesis.An example of elemental analysis is for instance the X-ray Fluorescence (XRF). XRFis an analytical technique that uses the interaction of X-rays with the material to deter-mine its elemental composition. Orbiting electrons in a stable atom are organised intoshells: each shell is made up of electrons with the same energy. When a high energyincident (primary) short-wavelength X-rays or gamma-ray collides with an atom it dis-turbs this stability, ionizing it (occurs if the energy of the incident photon is higher thanthe ionizing potential). An electron (or more) is ejected from a low energy level (egK shell) and its space is empty. As a result an electron from a higher energy level (egL shell) falls into this space. The difference in energy produced as the electron moves

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Chapter 1. Introduction

(a) In this image of a pulsar neutron stars (PSR B1509-58), the lowest energy X-raysthat Chandra detects are red, the medium range is green, and the most energeticones are colored blue.

(b) X-rays from Jupiter observed with the Chandra X-ray observatory.

Figure 1.1: Pictures obtained with X-rays observations with the Chandra X-ray observatory. Source:wikipedia.com

.

between these levels is released as photon with energy given by the difference of thetwo orbitals involved. The secondary X-rays emitted is therefore a characteristic of theelement composition of the atom present.XRF is widely used as a fast characterization tool in many analytical applications byindustries in many fields:

- metallurgy;

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- electronics;

- archaeology and cultural heritage;

- geology and mining;

- glass and ceramic manufacturers;

- medical devices;

and many others. Fig. 1.2 reports an example of XRF spectrum.

Figure 1.2: Example of XRF spectrum of an automotive catalyst. Source: www.amptek.com.

The benefits of XRF are in minimal or no sample preparation, non destructive analysis,no chemical reactions (no reagents or acids), quite rapid, qualitative and quantitativeanalysis, typical detection limit of around 0.01% for most elements and relatively lowcost and allows analysis on solids and powders.

The detectors for XRF measurements were historically Silicon Lithium Si(Li) orgermanium detectors. The Si(Li) detectors, which are essentially P-I-N devices formedby lithium compensation or drifting of p-type silicon, are the result of a very com-plicated and expensive manufacturing processes. The number of electron-hole pairsformed depends on the energy of the incoming X-Ray. Higher the X-ray energy of theincident photon, higher is the number of e-h pairs. A very high voltage is applied tobias the device. To provide acceptable energy resolution, these detectors are typicallycooled with liquid nitrogen, to obtain resulting in typical resolution of lower than 160eV. Also Ge detectors had found application in XRF but they have the main drawbackof the impossibility to go below 10-11 keV, an interesting energy range in many appli-cations.

SDDs became over the years first a valid alternative to Si(Li) and than most populardetector for XRF analysis. The advantages are many:

- high count rates and processing (hundreds of kcps);

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- excellent energy resolution;

- good peak to background (7 - 20 k but lower than Si(Li) 15 - 25 k);

- they work moderately cooled with Peltier stages, -20 -30 °C, without complicatedliquid nitrogen cooling system;

The only relevant drawback is that SDDs are made with 500 µm silicon wafer and thislimits the maximum energy range of the application (while for instance Si(Li) can havethickness of millimetres), but the most relevant analysis are below 30 keV where theefficiency of SDD is still good. In some low cost applications also silicon pin diodesare used but their limitations compromise the sensitivity.

From Fig. 1.2 the possibility to distinguish energy peaks close together is correlatedto the narrowness of the peak itself, i.e. a low noise in the detection system becausenoise modifies the amplitude of the detected signal and therefore the estimation of thecharge collected by the detector and the corresponding energy of the incident X-rayphoton. An interesting research field is combine the design of Application SpecificIntegrated Circuits ASICs for the acquisition of signals from SDDs in order to reachthe best performance of energy resolution with compactness, low power and high ef-ficiency. The flexibility of ASIC allows also to design circuits with multiple channelsin order to create a compact system with a high number of detectors. The applicationof a superior energy resolution or the higher efficiency with high count rates allow toimprove the performance of the cited applications, for instance a high rate system canreduce the analysis time required simply moving the detector closer to the sample undertest without degradation. Detectors produced with high density semiconductors suchas cadmium telluride (CdTe) and cadmium zinc telluride (CdZnTe) have improved ef-ficiency at higher X-ray energies, are capable of room temperature operation and theyare a very interesting evolution but actually their very high cost impedes the diffusion.

During the years also the study of γ-rays has become very interesting for differentapplications from the pure gamma spectroscopy to applications in nuclear imaging (forinstance SPECT and PET).Starting from the first experiments in the field of γ-imaging for biomedical applications,scintillators materials have been used coupled with photomultipliers tubes, for instancea PMT coupled with a large continuous NaI(TI) scintillator.Scintillator, a transducer that converts the gamma radiation into visible light flash easilyreadable, technology had over the years a great improvement and modern scintillatorslike for instance LaBr3:Ce allows very good performance in γ-rays spectroscopy. Asexamples, the following table reports the main properties of the common scintillatormaterials used for γ-rays applications.

An alternative to the combination of PMT and scintillator, is the use of high-densitydirect conversion devices that have several potential advantages with respect to the indi-rect conversion with scintillators, first of all the energy resolution. The following tablelists some materials used for direct conversion γ-ray detection with the reference valueof the silicon.The use of these detectors is very interesting but usually very expensive and limited

to medium low energy γ-rays in medical imaging, for instance CZT cameras for 99mTc

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Density Maximum Decay time Light[g cm-3] Emission [ns] Yield

[cm-1] [ph/keV]

NaI(Tl) 3.67 415 230 38LaCl3(Ce) 3.86 330 20, 213 49CsI(Tl) 4.51 540 680, 3340 65LaBr3:Ce 5.30 358 35 64

Table 1.1: Relevant properties of the most common used scintillator materials.

Density Attenuation Energy Electron Hole[g cm−3] at 140 keV [eV] mobility mobility

[cm−1] [cm2V−1] [cm2V−1]

Si 2.33 0.02 3.61 0.42 0.22Ge 5.32 0.72 2.98 0.72 0.84CdTe 5.85 3.22 4.43 3x10−3 5x10−4

CdZnTe 5.82 3.07 5 3x10−3 5x10−5

HgI2 6.40 8.03 4.20 <10−2 5x10−5

Table 1.2: Relevant properties of semiconductor materials included materials used for direct conversionγ-rays detectors.

140 keV energy in SPECT applications. In application with high energy γ-rays the useof scintillators coupled to PMT is still the most common solution.In the last decades many efforts have been made to overcome the use of PMTs, that havelimitations in compactness, robustness and reduced linearity due to saturation phenom-ena in extended γ-rays range, i.e. when the contemporary detection of photons with avery different energy (for instance two decades) is required. A possible alternative isthe use of SDDs (or SDDs arrays for bigger area) as scintillation light detector. Thanksto their high quantum efficiency, very low electronics noise and the possibility to real-ize quite big area detectors without penalization of noise performance (unlike P-I-Nsdetectors in SDDs the output capacitance is independent from the active area), SDDshave shown to be very interesting and at the state of art also in this field. A mono-lithic silicon as detector can be a suitable solution for interplanetary experiments (anexample reported in the thesis) or for applications where the γ-ray should be detectedin presence of high magnetic fields that prevents the PMT operation.

1.0.1 Motivations of the Dissertation

The development of integrated readout electronics for radiation detectors is an activityoften strictly connected to the required application in order to fully exploit the advan-tages of microelectronics processes in terms of compactness, low noise, low power andreconfigurability in the design. The flexibility of ASICs allows to design integratedcircuits with multiple reconfigurable options to adapt the circuit to a specific appli-cation. Multichannel architectures are required to adapt the electronics readout to ahigher number of channels in more and more complicated detection systems. Aim ofthis work is to present the solutions adopted and the design philosophy pursued in thedesign of a family of ASIC designed for different applications from X-rays and γ-rays

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spectroscopy with SDDs, to readout of multiple detectors.

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CHAPTER2Silicon Drift Detector

Silicon Drift Detector (SDD) is a ionizing radiation detector characterized by a very lowcapacitance at the collecting anode, independent of the total active area of the device.Thanks to this characteristic, SDDs are particularly suitable for X ray spectroscopy butthey are also a valid alternative to PMT or other photodetectors as scintillator light sen-sor in γ-ray detection. Circuits and systems presented in this thesis have been designedto work with SDDs of different sizes and shapes, aim of this chapter is to describe theworking principle of this detector and the fundamentals of signal processing theory.

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Chapter 2. Silicon Drift Detector

2.1 Fundamentals of Signal Processing

The electronics readout of signals from Silicon Drift Detectors, but in general fromradiation detectors, has the role to measure with the maximum accuracy the value of thecharge delivered to the detector. If we consider a traditional time-invariant analog basedreadout, the electronics chain is composed by the cascade of different basic blocks: apreamplifier, a shaping amplifier, a peak detector, an analog-to-digital (ADC) converterand a digital system for storing and processing data (Fig. 2.1) [1].

Figure 2.1: Blocks diagram for a generic radiation detector readout.

The preamplifier is used for the first amplification of the signal from the detector, avery common configuration is the charge-preamplifier where the detector is connectedto a virtual ground and the charge Q is integrated on a feedback capacitance Cf. As-suming a delta charged collected, the output of the preamplifier is a step-like voltagewaveform with an amplitude proportional to Q. A possible alternative is the voltagepreamplifier, in which the charge Q is integrated on an equivalent capacitance which isthe sum of the capacitance of the detector and the input capacitance of the voltage am-plifier. The charge preamplifier has the main advantage to have a gain depending onlyfrom the feedback capacitance and insensitive to the variations of the detector one.

The second stage is the shaping amplifier which provide a further amplification ofthe signal and a filtering in order to improve the signal-to-noise ratio (S/N). The outputvoltage is proportional to the amplitude of the input voltage step.

Following blocks have the role to measure the amplitude of the voltage at the outputof the shaping amplifier (peak detector), to convert the analog signal in a data stream(ADC) and to provide an analysis of the data acquired (MCA).

Noise sources in the electronic circuits affect the measurement of the amplitudeof the voltage pulse and, therefore, the estimation of the charge Q. The detector canbe modelled by a current generator which provide an ideal δ-like current pulse with Qarea, in parallel with the detector capacitance CD. Fig. 2.2 shows the electrical model ofthe detector with input-referred equivalent noise generators of the front-end electronics.CG is the capacitance added by the front-end, and it is usually dominated by the gatecapacitance of the input transistor of the preamplifier.

2.1.1 Noise Analysis

The precision of the measurement of Q is usually defined in terms of signal to noiseratio (S/N) or, in a different formulation widely used in the field of radiation detection,

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2.1. Fundamentals of Signal Processing

Figure 2.2: Electrical model of the detector with the equivalent noise generators.

with the Equivalent Noise Charge (ENC) [1]. The ENC is defined as the charge deliv-ered by the detector which produces at the output of the electronic chain a pulse withan amplitude equals to the rms noise value (i.e. a signal to noise ratio S/N = 1). Theinput signal can be defined as a δ-like pulse:

id(t) = Qδ(t) (2.1)

The S/N is defined as the ratio between the peak amplitude of the signal and the rootmean square value of the noise, both measured in the same point, for example at theoutput of the shaping amplifier:

S

N=Max[vout√〈v2noise〉

=QMax[vout−δ(t)]√

〈v2noise〉

(2.2)

where vout−δ(t) corresponds to the pulse at the output of the shaping amplifier when thedetector delivers a charge equal to one (Q=1). The ENC is:

ENC =

√〈v2noise〉

Max[vout−δ(t)](2.3)

In Fig. 2.2 the input referred noise generators can be used to represent at the inputof the system all the electronics noise of the front-end (vnoise in 2.2 - 2.3). The noisecontributions can be summarized in three sources: white current noise (Siw), whitevoltage noise (Svw) and 1/f voltage noise (Sv1/f ). A fourth term that can be consideredis the 1/f current noise but its contribution is usually negligible and it complicates themathematical analysis. In a first approximation the dominant contributions are givenby the shot noise associated to the detector leakage current and by the noise of the firsttransistor of the preamplifier. Others terms are here not considered but they could beanalysed in the same way referring their equivalent noise generators at the input of thechain.The white current source is related to all the shot noise at the input of the front-end:

- shot noise of the leakage current of the detector IDL with white spectral density:

SiDL = qIDL (2.4)

- shot noise of the gate leakage current of the first transistor of the preamplifier:

SiG = qIG (2.5)

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(this term is particolary important if the first transistor is a JFET or a MOSFET inan ultrascaled CMOS technology).

- shot noise (thermal) of a resistor, if present, used to fix the biasing of the detector:

SiR = qIR =2kT

R(2.6)

The equivalent generator has a spectral density given by the sum of these contributions:

Siw = qIDL + qIG + qIR = qITL = b (2.7)

with ITL the total leakage current.The white voltage source, considering only the noise of the first transistor of the pream-plifier, is the thermal noise of the transistor:

Svw = α2kT

gm= α

2kT

CGωT= a (2.8)

where ωT is the cut-off angular frequency and α is a constant that depends on thetechnology (for Si is from 2/3 to values higher than 1 in scaled processes).The flicker voltage source is mainly related to trapping phenomena in the channelregion of the first transistor, it has a ω−1 spectral power density:

Svf (ω) =1

2

Af|f |

= α2kT

CG

ωcωT

1

|ω|=c

ω(2.9)

where Af is the 1/f noise coefficient of the technology and ωc is defined as the cornerfrequency in which the 1/f noise spectrum is equal to the white noise spectrum.

2.1.1.1 Calculation of the ENC

The simplest way for the calculation of 2.3 is proceed in the Laplace domain for time-invariant systems. The input signal is therefore:

id(t) = Qδ(t)⇒ Id(s) = Q (2.10)

The signal at the output of the charge preamplifier:

v(t) = Q1

CFu(t)⇒ V (s) =

Q

CF

1

s(2.11)

The signal at the output of the shaper:

vout(t) = Q1

CFL−1[

1

sTC(s)]⇒ Vout(s) = V (s)TC(s) =

Q

CF

1

sTC(s) (2.12)

with Tc the shaper filter transfer function. Also the output RMS noise can be evaluatedin the frequency domain using the noise sources estimated in the previous section.The noise power spectrum at the output of the shaper is:

Sn(ω) =

[(a+

πAf|ω|

)ω2(CD + CG)2 + b

]1

ω2C2F

|TC(jω)|2 (2.13)

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and the output rms noise:

〈v2noise〉 =

1

2π

∫ +∞

−∞Sn(ω)dω (2.14)

The ENC, according to 2.3 is the ratio between 2.14 and 2.13:

ENC2 =〈v2noise〉

Max2[vout−δ(t)]=

=

1

2π

∫ +∞−∞

[(a+

πAf|ω|

)ω2(CD + CG)2 + b

]1

ω2C2F

|TC(jω)|2d(ω)

1

C2F

Max2

(L−1

[1

sTC(s)

]) =

=

1

2π

∫ +∞−∞

[(a+

πAf|ω|

)(CD + CG)2 +

b

ω2

]|TC(jω)|2d(ω)

Max2

(L−1

[1

sTC(s)

])(2.15)

The term in the denominator, Max2

(L−1

[1

sTC(s)

])is a number and it can be

normalized to one with a proper gain of T (this does not affect the calculation of ENCbecause also the noise has the same gain).

The integral can be simplified applying a normalization to a characteristic ω and asubstitution with an a-dimensional variable x =

ω

ωc= ωτ ; τ is a characteristic time

of the filter and it is called shaping time. The definition can be general for instancethe time width at half height or the peaking time of the output of the filter or any othercharacteristic time. The 2.15 can be simplified:

ENC2 = (CD + CG)2a1

τ

1

2π

∫ +∞

−∞|TC(x)|2d(x) + bτ

1

2π

∫ +∞

−∞

1

x2|TC(x)|2d(x)+

+ (CD + CG)2c1

2π

∫ +∞

−∞

1

|x||TC(x)|2d(x)

(2.16)

The three integrals depend only on the shape (normalized) of the output of the filter.The equation can be simplified with the introduction of three "shaping factors" A1, A2,A3:

A1 =1

2π

∫ +∞

−∞|TC(x)|2d(x)

A2 =1

2π

∫ +∞

−∞

1

|x||TC(x)|2d(x)

A3 =1

2π

∫ +∞

−∞

1

x2|TC(x)|2d(x

(2.17)

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Figure 2.3: The ENC as function of the shaping time. The series, 1/f and parallel noises are highlighted.

The three factors A1, A2, A3 are defined according to the definitions of τ adoptedin the normalization. With a different definition of τ the values of the shaping factorsare different but, obviously, the ENC does not change. It is possible to switch fromdifferent definition of τ simply applying a transformation. For instance for a lineartransformation τ2=kτ1 the factors can be easily calculated as:

A1(τ2) = kA1(τ1)

A2(τ2) = A2(τ1)

A3(τ2) =1

kA3(τ1)

(2.18)

A compact formulation for the ENC can be written:

ENC2 = (CD + CG)2a1

τA1 + (CD + CG)2cA2 + bτA3 (2.19)

In this equation the first term represents the series noise, the second one the 1/f noiseand the last one the parallel noise. The series noise is inversely proportional to theshaping time τ, the 1/f noise is independent from τwhile the contribution of the parallelnoise is directly proportional. A typical plot of the ENC as a function of τ is reportedin Fig. 2.3 with the three noise contributions highlighted. The ENC calculation forvoltage-preamplifier is very similar to the charge-preamplifier one and it can be foundin [1].

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2.1.2 ENC Optimization

Using the explicit expressions of the noise generators, the 2.19 can be rewritten:

ENC2 = A1CD

(√CDCG

+

√CGCD

)2

α2KT

ωT

1

τ+

+ A2CD

(√CDCG

+

√CGCD

)2

α2KT

ωTωC+

+ A3qτITL

(2.20)

and it is minimized for a particular value of the shaping time:

τopt = (CD + CG)

√a

b

√A1

A3

(2.21)

The ENC value at τ=τopt is the best one obtainable with the given shaping filter, CDand CG, and noise sources (a,b,c):

ENC(τopt)2 = 2(CD + CG)

√ab√A1A3 + (CD + CG)2cA2 =

= 2√CD

(√CDCG

+

√CGCD

)√α

2KT

ωT

1

qITL

√A1A3+

+ CD

(√CDCG

+

√CGCD

)2

α2KT

ωTωCA2

(2.22)

In the second part of the equation, the term(√

CDCG

+

√CGCD

)is explicit and a

further optimization of the ENC can be done minimizing it. It happens with CD=CG,the so called detector-transistor capacitance matching condition.

Another optimization in the ENC is the best choice of the shape of the output of theshaping filter, i.e. the best A1,A2,A3. It is possible to demonstrate that with only whitenoise (voltage and current), the optimum filter is an ideal filter with an infinite-cuspresponse to an input step-like pulse.

vout(t) = e

(−|t|τ

)(2.23)

The optimal shaping time is the one that minimize the white series noise and thewhite parallel noise. The Fig. 2.4 shows the infinite-cusp shaped pulse response of thefilter.

This infinite-cusp response shaping filter is not realistic because it has infinite du-ration and it can not be implemented with analog circuits. Is is however interesting ascomparison because it sets the best ideal value of the ENC. The shaping factors can beeasily calculated:

A1 = 1

A2 =2

πA3 = 1

(2.24)

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Figure 2.4: Output of the optimum filter with only white series and white parallel noise

If the 1/f noise is considered the optimum shaping filter is different, a complete analysiscan be found in [2].

2.1.2.1 Real Shaping Filters

Real filters can only approximate the ideal optimum weighting function, in this para-graph the most common solutions are briefly presented.

CR-RCn FiltersCR-RCn filters are a very popular family of filters, in particular the CR-RC (n=1, twopoles one zero) was historically the most common filter for radiation detectors. In aCR-RC filter the output pulse is:

vout(t) =t

τSe−t

τS (2.25)

with τS = RC. The peaking time (time corresponding to the peak of the output) isτpeak = τS . An evolution of the CR-RC filter is the n-th order implementation, CR-RCn, that provide a better ENC performance. The n-th order is characterized by n+1real negative poles and a single zero in the origin. It can be implemented in a easy way:a differentiator with time constant τC = RC followed by a cascade of n approximatedintegrators with the same time constant. The output pulse in general is:

vout(t) =1

n!

(t

τS

)ne−t

τS (2.26)

The corresponding peaking time is τpeak = nτS .

Triangular and Trapezoidal Filters

These filters are characterized by an output response with a shape equal to their names,

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triangular or trapezoidal. They are both not practical to be implemented in a time-invariant mode because they need delay lines, while an easiest time-variant implemen-tation suffers from synchronization problems with random signals (but they are verysuitable when the arrival time of the signal is known). The main advantage of the trape-zoidal filter with respect to the triangular one is the easiest acquisition and digitalisationof the output (during the flat-top). An interesting implementation that tries to reducesynchronization problems for trapezoidal filters is presented in [3].

Filters with Complex Poles

A filter can be characterized by real poles (for instance CR-RCn) or by complex poles.The positions of the poles in the complex plane is the consequence of the approximationof the desired output shape. Different approximation in nuclear electronics are Bessel,Least Squares, parallel poles and the most popular one Semi-Gaussian. In Fig. 2.5the constellation of the approximation with seven and nine poles are shown: A more

Figure 2.5: Contellation of poles of the Semi-Gaussian filter with seven and 9 poles.

detailed analysis of the Semi-Gaussian filter (also with a comparison with CR-RCn) isreported in Chapter 3.

Shaping Factors for common used filters

Table 2.1 reports the shaping factors for different filters.In 2.1 the column τ indicates the characteristic time chosen for the calculation. The

column√A1A3 is reported because this value is an indication of worsening compared

to the optimum filter [1] (lower is better). The shaping factors for CR-RCn and Semi-Gaussian shaper have been calculated during the thesis where possible (real poles) byhand or with numerical approximations with MATLAB and Cadence. In this sectiononly analog filters have been presented, an alternative is the use of digital filters thathave the advantage to implement any desired weighting function but also the difficultyto integrate them in low power multi-channels circuits. Details about digital filteringtechniques of detectors signal can be found in many studies in the literature, for in-

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Filter τ A1 A2 A3

√A1A3

Infinit cusp τ 1 0.64 1 1CR-RC τpeak=RC 1.85 1.18 1.85 1.85CR-RC3 τpeak = 3RC 1.87 1.06 1.04 1.39CR-RC5 τpeak = 5RC 2.22 1.03 0.8 1.33CR-RC7 τpeak = 7RC 2.54 1.02 0.67 1.3Triangular Tbase/2 2 0.88 0.67 1.16Trapezoidal (TF-T=0.5TR) TR 2 1.18 1.16 1.52Trapezoidal (TF-T=TR) TR 2 1.38 1.67 1.83Trapezoidal (TF-T=2TR) TR 2 1.64 2.67 2.31Semi-Gaussian 3 poles τpeak 1.77 1.18 1.17 1.44Semi-Gaussian 5 poles τpeak 2.26 1.06 0.78 1.33Semi-Gaussian 7 poles τpeak 2.74 1.03 0.61 1.29Semi-Gaussian 9 poles τpeak 3.16 1.02 0.52 1.28

Table 2.1: Shaping factors. Some data from [1], others calculated by hand or with Matlab simulations.

stance [4].

Most of the circuits designed and presented in the next chapters are for Silicon DriftDetector, next section introduces this device.

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2.2. Silicon Drift Detectors

2.2 Silicon Drift Detectors

Silicon Drift Detector (SDD), introduced by E. Gatti and P. Rehak in 1983 [5–7], isa ionizing radiation detector characterized by a very low capacitance of the electrodecollecting the signal charge. This capacitance is independent on the active area of thedevice and its low value results in an overall low electronic noise (see previous sectionfor the correlation between low output capacitance and low electronic noise) that hasmade this detector ideal for high-resolution X-ray spectroscopy measurements.

In the years after its invention, the SDD has been developed in a large variety oftopologies for different applications. Originally, the SDD was designed as positionsensitive detector for high-energy physics experiments, by using the measurement ofelectrons drift time to reconstruct one coordinate of the particle interaction point whilethe second coordinate was given by a proper segmentation of the collecting anode [8,9].Then it founds application in the field of X-ray spectroscopy where it has become thestandard [10–12]. Recently SDDs have also demonstrated to be a competitive device forthe readout of scintillator in hard X-ray and γ-ray detection compared to conventionalphotodetectors [13, 14].

2.2.1 Working principle

The working principle of SDD can be understood starting from the conventional pindetector.In a conventional pin diode, the ohmic n+ and the rectifying p+ junctions extend overthe full area on opposite wafer sides (Figure 2.6a). The CD anode capacitance, that canbe estimated as a parallel-plate capacitor, has a value depending on the active area ofthe device, causing an high electronic noise. In the structure shown in Figure 2.6b, thebulk depletion can be achieved in a different way, by positively biasing a small ohmicn+ contact with respect to p+ electrodes covering both top and bottom of the wafer.

When the n+ voltage is high enough, the two space charge regions, separated bythe undepleted bulk, touch each other (Figure 2.6c), leading to a small undepleted bulkregion only close to the n+ electrode. The depletion is achieved in this way with anapplied voltage which is lower than the voltage needed for a conventional diode ofthe same thickness. The electron potential energy along the two p+ junctions can becalculated solving the one-dimensional Poisson’s equation:

d2φ1

dx2= −qND

ε(2.27)

where ND is the active donor concentration in the bulk, q is the electron charge and εthe Si dielectric constant. The equation has a solution:

φ1 = −qND

2ε(x− x0)2 + φ0 (2.28)

where φ0 and x0 are proper integration constants.The diagram of the electron potential energy, perpendicular to the wafer surface has

a parabolic shape, with a minimum located in the middle of the wafer (Figure 2.6c).

In the SDD an additional electric field parallel to the surface is added to force the

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(a)

(b)

(c)

Figure 2.6: Sideward depletion idea. With respect to a conventional PIN diode detector (a), the depletionof the bulk is achieved by positively biasing a small n+ electrode with respect to p+ electrodescovering both sides of the wafer (b). Increasing the voltage only an undepleted region near the n+

contact is present (c). For each scheme, it is shown the electron potential energy on the verticaldirection.

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Figure 2.7: SDD working principle, electrons generated in the energy potential minimum drift to thecollecting anode while holes to the p+ cathodes.

electrons collected in the energy potential minimum to drift towards the n+ anode, thatit becomes the collecting anode. This is achieved by implanting two arrays of p+ elec-trodes on both sides of the wafer (Figure 2.7), instead of the continuous p+ implantsshown as example in Figure 2.6.

These electrodes are correctly biased with a voltage gradient in order to provide anelectric field E parallel to the surface. A drawing of the potential energy in the driftingregion is shown in Figure 2.8a. The "gutter-like" shape is given by the sum of thepotential φ1 and of the potential:

φ2 = −Ey (2.29)

The electrons are focused in the central plane of the semiconductor by the field re-lated to φ1 and drifted towards the anode region by the electric field related to φ2.Theholes, driven by the depletion field φ1, are collected by the nearest p+ electrodes. In theregion close to the collecting anode (Figure 2.8b), the bottom of the potential channelis shifted toward the surface where the anode is placed by suitably biasing the elec-trodes on the opposite side. The cloud of electrons induces in the anode an output pulseonly when the electrons arrive close to it because of the electrostatic shield of the p+

electrode [15]. The drift time of the electrons with respect to a trigger can be used tomeasure one of the interaction coordinates while the collected charge allows to measurethe energy released by the incident ionizing event. In fact as briefly described, origi-nally, the SDD was designed as a position sensitive detector for high-energy physicsexperiments, using the measurement of the electrons drift time to reconstruct one coor-dinate of the particles interaction point [8, 9].

The main advantage of a Silicon Drift Detector with respect to a conventional p-ndiode of equivalent active area and thickness is the low value of the capacitance of then+ anode, which is in the order of few hundreds of fF, a value independent of the activearea of the device. This feature allows to reduce both the electronics noise and the valueof the shaping time to be used for processing the signal (see section 2.1).

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(a) Drift region.

(b) Anode region.

Figure 2.8: Electron energy potential diagrams in the drifting region of the SDD (a), and in the regionclose to the anode where the potential valley is directed towards the surface (b). The potential isrelated to the structure shown in Figure 2.7.

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2.2.2 SDDs for X-ray spectroscopy

SDDs are also an ideal device for high-resolution X and γ-ray spectroscopy measure-ments. To enhance the quantum efficiency in the soft X-ray region (E < 5 keV) or withvisible light, a new design has been developed with a particular care for the radiationentrance window, limiting as much as possible the insensitive area and optimizing thedoping profile to minimize charge loss.

In a detector of the type shown in Figure 2.7, the surface areas between the p+ stripsare covered by thermally grown SiO2. The fixed positive charge, always present withinthe oxide, bend the potential distribution downward at the detector surface and createlocal potential minima, which could collect the electrons generated close to the surface.This is an important limitation for the detection of soft X-rays and visible light, whichare totally absorbed within few microns from the surface.

A radiation entrance window was proposed [16], based on a continuous p+ implantwithout oxide gaps. The schematic view of a SDD for X-ray spectroscopy based on thisnew design is shown in Figure 2.9a. By using an equipotential electrode on the p-side,only the potential on the opposite side of the detector is varied to provide the driftingfield, as shown in Figure 2.9b. As can be easily understood from the figure, also for thisdevice, as in the case of the SDD shown previously, regardless their generation point,they are driven to the small collecting anode. An integrated voltage divider can be usedto bias the p+ rings by only contacting externally the first ring close to the anode andthe last one at the edge of the detector.

In order to reach a good response in the low energy range (few hundreds eV) a veryshallow implantation of the p+ back contact that acts as radiation entrance window isused.

2.2.2.1 Limits of silicon detectors in X-ray spectroscopy

In almost all the X-ray spectroscopy applications, the main task for the detector andthe readout electronics is to determine in the more accurate way the energy distributionof the incident photons. For this reason the energy resolution ∆E is a typical and fun-damental parameter of the system. In a real system, in fact, the energy distribution ofan incident photons flux with a fixed energy E0 is broadened with respect to the idealδ-like due to different sources of statistical fluctuation that affect the measurement.A typical value for the estimation of the resolution is the full-width-at-half-maximum(FWHM) of the Gaussian fitting of the energy distribution (FWHM=2.355*σ), higheris the FWHM more difficult is the identification of photons with energy very close eachother. The resolution can be also expressed as the ratio between the FWHM and themean energy:

R =FWHM

E0

(2.30)

The statistical sources that affect, in general, the measured energy resolution of thedetection system are:

∆E2measured = ∆E2

statistical + ∆E2noise + ∆E2

multiplication + .... (2.31)

The third term is related to the statical of the multiplication process and it should bediscard for SDD, while the first two terms are mainly responsible for the broadening

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(a) Structure.

(b) Potential.

Figure 2.9: a) Schematic diagram of the Silicon Drift Detector for X-ray spectroscopy with continuousimplant on the back side. b) Energy potential for electrons inside a SDD with homogeneous entrancewindow. A possible electrons path is shown.

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of the energy spectra. The first term is related to the conversion process of the photonenergy in charge carrier and it is a property of the material; for semiconductor detectorthe variance σ2 of the number of generated carriers is in accordance with a modified-Poisson distribution:

σ =√FN (2.32)

with σ is the standard deviation of the process, N is the number of charge carriersand F is the so called "Fano factor" from the name of the physicist, Ugo Fano, thatfirst proposed this theory in 1947 [17]. Theoretical calculation [18] and experimen-tal verification of the Fano factor can be found in literature, for Silicon the value isapproximately 0.115.

The expression for the energy resolution due to the statistical is therefore:

FWHMstatistical = 2.355√FN = 2.355

√FE0ε (2.33)

with E0 the energy of the photon and ε is the conversion factor eV per charge carriers.For silicon this conversion factor εSi is about 3.62 eV per e-h pair.

Therefore the limit energy resolution for silicon detector of the Mn-Kα energy line(a typical reference in X-ray spectroscopy) is:

FWHMMn−Kα = 2.355√

0.11 ∗ 3.62 ∗ 5898.8 ' 119eV. (2.34)

where 5898.8 is the value of the considered energy line. This is also called Fano limit.The second term of the equation 2.31 is the contribution to the energy resolution

given by the electronic noise of the complete system. The electronics noise of a de-tection system is expressed usually in terms of equivalent noise charge (ENC) that, Iremind, is defined as the charge delivered by the detector which makes the S/N ratioequal to one. Known the value of ENC for a given detector-electronics system, the∆Eel.noise is:

∆Eel.noise = 2.355ENCε

q(2.35)

In a typical spectroscopy system based on SDD, the ENC is in the order of few e- for atypical resolution, in terms of FWHM, below 130 eV for the Mn-Kα energy line.

2.2.3 Preamplification of signals from SDD

In order to take advantages from the low output capacitance typical of the SDD, the in-put capacitance of the preamplifier and the capacitance of the stray connections shouldbe kept as low as possible; working with low levels of electronics noise, of course, notonly the minimization of the total anode capacitance is a task but the noise minimiza-tion due to the first amplification (in terms of shot and 1/f) element is crucial. Overthe years different SDD readout topologies have been developed from external JFET tointegrated JFET and to CMOS preamplifiers.

2.2.3.1 Integrated JFET

The solution with integrated JFET is a goal for the minimization of the stray capaci-tances otherwise required for bonding the detector to the external amplifier. With the

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Figure 2.10: A view of a SDD with an integrated n-channel JFET.

integration of the first amplification element in the same wafer of the detector, the con-nection can be done with a very short metal strip (Fig 2.10). With an accurate designalso the matching capacitance condition CD=CG can be achieved reducing the electron-ics noise contribution. In the case of figure 2.10 the transistor is a n-channel JFET,designed to operate in a completely depleted high resistivity silicon, and placed in thecenter of the detector, inside the ring-shaped anode. The connection between JFET gateand anode is provided by the blue metal strip. The transistor region is separated fromthe detector region by an additional deep p implantation guard ring. In Fig. 2.11 thetop and the lateral schematic views of the n-JFET are shown.With the integration of the JFET the added capacitance is lower than 20 fF, one order ofmagnitude lower than the one added by an external JFET or CMOS preamplifier. How-ever the integration of the JFET has some drawbacks: it required a more complicatedtechnology process and the performance of the JFET itself are limited in terms of 1/fnoise and transconductance (typical gm value about 0.3 mS).

An evolution of the SDD with integrated n-JFET in the center of the detector is theso called droplet-SDD (or SD3) [19]. In this design the anode and the integrated n-JFET are placed in the margin of the detector allowing a reduction of the anode size,with a reduction in total anode capacitance down to 120 fF with respect to 200 fF of thecircular type. This improvements results in the energy resolution, thanks to the anodecapacitance reduction, but also it resolved the problem due to the charge created underthe JFET region (low peak-to-background values), because the lateral side in no morean active area and it can be shielded from incident radiation. Fig. 2.12 shows a sketchof the droplet-SDD concept.

This new approach has also a drawback because the longer drift path results in anhigher X ballistic deficit and this results in a worsening of the energy resolution at veryshort shaping time.

The JFET usually works in a source follower configuration with an externalcurrent generator connected to the source. The discharge of the detector leakage cur-rent and the reset of the signal charge accumulated on the anode are important issues

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(a) Top view. (b) Lateral view.

Figure 2.11: a) Schematic top view of the integrated JFET b) lateral view of the central region of theSDD.

Figure 2.12: Concept idea of the SD3, the drift field is created in order to force the electrons to drifttoward the readout anode in the lateral side.

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described in several works, for instance [20].The readout of SDD with an integrated n-JFET is typically based on a pulsed reset

scheme [21] [22], a technique in which the charge at the anode is not removed in acontinuous way but only in selected time phases; this technique has become in the yearsa standard in SDD readout because, with respect to a continuous reset configuration, itsolves the problem of the noise worsening with a high input count rate (> 10000 cps)due to the noise associated to the increasing reset current (that is equal to zero in pulsedreset mode). In Fig. 2.13 a source follower readout scheme for integrated JFET readoutis presented.

Figure 2.13: Pulsed reset scheme for SDD with integrated n-JFET used as voltage follower.

The readout is based on the well known charge preamplifier scheme, here the feed-back capacitor is not a real capacitance but a parasitic capacitance between the anodeand the internal deep p implant guard ring (IGR), Ca-igr in Fig 2.13 and 2.14.

Figure 2.14: complete lateral view of a SDD with integrated JFET, most of the parasitic capacitance areshown, in particular the junction capacitance between anode and guard ring Ca-igr used as feedbackelement.

The parasitic capacitance Ca-igr is in the order of 30 fF. The reset of the charge atthe anode of the detector takes place through a diode integrated in the SDD; usuallythis diode is reversed biased and no current passes through it, while applying a positivevoltage at the cathode for a short time the gate is discharged. The Rp -Cp networkis necessary for the biasing of the internal guard ring and it has no influence in the

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Figure 2.15: Voltage output with the integration of the leakage current and of the signal (above) and thereset signals (below).

operating bandwidth. The n-JFET needs a biasing current and it is AC coupled with theamplifier. With a correct and accurate design of the poles and zeros of the two loops,the complete circuit works as charge amplifier with Ca-igr as feedback capacitance. Inthis case the ideal current input-voltage output is:

Gideal =V out(s)

In(s)= − 1

sCa−igr(2.36)

As mentioned, in this scheme there is no a continuous removal of the charge so notonly the signal but also the leakage current of the detector is integrated in the feedbackcapacitance. Without signals, the slope of the ramp is only due to the leakage current.The voltage output appears as a ramp, due to the integration of the detector leakagecurrent, with steps overlapped due to the integration of the signals, Fig. 2.15. In firstapproximation, the amplitude of the step is proportional to the charge Q in the detector:

∆V =Q

Ca−igr(2.37)

The rise time of the signal depends on the bandwidth of the circuit, typical value is30-50 ns. The reset of the circuit can be periodic (i.e. fixed time betwwen two resetpulses) or when the output exceed a fixed threshold.

2.2.3.2 CMOS preamplifier

A valid alternative to a JFET based readout is the use of CMOS preamplifiers. Recently,at Politecnico di Milano, a CMOS preamplifier has been developed, called CUBE [23–25] specifically dedicated to SDD readout. The concept idea of the coupling of theCUBE circuit and the SDD is shown in Fig. 2.16

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Figure 2.16: Schematic view of CUBE connected to the SDD detector.

This readout is significantly less complicated with respect to the one used for theSDD with an integrated JFET, but it requires a well-engineered connection between thecircuit and the anode (in order to minimize the stray capacitance) and a careful design ofthe front-end transistor, similar considerations for the design of the first transistor can befound in [26]. This circuit works in pulsed reset mode but here the feedback capacitanceis no more a parasitic capacitance inside the detector but it is a real capacitor inside theCMOS circuit, with a value that can be arbitrarily chosen but typically it is equals to 25fF.

The results obtained with this SDD+CUBE approach are at the state of art in terms ofoptimum energy resolution (< 125 eV for the Mn-Kα line) and a great improvements atshort shaping time of the processing filter, with resulting superior performances at highinput count rates with respect to a solution based on JFET (noticeable differences inFig. 2.17, [24]). Another advantage given by a readout based on CMOS preamplifieris the relative standard process for the detector without the additional and dedicatedtechnology steps required for the JFET integration.

2.2.4 Silicon Drift Detector as scintillator light sensor

Photomultiplier tubes (PMTs) are still the most used devices use to measure light fromscintillators in γ-ray spectroscopy and γ-ray imaging. The main reason for their successare related to the good spectroscopy results that can be obtained with a simple readoutelectronics. Thanks to the internal multiplication phenomena that characterized thesedetectors, in fact, the contribution to the energy resolution given by the electronics noiseis negligible.

Energy resolution in γ-ray spectroscopy with scintillator

In γ-ray spectroscopy with scintillator coupled to radiation detectors, the energyresolution is usually defined as sum of four main contributions:

R =√R2int +R2

stat +R2coll +R2

ENC (2.38)

with:

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(a) Energy resolution.

(b) Energy spectra of a sample.

Figure 2.17: a) Energy resolution at the Mn − Kα line of the 55Fe source with a 25 mm2 SDD, b)comparison of energy spectrum of a sample with Zinc and Gallium acquired with SDD+JFET andSDD+CUBE with 0.3 µs peaking time and input count rate of 800 kcps.

- Rint is the intrinsic resolution of the scintillator, mainly due to the non propor-tional response and non uniformity of the crystal;

- Rcoll is the transfer resolution or collection efficiency, of the scintillator, this termin modern scintillation detectors is negligible compared to the other components;

- Rstat is the statistical resolution due to the statistical spread of the light generationin scintillators and of the photons to electrons conversion in the detector. Thisphenomena, unlike what seen for X-ray detection, is characterized by Poissondistribution;

- RENC is the contribution given by the electronic noise. For detectors with in-ternal multiplication, the contribution of the electronics noise is divided by themultiplication factor (for instance 106 for a PMT) making it negligible.

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In general, fixed the intrinsic resolution that is a property of the scintillator, a good de-tection system should be characterized by high quantum efficiency of the detector andlow electronics noise.In the last years the drawbacks of PMTs are becoming more and more evident: first ofall the low quantum efficiency, in the order of 30%, that causes a worsening in photo-electrons generation statistics Rstat a problem with the new generation of scintillatorscharacterized by low intrinsic resolutionRint, such as LaBr3:Ce or CeBr3 [27] (theRstat

is also worsened by the statistic of the multiplication). Moreover, the structure of thePMTs, tightly related to their working, is a limit in terms compactness and portability;another problem of PMTs is their high sensitivity to magnetic fields, an insurmountablelimitation to their use in the new generation of PET and SPECT instruments compatiblewith magnetic resonance (MRI).Possible alternatives to PMTs for scintillation readout are p-i-n photodiodes (PINs),avalanche photodiodes (APDs), silicon photomultiplier (Sipms) and Silicon Drift De-tectors [28].The following table summarizes the properties of different scintillation photodetectors:

PMT PIN APD Sipm SDD

Quantum efficiency ∼ 30% >85% >85% *PDE=40% >85%Multiplication 106 1 103 105 − 106 1Compatibility No Yes Yes Yes Yesto magnetic fieldsSolid state No Yes Yes Yes Yes

Table 2.2: Relevant properties of the most common photodetectors.

In Tab. 2.2 the quantum efficiency for Sipm refers to the Photo Detection Effiecency(PDE) a more significant parameter for this detector.

PIN diodesPINs have several potential advantages like high quantum efficiency in the visible spec-tra, biasing voltages are quite low and their are also compatible to magnetic fields. Themain disadvantage in the use of PINs is the same that limit their use in X-ray spec-troscopy: poor noise performance due to the higher detector capacitance.

Without multiplication, the electronic noise is no negligible (like in PMTs) and it de-grades the contribution of the total resolution determined by the electronicsRENC . Thenoise contribution due to the increase of detector capacitance is a series noise contri-bution and it can be mitigated with very long shaping times of the filter but this resultsin a lower maximum input count rate. The capacitance of the device is proportionalto its area, and, therefore, the requirement for a specification in the energy resolutiondetermines a limit to the area of the single detector.

Avalanche photodiodesAvalanche photodiodes combine the high quantum efficiency of PINs thanks to theirnature of solid state detectors with the benefit of avalanche multiplication, which re-duces the electronic noise contribution to the overall energy resolution. However, as in

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the case of PMTs, the statistical component Rstat of the overall energy resolution is af-fected by the statistics of the multiplication. Others limiting drawbacks are in the highsensitivity of the gain to temperature and bias variations and the difficulty to fabricatelarge arrays of uniform units.

Silicon PhotomultipliersSilicon Photomultiplier is an emerging detector topology particularly suitable for thereadout of scintillaors thanks to the advantages of the internal multiplication (in the or-der of 106), the easiness to assemble them in arrays to cover large areas, the photo detec-tion efficiency that allows to reduce the contribution to the total energy resolution givenby the Rstat (that is growing up year by year) and the compatibility to magnetic fields.The Sipm is an array of thousands cells each one composed by a passive-quenchedSingle Photon Avalanche Diodes (SPADs) read in parallel, when the scintillator lighthits the detector, a certain number of cells go in avalanche and the total output currentis proportional to the charge collected (and known the gain of the scintillator, to theenergy of the incident γ-ray). The main disadvantages of this detector are related to theperformance of this detector such as dark count rate, excess noise factor (ENF) or aboutthe working principle, such as sensitivity of the gain to the temperature. A descriptionof the use of this detector is not part of this thesis and can be found in many studies, forexample [29, 30].

Silicon Drift DetectorsSilicon drift Detectors, as widely described, thanks to their advantages in high quan-tum efficiency and low electronics noise are particularly suitable for scintillator read-out. Different works during the years showed the very good results that can be obtainedwith these detectors [31–34] For instance, 2.18 shows the results obtained with a cir-cular SDD with active area 30 mm2 with integrated JFET coupled to a cylindrical (5mm diameter x 5 mm thickness) LaBr3:Ce scintillator using a 137Cs source at roomtemperature.

Figure 2.18: 137Cs spectrum at room temperature, the same graph includes two energy scales in orderto appreciate the low energy peak at 32 keV and the main peak at 662 keV

Most of the works reported in literature use scintillators coupled to SDD with inte-

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grated JFET, in Chapter 4, measurements with SDD readout by CMOS preamplifier arereported with state-of-art performances.

Silicon Drift Detectors arraysA natural evolution of the use of single SDD detector is the use of arrays of SDDs inorder to cover bigger areas and bigger scintillators, especially for γ-ray imaging in med-ical applications (Anger Cameras). Assembling a matrix with a minimum dead area (inorder to maximize light collection) requires a re-design of the traditional round shapedSDD with different geometries, such as hexagonal, octagonal or squared. All the SDDbased anger cameras have been mainly designed at Politecnico di Milano [35–39].

The first small prototype realized was based on a monolithic array of 19 SDDs withon-chip JFETs 5 mm thick CsI(Tl) scintillator, the prototype has allowed for the firsttime γ-ray imaging using a SDD array. The camera had an intrinsic spatial resolutionof less than 200 µm, as shown in Figure 2.19 [35].

(a) Array. (b) Points reconstruction.

Figure 2.19: a) Layout of the monolithic array of 19 SDDs. b) Distribution of 11 points along a line, theintrinsic spatial resolution of less than 200 µm. Pictures are from [35].

Recently, other important projects were the DRAGO (DRift detector Array-basedGamma camera for Oncology) camera [36,37] (2.20), which is a high-resolution Angercamera based on a monolithic array of 77 SDDs (exagonal-shaped), with an active areaof 6.7 cm2, coupled to a 5 mm thick CsI(Tl) scintillator crystal, and the HI-CAM (Highresolution Gamma camera) camera [39] based on 100 SDDs (square-shaped) with a10x10 cm2 format, and 1 cm thickness CsI(Tl) scintillator (2.21). The HI-CAM cam-era has found applications in different fields from high energy gamma camera in nuclearphysics to prompt gamma imager in hadron therapy, a full description of the camera andof its application can be found in [39].

When a scintillator is read by arrays of SDDs, eq. 2.38 should explicitly considera very important and fundamental parameter like the ballistic deficit, that affect boththe statistical resolution (Rstat) both the electronic noise contribution (RENC). Thiseffect is mainly due to the size of the detector and, therefore, fixed the total area, it setslimitations in single pixel size and total number of channels.The ballistic deficit effect and others details about the trade-off in the design of a gammacamera based on SDDs will be reported in the Chapter 4.

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(a) DRAGO array. (b) Irradiation spots.

Figure 2.20: a) Layout of the DRAGO camera ,with a monolithic array of 77 SDDs, the active area is6.7 cm2. b) Irradiation spots of a 57Co source collimated, a spatial resolution from 0.25 to 0.5 mmwas measured. Figures from [36, 37].

(a) HI-CAM array with 100 square-shaped SDDs. (b) Thyroid phantom.

Figure 2.21: a) Detector array of the HI-CAM gamma camera, with 100 SDDs. b) Thyroid phantomacquired with the camera. Figures from [39, 40].

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CHAPTER3HTRS: High Time Resolution Spectrometer

Aim of this chapter is to describe the design choices, the innovative solutions imple-mented and the results obtained with a multichannel integrated circuit designed for highresolution and high throughput applications with Silicon Drift Detector. The circuit wasinitially designed to be used with SDD with integrated JFET but the best performancehave been carried out with a CMOS preamplifier taking advantages from the best per-formances at short shaping time of this readout.

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Chapter 3. HTRS: High Time Resolution Spectrometer

3.1 IXO-HTRS

This chapter is about an integrated circuit for high rate applications with SDDs and itsstudy and implementation have been motivated in 2010-2011 by a collaboration for thedevelopment of an instrument, HTRS (High Time Resolution Spectrometer), that givesthe name to this chapter, one of the focal-plane instruments of the International X-rayObservatory (IXO) (Fig. 3.1). IXO was a joined project funded by ESA, JAXA andNASA (result of the merger of the old projects, XEUS and Con-X), successor of XMM-Newton for X-ray observations, fundamental in astrophysics for the understanding ofthe structure and the evolution of stars and galaxies. For instance, X-ray sources areassociated with the different phases of stellar evolution such as neutron stars, supernovaremnants or black holes [41].

(a) IXO sketch. (b) In plane instruments.

Figure 3.1: Skecth of the IXO observatory (a) and view of the instruments. Figures from [42] [43].

The HTRS, in particular, was focused on the matter under extreme condition sci-ence, with the capability to observe bright X-ray sources such as accretion neutronstars and black holes X-ray binaries. A schematic example of possible application isreported in Fig. 3.2.

The IXO observatory was discontinued in mid 2011 and some IXO instruments,have been proposed for the ESA ATHENA project (Advanced Telescope for High EN-ergy Astrophysics), unfortunately HTRS is not one of these and, therefore, the proposedASIC will not be used for what it was designed. Anyhow, HTRS main features havedetermined the characteristics of the ASIC and, for this reason, they are reported asguidelines in the next paragraph.

3.1.1 Requirements for the HTRS instrument

HTRS was focused on spectroscopy and not on imaging and the incident flux is spreadover an array of silicon drift detector in order to maximize the total input count rate. Afirst prototype studied for this a application is reported (dummy structure) in Fig. 3.3with both top and bottom view. The detector is composed by 31 SDDs with integratedJFET for a total active area of 4.5 cm2 with a total area circumscribable in a 24 mmdiameter round shape. All the detectors have the same area of 14.6 mm2, the central

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3.1. IXO-HTRS

Figure 3.2: Example of application: study of stars or black holes (in this case) from the X-rays reflectedby accreation disks. Figure from [43].

has a round shape while the others have different shapes suitable for an accommodationin three concentric rings (the inner one with six cells, the two outer with twelve cellseach).

(a) Radiation entrance window side. (b) Readout side.

Figure 3.3: Mechanical dummy sample of the HTRS sensor, (a) detector back-side with entrance win-dow,(b) top-side with contacts of the single elements.

The cells are separated by a baffle in order to inhibit split-events, charge collectedin two or more different cells result of photons absorbed in the cell borders. A partialcollection in a single cell results in a wrong energy information in the spectra andshould be avoid. The baffle reduces the total sensitive area, but the single cell receivesthe full signal of an event. Requirements are reported in Tab. 3.1.

The "Crab" (indicated in 3.1) is a standard unit for measurement of the intensity ofastrophysical X-ray sources and it is defined as the intensity of the Crab Nebula [44].The maximum input count rate can be translated in a more conventional 2 Mcps countrate. Efficiency refers to the events lost by the system due to dead time or pile-up (seenext section). These requirements can be translated in dead time and pile-up lower than1% at 10 kcps and lower than 10% at 100 kcps.

A relatively high number of channels requires the use of an integrated circuit for

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Energy range. 0.3-30 keVEnergy resolution (-40 °C) FWHM @ 5.9 keV < 150 eVMaximum count rate 10 Crab (1 Crab ' 160.000 counts/secEfficiency at 10 kcps > 99%Efficiency at 100 kcps > 90%

Table 3.1: Sensor requirements.

signal acquisition. For thirtyone detectors a possible solution is the use of four ASICseach one with eight readout channels. An example of a general readout is shown in Fig.3.4.

(a) Overview of the sensor readout.In red ASIC locations.

(b) Blocks diagram.

Figure 3.4: Sensor readout (a) and blocks diagram with emphasis on the digital processing unit (b).

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3.1. IXO-HTRS

The readout can be based on two different architectures: analog processing and dig-ital processing. The first case is based on conventional analog processing (preamplifier,shaping filter and peak detector) with an analog to digital conversion at the output ofthe processing chain, for instance on ADC at the output of an analog MUX in order toshare resources. The second option is the analog to digital conversion of the signal atthe output of the preamplifier and a digital filter for processing. The designed ASICis based on the first approach but it provides also preamplifiers outputs for the digitalacquisition.

Before describing in details the ASIC, the next two paragraphs introduce the prob-lem of pile-up and the choice of the shaping filter in order to minimize it.

3.1.2 Pile-up issue

When two (or more) photons are detected very close one to the other in time, the out-put of the charge amplifier has two steps (with a proper amplitude proportional to theenergy) with the same temporal distance. As a consequence, the output of the shaperhas an output given by the combination of the two responses of the single events. Ifthe width of the output of the filter to the single event is not narrow enough, the over-all output is the superposition of the two responses. In spectroscopy applications, thisresults in a misinterpretation of the signal amplitude and a consequent in the spectrum.This phenomena is usually called pile-up, and, due to the random distribution in timeof the input signals, is always present, but it becomes more and more important withthe increase of the input count rate.Alternatively the pile-up occurs when an events is detected within a fixed time withrespect to the previous event. This time depends on the acceptable error and on thecharacteristics of the shaper output. The corruption of the peaks amplitude occurs whenthe falling tail of first response is summed to the second, or, in another way, if the am-plitude of the tail of the first peak in correspondence of the second peak is too big. Ifthis amplitude is not big the effect on the amplitude of the second peak can be negligi-ble because, for instance, the statistical noise is dominant. If the maximum acceptableerror is 1%, the second peak should occur not before the falling tail of the first responseis lower than 1% of its peak value (same amplitude of the pulses).Fig. 3.5 shows three different cases of two signals with the same amplitude. Themarked lines are the overall responses while the thinner ones are the hypothetical re-sponses of the single events. In the first case, first green and thinner red are the re-sponses to the single events while marked red is the "real" output of the filter, only onepeak with wrong amplitude is detected.In the second case, first green and thinner blue are the single responses, the output is thegreen line until the second response occurs, than it continues with the marked blue. Inthis case the first peak has the right amplitude while the second is wrong. An efficientsystem can try to acquire the first peak and discard the second one.Third case, the two events have sufficient distance in time and the output has two peakswith the right amplitude (green marked line).

Two events detected at the same time produce a peak in the spectrum at an energythat is the sum of the two events. This peak is called "ghost peak" and it is not dis-tinguishable with respect to an individual event with that energy. The probability of"ghost peaks" in the spectra increases with high count rates.

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Figure 3.5: Output of the shaping filter in three cases: with (marked red and blue) or without (markedgreen) pile-up.

A possible solution in order to minimize pile-up is to reduce the peaking time of the fil-ter but, as seen in Chapter 2, if the peaking time is too short the serial noise contributionis dominant with a worsening of the energy resolution. A very fast (short peaking time)auxiliary shaping filter in parallel can be used to detect and discard events that occursin a fixed time window. An efficient logic based on this approach has been designedand it will be presented in the paragraph 3.2.4.

3.1.3 Choice of the shaping filter

The choice of the shaping filter and of the peaking time are crucial to reduce the effectof the pile-up. For an easier understanding in the time domain the τ used for the nor-malization of the filter is the peaking time. Fig. 3.6 shows the characteristic times ofthe impulse response that can be used for a design oriented to pile-up minimization.

TP: peaking time, the time between the arrival of the photon and the peak of theimpulse response.

TSH: shaping time, here defined as the time that elapses between the two time in-stants in which the response is equal to half the amplitude of the peak.

Ti: impulse time, defined as the time in which the output is higher than 1% of thepeak value.

Tf: full time, is the time between the start and the end of the output.

In this design we assume the collection time of the electrons at the anode almostconstant, and the output of the preamplifier like an ideal step, i.e. we do not considerin a first approximation the ballistic deficit effect. This is a good approximation in our

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Figure 3.6: Characteristic times of the impulse response of a generic filter.

Figure 3.7: Output response of three events without pile-up.

application with small SDDs (used in X-ray direct conversion) and with preamplifierswith rise time lower than 50 ns, it would not be the same with detector with bigger areaor in applications with scintillators where the collection time is longer. An elevatedballistic deficit, in fact, produces an increase of the peak time of the output shape anda decrease of the amplitude of the peak (the signal filter response is convolved with aslower signal). Thanks to the approximation as ideal step of the output of the pream-plifier, and assuming the shaper a linear time-invariant filter, the characteristic times ofthe filter are independent from the amplitude of the input signal. Known the output ofthe impulse response, is possible to calculate the minimum time interval between twoevents that does not produce pile-up.

According to Fig. 3.7 it is possible to find a condition in which the second event thatoccurs in T2 is not affected by the falling tail of the first one. The peak of the secondevent must occur after the end of the first tail:

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TP + T2 > TF + T1 (3.1)

and thus:T2 − T1 > TP − TF (3.2)

The tail of the response must be smaller than the distance between the two consec-utive pulses. It must also be considered that the rise of a third event should start afterthe second peak:

TP + T2 6 T3 + TF − Ti (3.3)

thus:T2 − T1 > TP + Ti − TF (3.4)

so the rise must be smaller than the distance between two events. In general for thefilters described in Chapter 2 (CR-RCn, semi-Gaussian, ecc..) the rising tail is alwayssmaller than the falling one and therefore the eq. 3.2 is the more stringent one. Toavoid pile-up only one event can occur in TP-TF, a relevant interval called Tfall. For thepile-up estimation is now important to calculate the probability that an individual eventoccurs in a fixed time interval. Using a Poisson distribution to approximate the statisticof photons on the detector [45], it is possible to find a time interval T in which no morethan one event occurs.

T = − 1

finln

(foutfin

)(3.5)

with fin the average input count rate expected and fout/fin is the ratio between the eventsnot affected by pile-up and the total events.

With 3.2 and 3.3 it is possible to define a constraint for the fall time of the filter:

Tfall 61

finln

(finfout

)(3.6)

In order to reduce the TF of the impulse response a filter with complex poles is the bestchoice compared to one with real poles. Fig. 3.8 shows the advantages of a filter withcomplex poles (semi-Gaussian) with respect to one with real poles (CR-RCn) normal-ized with the same peaking time. The TF is reduced increasing the order of the filter.

An alternative to Semi-Gaussian is the parallel poles approximation, that has verygood performance in terms of noise and narrowness of the output response, similar oreven better than the semi-Gaussian but, for the same peaking time, it requires poles athigher frequencies, with problems in the real implementation due to the finite GBWP(Gain-Bandwidth Product) of the operational amplifiers used in the design.The output response of a semi-Gaussian filter is obtained as the approximation in timeof the Gaussian shape, i.e. a polynomial function with n order is used to approximatethe Gaussian. The mathematical method is reported in [46] with the calculation of thepoles location of the filter up to the seventh order. We used the same method to obtainthe ninth order approximation and we compared it with the seventh order for the finalchoice of the filter (Fig. 3.9 and Tab. 3.2).

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Figure 3.8: Comparison of CR-RCn and semi-Gaussian with same peaking time and different orders.With the same order, the semi-Gaussian is always the narrowest.

(a) Poles location.

(b) Impulse response.

Figure 3.9: Poles location (a) and impulse responses (b) of semi-Gaussian filters with seven and ninepoles approximation.

Tab. 3.2 reports the pole location in terms of real imaginary parts. The poles arenormalized with unitary peaking time in for an easier calculation of the poles locationcorresponding to a desired peaking time. The output response of the two filters has been

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n=7 n=9<0 −4.9218 −6.3325<1 −4.8090 −6.2365=1 ±1.4838 ±1.5304<2 −4.4298 −5.9332=2 ±3.0978 ±3.1324<3 −3.6577 −5.3632=3 ±5.0708 ±4.9173<4 −4.3504=4 ±7.1675

Table 3.2: Real and imaginary part of the poles of the semi-Gaussian filter (seventh and ninth order).The pole position is normalized with an unitary peaking time.

simulated with a numerical analysis ( MATLAB based) and the characteristics time andnoise factors of the filters have been obtained. Tab. 3.3 summarizes the most relevantresults.

Order A1 A2 A3 Tfine Timpulso TpiccoVII 2.7148 1.0338 0.6133 2.185 1.949 1IX 3.16 1.0237 0.5235 1.998 1.693 1

Table 3.3: Characteristic times and shaping factors of the two filters.

The filter chosen is the ninth order semi-Gaussian for the narrower impulse responsethat gives a lower pile-up probability.

With 3.3 and 3.6 it possible to determine the maximum peaking time:

Tpeaking =Tfall0.998

61

finln

(finfout

)6 1µs (3.7)

using the specification (3.1) of 1% loss at 10 kcps input count rate.

For noise estimation we can assume these parameters for circular SDD with inte-grated JFET:

CTOT (SDD + JFET total capacitance) 180 fFgm (JFET) 0.3 mSAf (JFET 1/f coefficient) 5*10-12 V2

ITL 1 pA at -40 °C

Table 3.4: SDD parameter for noise evaluation.

The ENC vs. peaking time and the % of lost events are reported in Fig. 3.10, theyellow area satisfies the efficiency requirement while the blue one the energy resolution(FWHM < 150 eV at 5.9 keV). Four peaking times have been implemented: 600 ns forhigh rate application (a good margin with respect to the 1 µs constraint), 3.94 µs theoptimum peaking time for noise at -40 °C, 1.5 µs (geometric mean between the firsttwo) and 2.2 µs.

The poles position has been defined as function of the peaking time, therefore the

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Figure 3.10: Graphical comparison of the requirements in terms of energy resolution and efficiency. Thefour reported times are the peaking times chosen for the design.

calculation of the value of the poles is very easy, the values in 3.2 must be divided bythe peaking time value:

<0(Tpeaking) =<0

Tpeaking(3.8)

<1(Tpeaking) =<1

Tpeaking

=1(Tpeaking) ==1

Tpeaking

(3.9)

. . .

With the usual definitions complex conjugate poles can be written in terms of naturalfrequency ω0, and damping ratio ξ (or quality factor Q):

s2 + 2ξω0s+ ω20 (3.10)

s2 +ω0

Qs+ ω2

0 (3.11)

and the parameters can be derived from the poles location:

ω0 =√<2x + =2

x (3.12)

ξ = −<xω0

(3.13)

Q = − ω0

2<x45

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Poles [MHz] ω0 [Mrad/s] Q<0 −10.5542 10.554 0.5<1 −10.3941 10.702 0.5148=1 ±2.5507<2 −9.8887 11.182 0.5654=2 ±5.2207<3 −8.9387 12.127 0.6784=3 ±8.1955<4 −7.2507 13.974 0.9636=4 ±11.9458

Table 3.5: Poles location, ω0 and Q factor for the 600 ns peaking time.

The poles for 600 ns peaking time are listed in Tab. 3.5. Similar tables can be easilyderived for the other three peaking times.

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3.2. The HTRS chip

3.2 The HTRS chip

In this section the electronics solutions adopted in the design are presented. In a firstphase the design has been focused on a single readout channel composed by chargepreamplifier, 9th order shaping amplifier (SA) and baseline holder (BLH) in order tomatch the requirements in terms of noise and desired peaking time of the filter. In asecond phase the peak detector (PKS) and its controlling logic have been developed tomeasure the amplitude of signals not affected by pile-up and discard the corrupted ones.In the final phase the complete architecture with eight channels has been completedwith an analog multiplexer, an output buffer and other common peripheral circuits (forbiasing, outputs test, ecc..).

In Fig. 3.11 a generic blocks diagram of the ASIC is reported.

In the single channel a parallel fast shaper FSA has been used for the detection ofevents with pile-up. The digital section is arranged in two hierarchical levels of fullcustom logic. The lower level, implemented as one block per channel, consists of twosub-blocks: channel logic and peak logic. The channel logic implements tasks directlyrelated to the single channel. It detects when the output of the preamplifier has exceeda selectable threshold or not in order to provide the reset pulse out-of-chip, it providesthe inhibit signals for the shapers and for the BLHs during the reset phase and allowsto modify the shaping time (of the shaper amplifier SA) and the gain (of both the SAand FSA). The peak logic handles the three phases of the peak stretcher and the pile uprejection operation. The top level, called "global logic" in Fig. 3.11, is in common to allthe channels. The main role of the global logic is to provide a communication interfacewith the external DAQ and to handle the multiplexer operation, that works in pollingmode: during an acquisition, all the channels are read one after another, regardless ofthe fact that there is a valid signal on it.

All the implemented features (gain, shaping time, functionality options, etc...) areprogrammed inside the ASIC with internal registers. To program all these registers,a 160 bits shift register with a custom SPI (Serial Peripheral Interface) is included.A ROM with a standard configuration is also included, and its configuration can beselected to use the circuit without the SPI connection.

The output of one of the 8 preamplifiers, one of the fast shaper amplifiers, and one ofthe outputs of the shaper amplifiers can be buffered outside the chip for testing purposevia three internal buffers. The implemented architecture is modular, so it can be easilyupgraded to a higher number of channels if needed in future prototypes. The chip isdesigned to reduce the number of external components. All the voltage and currentreferences have been integrated inside the ASIC with 5 bits or 6 bits trimming DACs inorder to generate all the required biases (the values are set by the internal register). Theonly off-chip required components are decoupling capacitors for two power suppliesand five internal voltages.

The design has been done with CADENCE Virtuoso Environment for schematic,simulation ( with SPECTRE and UltraSim) and layout.

The technology used is 0.35 µm by AustriaMicroSystems and the power supply is±1.7 V. The ±1.7 V biasing was used historically in the ASICs by the research groupin order to use the ground as reference for the baseline and for the output. Following

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paragraphs are dedicated to the main building blocks.

3.2.1 Design: Preamplifier

The preamplifier designed is a circuit that combined with the SDD with integrated JFETallows to set-up a charge preamplifier, as seen in Chapter 2 when the JFET is used asvoltage follower (Fig. 2.13). The lateral view of the detector with JFET integrated hasalready been shown in Fig. 2.14 and it is reported here in Fig. 3.12 for convenience,with a brief description of the contacts.

Ring 1 (R1) and Ring N (RN): the rings from 1 to N are responsible for the creationof the drift electrical field. Ring 1 is the first ring and it is close to the anode, it is biasedwith a small negative voltage (-20 V). Ring N is the last ring, placed in the outer part ofthe detector and it is biased with a high negative voltage (-160 V). All the other ringsare automatically biased to intermediate voltages through an integrated voltage divider(not shown). The rings are implanted as p+ well;

Back: is the entrance window for the radiation, made with a homogeneous p+ well,it is biased with a high negative voltage level and it is responsible for the depletion;

Backguard: is a ring around the Back contact, it provides insulation of the activeregion of the SDD;

Inner substrate (IS) and outer substrate (OS): are bulk contacts, n+ implants, bothconnected to ground. OS is the external contact of the non-depleted n-region, IS is thebulk contact located near the center of the sensor;

Inner guard ring (IG): it isolates (electrically) the integrated JFET from the rest ofthe device;

JFET source (FS) and drain (FD): are the source and the drain of the integratedFET;

Reset diode (RD): it is an integrated device used to reset periodically the detectors,removing the collected charges due to signal and leakage current.

In Fig. 3.13 the readout scheme is reported with real values of some components,Cf is the Ca-igr while Cp1 and Cp2 are the parasitic capacitance at the source of theJFET and the output that must not be neglected in the design because their value isin the order of 20-30 pF (dominated by the connections from SDD to ASIC througha board). In this design, unlike previous approaches [47], we want to integrate all thecomponents in the yellow box, in order to reduce as much as possible the number ofthe discrete components on the board.

The guard ring biasing network can be considered a short circuit for the all thefrequencies. The input-output "ideal" transfer function of the charge preamplifier:

Gid(s) =V out(s)

V in(s)=

1

sCa−igr=

1

sCf(3.14)

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Figure 3.11: HTRS chip.

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Figure 3.12: Lateral view of SDD with integrated JFET. The junction capacitance between anode andguard ring is highlighted.

Figure 3.13: Pulsed reset scheme for SDD readout.

is well approximated if the inner loop composed by Cac, Rf and A(s) is stable and welldesigned. We can calculate the loop gain of the circuit and than the real input-outputtransfer function. The gain loop can be easily calculated in first approximation withoutthe parasitic capacitances and considering the gain A(s) an ideal block.

GLOOP = βsCacRf

1 + sCac

gmFET

(3.15)

where β is defined as the capacitive partition:

β =Cf

Cin + Cf(3.16)

The "real" gain is:

GREAL =Gid

1− 1

GLOOP

= βRfCacCf

1

1 + sCac

(βRf +

CacgmFET

) (3.17)

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Figure 3.14: Proposed solution for the preamplifier.

From this expression it is possible to extract the frequency after which the circuit worksan integrator:

ft =1

2π

(CacβRf +

CacgmFET

) (3.18)

We want that the circuit works as integrator for almost all the frequencies, i.e. the polemust be at very low frequency (few Hz). With discrete components, capacitor in theorder of hundreds nF and Rf in the MΩ range are not a problem but in an integratedcircuit these values are impossible. In our design a smart network is used to synthesizea high value Rf resistor while the Cac capacitor is a 20 pF standard component availablein the CMOS technology (poly-insulator-poly).

The designed inner loop of Fig. 3.13 is shown in Fig. 3.14.The amplifier A(s) is a standard configuration 2-stage differential amplifier with

Miller compensation [48] while the network composed by the two resistors R and 49Rand the PMOS in feedback is the equivalent resistor (red dashed box). The PMOS (usedinstead of an NMOS to reduce 1/f noise) is in deep weak inversion and it is designedin order to have a constant value of channel resistor with a small variation of its source.The node A, in fact, is a ramp with an amplitude given by the amplitude of the output(2 - 2.5 V) divided by the resistive partition. The simulated channel resistor is about780 MΩ. The input-output resistor can be easily calculated as:

Rf = Rch

(1 +

49R

R

)+ 49R ' 50 ∗Rch ' 39GΩ (3.19)

where Rch is the channel resistor and R and R2 are considered « Rch.The resulting pole (Cac=20 pF) is at '1.2 Hz.The Cc capacitor is used for the compensation of the inner loop, with a sort of

reversed nested Miller compensation. The Cac capacitor is also used to AC couple theASIC and the detector; the capacitor used has a maximum ∆V across its terminals of

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Figure 3.15: Reset logic circuits (simplified with functional blocks).

5.5 V, not a limitation for this application. The current generator for JFET bias is notshown in Fig. 3.14 and, for noise considerations, is composed by a simple resistor withone terminal connected to a negative voltage on the board (according to the desiredcurrent, in the range of -8/-10 V). In the real design with the simulator, of course, alsothe finite GBWP of the amplifier and the parasitic capacitances are considered.

3.2.1.1 Reset of the preamplifiers

The preamplifier works in pulsed reset mode, so when the output of one amplifier ex-ceed a fixed threshold all the eight preamplifiers are reset. In the single channel theoutput of the preamplifier is compared to a fixed threshold made with a 6-bits (se-lectable in the internal registers) DAC and a logic in common to all the channels (Fig.3.15).

Two other solutions are present for the reset of the preamplifiers, the first (bluebox) is a sort of analog watchdog timer, a reset is given if in a fixed time window(programmable, typical value 30 ms) there are no reset. The second solution is the useof external signal that can be connected, for instance, to a programmable logic. Whena reset occurs, the shaper, that is AC coupled to the preamplifier, receives a currentwith a reverse polarity and therefore there is saturation to the lowest possible value atits output. To avoid this problem some inhibit signals (with selectable duration) areprovided to the shaper. Fig. 3.16 shows the control signals.

When one channel exceed the threshold the reset signal is not given immediatelybut after a fixed time. This is necessary because we want to process also the last signalbefore the reset, if this is not done, the reset can occur on the rise of the preamplifieroutput with a high energy event. The duration of this delay in the reset is selectableand should be at least two times the peaking time of the filter. The circuit allows alsoto avoid a typical problem of this SDD configuration [49] [50], after the reset, theoutput of the preamplifier can have an overshoot with a new exceed of the threshold, a

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Figure 3.16: Timing diagram of control signals.

subsequent new reset and so on (uncontrollable series of resets). The monostables hasbeen designed in order to give an output pulse with a selectable duration. The durationof the reset is 500 ns and the inhibit signals in the order of few µs so the dead timeintroduced is negligible.

The RESET signal is then adapted on the board to the values required for the resetof the SDD (-7 V low value and +14 V high value).

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3.2.2 Design: Shaper Amplifier

During the design of the filter different architectures have been considered and alsodeveloped (in part) with the simulator:

- ladder network with impedance converter;

- current feedback architectures;

- gm-C filters;

- cascade of cells with passive components.

The first approach is probably the most elegant in terms of area occupancy andoverall low sensitivity to parameter mismatch but with our technology (0.35 µm), wenoticed it is very difficult to design the poles for the shortest peaking time (high fre-quency) required for the application (limitation due to the finite GBWP of the ampli-fier). The choice made has been the last one that allows, with a simple design, verygood performance with only the disadvantage of a high area occupancy that, anyway,is not dramatic with a smart choice of the components.

The output of the filter is connected to a circuit for the detection of the peak ampli-tude that is easier to be implemented in single ended. For this reason also the filter issingle ended.

AC coupling and first real pole.The first stage of the filter needs to provide the AC coupling to remove the ramp dueto the leakage current integration and we implement also the first real pole of the ninthorders constellation (Fig. 3.17).

Figure 3.17: First stage with AC coupling and first (real) pole.

The input-output transfer function is:

G(s) = − sR1CA1 + sC1R1

(3.20)

The ratio CA/C1 can be modified to adapt the gain of the filter. In the ASIC, with properswitches, it is possible to set the four times constant (changing C1 and R1) required for

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Figure 3.18: Low pass MFB, also called Rauch cell or infinite gain cell.

Figure 3.19: Low pass Sallen Key non inverting cell.

the four peaking times and the gain (changing CA).

Biquad cells: Multiple feedback and Sallen-KeyThe complex conjugate poles (Tab. 3.5) have been implemented with cascade of stan-dard cells, in particular low pass multiple feedback (MFB, Fig. 3.18) and Sallen-Key(S-K, Fig. 3.19 ). The MFB cell with respect to the Sallen-Key one has a lower sen-sitivity to mismatch parameter and not ideal performance of the operational amplifier,but, they are designed only with an inverting configuration. We have four complexconjugate poles in cascade to the inverting stage (Fig. 3.17) and the overall gain of thefilter must be positive. Therefore it is not possible to use a cascade of four MFB cells.The adopted solution is to use three MFB and one non-inverting S-K.

Every stage has a transfer low pass tranfer function:

G(s) =Kω2

0

s2 + 2sξω0 + ω20

(3.21)

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For MFB cell G(s) as function of the components:

G(s) = −

1

R1R2C1C2

s2 +s

C2

( 1

R1

+1

R2

+1

R3

)+

1

R1R2C1C2

(3.22)

With 3.21 and 3.22 it is possible to calculate ξ, ω0 and K as functions of the components:

ω0 =1√

R1R2C1C2

ξ =1

2

√C1

C2

(√R1

R2

+

√R2

R1

+

√R2R1

R3

)K = −R2

R3

(3.23)

For the non inverting Sallen-Key:

G(s) =A

1

R3R4C1C2

s2 + s

(1

R1C2

+1

R3C2

+1− AR3C1

)+

1

R3R4C1C2

(3.24)

and the equations for the design:

ω0 =1√

R3R4C1C2

ξ =1

2

(√C1R3

C2R4

+

√C1R4

C2R3

+ (1− A)

√C2R4

C1R3

)K = A = 1 +

R2

R1

(3.25)

After the calculation of the poles position for the four peaking times, it is very easy thecalculation of the values of the components (not reported here). The required compo-nents can be combined in series or in parallel with switches in order to reduce as muchas possible the area occupancy. The GBWP of the operational amplifier is crucial forthe position of the poles in every biquad cell, in particular for the shortest peaking time.Several simulations has been done, also with the SPECTRE p/z analysis, and the con-clusion is a required GBWP > 250 MHz, a value hard to obtain in 0.35 µm with usualtwo stages topologies.

The designed amplifier is mainly composed by a single differential stage followedby a simple output buffer (without compensation capacitor). To fully exploit the wholedynamic in the chain two amplifiers (optimized for negative or positive signals at theiroutputs) are alternated in consecutive cells, more details in [50]. The post-layout sim-ulations (with parasitic extraction) of the step response of three peaking times of thefilter is reported in Fig. 3.20.

A complete structure of the shaping filter is reported in Fig. 3.21 with the simulationof the output of every stage (absolute values).

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(a) Responses of the filter with three peaking times configuration: 600 ns (yellow), 1.5 µs(orange), 3.94 µs (red).

(b) Same three peaking times with four gain setting each.

Figure 3.20: Response of the filter with three peaking times and different gain settings (post-layoutsimulations).

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Figure 3.21: Shaper filter sketch with simulated outputs of the intermediate stages (absolute values).

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3.2.2.1 Design: Fast Shaper Amplifier.

As already mentioned and better explained in the paragraph 3.2.4 the pile-up rejectorlogic requires informations about the arrival of events when the main channel is pro-cessing an event (i.e. during Tfall of the main filter). This can be done with a parallelchannel with very short peaking time (fast channel). Ideally we desire a fast channelwith a very short peaking time but this is in contrast with the specification of the mini-mum energy detectable. In our design we assume acceptable a noise of the fast channellower than 25 e- ENC. Our pile-up rejector is based on time windows and, for this rea-son (that will be more clear in the following paragraphs) we want in the fast channelthe same shape. For this reason, also the fast channel is a ninth order shaping amplifier.The architecture is the same of the main channel but here the peaking time is fixed, andfor noise consideration is set to 200 ns. Fig. 3.22 shows a post layout simulation of thefast channel and of the main channel (with 600ns configuration).

Figure 3.22: Fast shaper (orange) and main shaper (yellow) in the 600 ns configuration peaking time.

3.2.3 Design: Base Line Holder

The baseline holder (BLH) is the circuit that has the role to stabilize to a fixed valuethe baseline at the output of the shaper. This circuit is absolutely fundamental in orderto compensate the shift of the baseline due to process or mismatch errors, thermal driftand, very important, the shift at high count rates.

The designed BLH is based on [51] with few modifications.The BLH is connected in feedback to the shaper (Fig. 3.23), it senses the output

value and it corrects the DC current in the shaper to fix the baseline value. In our casethe current If is injected in the virtual ground of the first cell of the shaper. The BLH isdesigned to work at low frequency to preserve the shaper transfer function.

In the single analog channel two BLHs are present, the first one for the main filter,

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Figure 3.23: Baseline holder general view.

the second one for the fast shaper. The differences will be specified in the following.Conceptual, not real ones, transfer functions of the shaper alone, of the BLH (a lowpass filter) and of the shaper and BLH combination is shown in Fig. 3.24.At high frequency, the transfer function Vout/If (b plot in Fig. 3.24 ) is zero and it not

Figure 3.24: Tranfer functions: a) shaper only, b) BLH, c) shaper and BLH considering as input thecurrent in the virtual ground (after the couplig capacitor). Figure from [51].

alters the shaper transfer function. The c) plot reports the transfer function from theinput current (in the virtual ground after the coupling capacitor) to the voltage output.The voltage input is AC coupled (the coupling capacitor is required to cut the ramp dueto the leakage integration) with the known drawback of the shift of the baseline (δbl)function of the rate. The AC coupling imposes an average value of the output equal tozero, Fig. 3.25.The Gloop(0) should be high to reduce the "static" error of the baseline up to few mV,but not too high because, with fOL the frequency of the pole of the low pass filter infeedback, the frequency of the closed loop pole is fCL=Gloop(0)*fOL and if it is tooclose to the poles of the shaper, the phase margin of the loop can be not sufficient forthe stability.

We can start the analysis of the BLH with the simpler implementation, an amplifier(gain GD) followed by a low pass filter, in feedback (equivalent model in Fig. 3.26).For an easier calculation is considered a triangle as shaper signal Vs (Fig. 3.27).

The analysis of the circuit can be done in two separate phases, for 0<t<2TP thecharge QC is integrated on the C capacitance (Fig. 3.28), for 2TP<t<TR (with TR=

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Figure 3.25: Shift of the baseline due to the AC coupling.

Figure 3.26: Equivalent model of a simple implementation of the BLH, amplifier followed by low pass-filter.

1/rate). the charge QSC "come back" to the circuit (Fig. 3.29) The time constant of thefilter τis very long (seconds) to ensure loop stability, and therefore is greater than TR.With this approximation it can be assumed ideal the integrator and linear the dischargemechanism. The charge CC integrated is:

QC =

∫ 2TP

0

VLPR

dt =1

RVPGDTP (3.26)

while the charge QSC (with TR»TP):

QSC =

∫ TR

0

|VLP |R

dt =1

RδVBLGDTR (3.27)

The QC=QSC condition give a baseline shift of:1

RVPGDTP =

1

RδVBLGDTR ⇒

δVBL =VPTPTR

= VPTP rate(3.28)

Assuming real values: VP=1 V, VP = 4 µs, rate 100 kcps, the shift is about 400 mV, avery high value that would compromise the functioning of the circuit.An improvement of the simple RC low pass filter is to have a saturation of the output ofthe amplifier, Fig. 3.30 instead of Fig. 3.28. In this case, with the same approximations,the charge QC is:

QC =

∫ TR

0

|V DD|R

dt =1

RVDD2TP (3.29)

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Figure 3.27: Simplified shaper signal for calculation.

Figure 3.28: Voltage response at the output of the amplifier (a) and on C (b) for the figure 3.26 withtriangular input signal.

Figure 3.29: Voltage signals including the period between two signals a) C discharge, b) linear dis-charge for τ »TR, c) average baseline value during T.

while QSC is the same calculated above in eq. 3.27. The voltage shift is:1

RδVBLGDTR =

1

RVDD2TP ⇒

δVBL =V DD2TPGD

rate = VPTP rate2V DD

VPGD= VPTP rateK

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Figure 3.30: Output of the amplifier with modification of saturation to VDD.

with the improvement factor K (2

GD) with respect to eq. 3.28. For the same parameter

and GD=10. The resulting shift is about 135 mV.A further and conclusive improvement, is the use of a non linear buffer after the ampli-fier, the resulting complete blocks diagram is reported in 3.31.Using a non linear element after the amplifier limits that limits the charge integrated

Figure 3.31: Shaper and BLH blocks diagram. Figure from [51].

(Fig. 3.32). If we consider again a simplified model (Fig. 3.33, signals in 3.34) it ispossible to calculate also in this case the baseline shift.

The integrated charge QC is now limited during the signal duration 2TP:

QC =1

R

∫ 2TP

0

SLtdt =1

RSL2T 2

P (3.31)

where SL is the slope during the charge. The resulting shift is:

1

RδVBLGDTR =

1

RSL2T 2

P ⇒

δVBL = 2SLT 2P

GDrate = VPTP rateSL

2TPVPGD

= VPTP rateK(3.32)

where K = SL2TPVPGD

with an evident advantage with respect to the previous solution.

The circuits proposed by De Geronimo (fig 3.34) is a very compact architecturewhere the pole and the non linear buffer are made with two followers with capacitiveload.

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Figure 3.32: Output with a non linear elements that reduce the integrated charge.

Figure 3.33: Equivalent model for the BLH with a non linear element, also in this case the amplifiersaturates to VDD.

The circuit works as described before, the output of the shaper is amplified by thedifferential amplifier that saturates to VDD, the first follower charge the C1 with a fixedcurrent non linear buffer and than the signal is low pass filtered. The transfer functionis:

I(s)

VOUT (s)=

GDgm0(1 +

sC1nPVTHIP

)(1 +

sC2nNVTHIN

) (3.33)

where gm0 is the traconductance of the last stage for the conversion voltage to current,IP and IN are the currents The denominator is composed by two parts related to the two

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Figure 3.34: Output before (a) and and after (b) the non linear element.

Figure 3.35: De Geronimo’s architecture with the non linear buffer and the low pass filter made ascascade of followers with capacitive loads.

capacitors and the transistors in weak inversion. The system has two poles and the onerelated to C1 should be out of the BLH band for stability of the complete loop. The lowpass filter is composed by an integrated capacitor and a transistor in weak inversion, fora pole at 10 Hz and a capacitor of 10 pF, the required current is in the range of pA, avery low current not easy to be controlled. The K parameter calculated in [51] is:

K =2

GD

2T 2P IPC1

+∫∞

02TP

IPC1e

(−t

nP C1VTHIP

)dt

2V DDTP(3.34)

The slew rate limitationINC1

can be used in the equivalent model, the resulting shift

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(with, for instance, IN=1 nA and C1= 200 fF) is 16 mV, one order of magnitude betterthan the one obtained with the only saturation of the amplifier (other parameters are thesame).A simplified schematic without current references of our implementation is shown inFig. 3.36.

The input single stage amplifier has a gain of 25 and the input Vbl is connected toground. The following stage composed by M1, M2 and M3 is the non linear buffer,when the output of the amplifier switch off M1, the current I1 charge C1 (200 fF). M2 istwo times bigger than M3 and so M2 is always working in ohmic region, if the output ofthe shaper is lower than the reference (for instance an undershoot of the shaper output),the output of the amplifier is negative and M1 is ON discharging C1 with an highercurrent (higher of a factor given by the ratio WM2/WM3). This trick of an higher currentallows a faster recover of the baseline value in presence of undershoot of the outputshape.

The low pass filter composed by C2=20 pF and M4 in weak inversion. The currentI2 is 20 pA and it is obtained with different current mirrors designed with commoncentroid structures. The reference currents are provided with current DAC in order tomodify the value of the "slew-rate current" (I1) and of the "pole current" (I2) during thedebug. The most complicated configuration for the stability (i.e. what limits the posi-tion of the pole) is the longer peaking time (3.94 µs) with the higher gain. The last stageperforms the voltage to current conversion is done by the M9 transistor degenerated byM10 biased in ohmic region. Changing the bias reference (again with a current DAC)it is possible to modify the gain of the BLH. The output is connected to the virtualground of the first stage of the shaper and so the noise of all the components after thelow pass filter, in particular M9 and M10 are directly compared with the output of thepreamplifier, and they must be minimized. Fig. 3.37shows a simulation of the outputof the shaper and of the preamplifier (zoom) when a signal with 20 kcps rate is appliedat the input (at 300 ms, peaking time of the filter 600 ns). The resulting shift is verysmall and almost constant with a fixed input count rate.The BLH for the fast channel is designed with the same structure of the main one, alsosharing the most sensitive parts of the layout. In the fast shaper the poles are at higherfrequency and therefore the design of the low pass filter is a less complicated. The C2

capacitance is 10 pF in order to reduce area occupancy and the pole current is higher tohave a more robust circuit.

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Figure 3.36: BLH circuit for the HTRS chip, current mirrors branches not shown.

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Figure 3.37: Simulated output response of the shaper with the BLH connected. Above zoom of the outputof the shaper, below zoom of the output of the preamplifier (ramp). The signal with 20 kcps rate startsat 300 ms. The output of the baseline is held with a small shift. The picture is a zoom and the partbelow the baseline (picture above) are undershoots of the shaper response.

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3.2.4 Design: Peak Stretcher and Pile-Up Rejector

For the maximization of the event throughput the solution proposed by Goulding [52] isthe best strategy to discard only events really corrupted by pile-up. The main block ofthe pile-up rejector circuit (PUR) are a 3-phase peak and hold circuit (also called peak-stretcher, PKS) and a digital logic that implements pile-up monitoring and rejection.The logic, using the fast shaper output, starts an inspection window (selectable, with aduration proportional to the peaking time of the main channel) for each photon detected.If only one photon arrives in a single window, the corresponding event is eligible forthe acquisition and correctly held by the PKS. On the contrary, if more than one photonis detected in the window, the PKS promptly discards the pulse and tracks again theshaper output without adding further dead-time. Using this strategy, instead of waitingfor the shaper to exceed again the given threshold (as adopted in other solutions inliterature), also acquiring partially overlapped pulses with uncorrupted peak amplitudesis possible.

The output of the main shaper is connected to a dedicated PKS that detects and holdsthe maximum value of the pulse until the PKS is reset. Figure 3.38 shows a simplifiedschematic of the peak stretcher. The choice and operation of the PKS are related to theoperation of the PUR. Let us start considering a peak stretcher permanently connectedto the shaper amplifier. Supposing that the semi-Gaussian signal has reached its maxi-mum upon the occurrence of an event. Then, the PKS is holding the peak amplitude. Ifa second pulse with higher amplitude occurs in the same channel, the PKS updates thestored value with the second amplitude, losing the first one. A 2-phase PKS [53] [54]allows overcoming this limitation because it holds the maximum peak disconnectingthe PKS input from the shaper output. In order to reset a PKS and re-activate it for anew incoming pulse, two different approaches are commonly used: reset the PKS fora fixed time after peak detection or keep the PKS reset until the output of the shaperhas fallen again below a fixed threshold. The first approach is not totally safe (with-out adding a complex control logic) because incorrect amplitudes can be detected (asshown in the example in Fig. 3.39 a). The second approach is, on the contrary, saferbut drastically reduces the throughput at very high count rate because it imposes a veryconservative condition on the output of the shaper amplifier, which does not fall belowthe threshold in case of partially overlapped pulses with uncorrupted amplitudes, whichare, nevertheless, discarded.3-phase paek stretcher.

Figure 3.38: PKS circuit diagram. During the "tracking phase", the switch T is closed, and the circuitworks as a buffer with the input voltage reported on CH.

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Figure 3.39: a) Example of an erroneous peak detected in a standard PKS with a fixed reset time. Uponthe arrival of next event, the PKS after reset is not able to reach the correct amplitude of the secondpeak. b) Correct peak detection with tracking.

A modified version of the conventional 2-phase PKS by adding a 3rd phase has beendesigned. Like in the 2-phase PKS, the 3-phase PKS tracks the input pulse in theWRITE phase (W switches closed, R switch open), while holding the peak amplitudein the READ phase (R switch closed, W switches open). In a 2-phase PKS, the circuitalways operates in the WRITE phase as long as it reached the peak, then switches tothe READ phase. In this 3-phase PKS, on the contrary, the sequence of the WRITE andREAD phases is enabled only around the peak. In the third phase, called TRACKING,the PKS operates in a buffer configuration (T switch closed in Fig. 3.38). During theTRACKING phase, even if the WRITE signal is high, the PKS cannot enter into theREAD phase.

In Fig. 3.40, a description of the operation of the 3-phase PKS is shown. The 3-stagePKS remains in the TRACKING mode (therefore operating as a buffer with respect tothe voltage on CH) until an event is detected by the fast shaper and a correspondingtrigger TR_ FAST is raised. After a programmable time (Program. delay in Fig. 3.40)from the falling edge of TR_ FAST, a signal PKS PHASE is activated. The programma-bility of the delay allows easily adapting the method with all the peaking times. Duringthe PKS PHASE activation, the WRITE/READ operations are enabled as in a standard2-phase PKS, and the transition between WRITE and READ can occur. After the con-version of the analog value stored in CH, the circuit can be reset (end of READ phase).This is accomplished in the 3-phase PKS with a transition of the circuit again in theTRACKING phase which allows the voltage on CH to track the voltage at the output ofthe shaper as fast as possible. The circuit is, therefore, quickly re-armed to record a newpulse, as shown in the example in Fig. 3.40, where a new event is available (second TR_FAST and a new PKS_ PHASE are activated to record the peak of the second pulse).

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This represents an advantage of this solution with respect to those PKS circuits that arere-armed only when the shaped pulses go back below a given threshold, a conditionthat would not allow the circuit to record the peaks of two closely-spaced pulses as theones demonstrated in the example of Fig. 3.40. All the inspection windows used by theinternal logic are generated on chip, and their duration can be trimmed changing bitsin the internal registers; the regulation allows adapting the procedure for each shapingtime.

Figure 3.40: Operation of the 3-phase PKS with indication of the most significant command signals.In the TRACKING phase, the PKS is in the buffer configuration, tracking the shaper output. TheWRITE and READ phases typical of a 2-phase PKS are activated only in proximity to the peak of thesemi-Gaussian pulse, enabled by the temporal window PKS_ PHASE.

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Pile-up rejection circuit.Fig. 3.41 shows the principle of the pile up rejection (PUR) strategy for the fastestpeaking time. In the cases shown, the output of the 9th order complex-poles shaper hasa rise time of 500 ns from 1% of its amplitude to the peak and a fall time of 600 ns fromthe peak to the 1% of its amplitude. Both the rise and fall times scale linearly with thepeaking time. The aim of the PUR for the shortest time (600 ns) is: I) to discard bothconsecutive pulses if they fall within 500 ns time distance, II) to record the first pulseand reject the second one, if they fall between 500 ns - 600 ns time distance (becausethe first one is not affected by the raising tail of the second one), and III) to recordboth pulses if they fall above 600 ns time distance (because also the second one is notaffected by the falling tail of the first one). In Fig. 3.42, the signals activated by the

Figure 3.41: Desired processing of the pulses to maximize the throughput. I) both events have to bediscarded; II) first event has to be read, second event is corrupted and must not to be read; III) bothevents have to be read.

peak logic during the PUR operations are presented in two cases of events. When aTR_ FAST occurs, another inspection window called T2 is open. Its length depends onthe peaking time being used (600 ns in the case of the shortest peaking time consideredin the circuit). If T2 goes to 0 without other TR_ FAST events, as in the case of thefirst pulse shown in Fig. 3.42, the amplitude is correct, and it has to be read. If oneTR_ FAST occurs in a T2 window, this control window is extended, a PUR signal isgenerated, and no amplitudes are recorded as long as PUR is on (the PKS does notenter in the READ mode). In the case of the couple of closely-spaced pulses in Fig.3.42, PUR is activated before the first pulse reaches the maximum, and therefore bothpulses are discarded (case I in Fig. 3.41). If PUR is activated just after the first pulsehas reached the maximum (case not shown in Fig. 3.42, corresponding to case II in Fig.3.41), the first pulse will be recorded, and the second one discarded (only in the firstcase PKS_ PHASE is high, and the peak-stretcher switch into READ phase) [55].

In Fig. 3.43, an example of a simulation of two pulses separated by 700 ns is pre-sented. In the figure, the main digital signals, TR_ FAST and T2, are shown. T2 of thefirst pulse ends just before the second fast trigger occurs. In this situation, both pulses

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Figure 3.42: The proposed pile-up rejection strategy. The length of the control window T2 is equal tothe falling tail of the semi-Gaussian pulse. If a TR_ FAST occurs in this phase, the T2 windows isextended for another peaking time.

Figure 3.43: Simulation of two events close together. The signals have the same amplitude and they arecorrectly read.

can be recorded, as it can be observed in the waveform of the voltage on the capacitanceCH that correctly samples the amplitudes of both pulses.

Many simulations have been done with randomly distributed signals both in timeand amplitude. The sequence of events have been generated with Matlab script andapplied as input to the system in Cadence.

Most of the logic designed is based on standard logic gates and monostable circuitwith a variable duration of the output pulse. The only circuit with a more complicatedcircuit is the one for the regeneration of the T2 signal. Fig. 3.44 shows the generalstructure for the generation of the T2 signal, Fig. 3.45 shows most relevant block, the"Delay switched".

When an event is detected the trigger on the fast channel (TR_ FAST) turns to 1updating the output T2 of the FF A which turns to 1. T2 is inverted turning to T2_ Nand delivered as the input of the delay switched block. The input inverter switches anda current charges one of the two capacitors, C1 or C2, causing a ramp at switch_ out

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Figure 3.44: Circuit for the generation of the T2 signal. MR is the master reset of the logic.

Figure 3.45: Circuit for the regeneration of the T2 signal.

node. If no TR_ FAST occurs, the Q2 signal does not change its state and the rampcontinues, when the ramp exceed the ground level (it starts from VSS=-1.7 V) a digitalsignal (delay out) is provided to the logic, causing the end of the T2 window and thecommutation of Q2. This is the condition of no pile-up detected (Fig. 3.46). Changingthe current reference (that is connected to a current DAC) it is possible to change theduration of the window T2 according to the peaking time. On the contrary, if a TR_FAST occurs during T2, the Q2 signal change its state and one of the two capacitors isdischarged and the other one starts the new integration and the T2 windows is extended(pile-up detection case, Fig. 3.47 ).

The T2 window can be extended for a virtual infinite time, depending of how manyTR_ FAST are detected until T2 is not ended, using alternately C1 and C2.

In alternative to the described pile-up rejector circuit, another logic has been de-signed in the ASIC. This logic disables the fast channel and the signal is acquired bythe peak-stretcher when the output of the shaper exceeds a given threshold.

3.2.5 Design: Peripheral circuits

The ASIC includes also other circuits, the most significant will be briefly described inthis paragraph.

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Figure 3.46: Control signals without pile-up.

Analog Multiplexer. As already mentioned, the outputs of the channels are notconnected to individual pads but to an analog multiplexer (A-MUX). All the ASIC, andin particular the PUR logic has been design to maximize the throughput and thereforealso the multiplexer must be very fast. The A-MUX consists in principle in simpleanalog switches with a proper logic that control them. The difficulty is to work at highfrequency with a negligible error due to charge injection.

Our MUX works in sparse mode and it requires two signals from the external DAQ:the clock and the enable (MUX select). During an acquisition all the channels areinspected but only if the peak stretcher is in READ a valid signal is multiplexed.

In order to exploit a very fast acquisition the multiplexer can work also in a 4+4 con-figuration, i.e the multiplexer is split in two MUXs working in parallel. The maximumworking frequency of the designed multiplexer is 15 MHz (on both configurations).

Output buffer. The output of the multiplexer must be drived at the output of theASIC, and to an ADC, and therefore an output buffer is necessary. The architecture isreported in Fig. 3.48 where from a single ended input a differential output is derived.

The designed buffer has a closed loop bandwidth higher than 150 MHz in order tobe not a limitation for the multiplexer. The buffer is also designed for a 50 Ω load.Two output buffers are included for the 4+4 channels configuration. When the circuitis configured with 8:1 multiplexer, the second buffer is switched off to save power.

The complete layout of the ASIC is shown in Fig. 3.49 with the main blocks high-lighted (the area is 15 mm2).

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Figure 3.47: Control signals with pile-up.

Figure 3.48: Output buffer architecture.

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Figure 3.49: HTRS chip layout. Area 15 mm2.

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3.3 Experimental Set-Up

The experimental set-up adopted for the measurements is basically composed by twoboards: an ASIC board and a data acquisition (DAQ) board. The ASIC board includesvoltage supply filters, digital I/O optocouplers and buffers for some test outputs. TheASIC is host in a 128 pin ceramic carrier. The DAQ, provided by XGLab srl, board isbased on an FPGA and performs both data acquisition and ASIC programming throughthe SPI. It is able to read the ASIC output multiplexed up to 15 MHz. The analog signalis transmitted from the ASIC to the DAQ in a differential mode in order to reduce pick-ups. The signal is then sampled with a commercial 16-bit resolution ADC. The sampleddata are buffered into the FPGA that stores the spectra (up to 8 spectra, with 13-bit ADCresolution) and then transmits the data via USB protocol to the host PC. All the spectraare accumulated in the FPGA, and only the 8 spectra are transmitted with a refresh rateof 5-10 ms. All the acquisition parameters (i.e. acquisition clock, ASIC configuration,and other system settings) are controlled through a custom software interface. A simpledata flow diagram of the system is shown in Fig. 3.50.

Figure 3.50: Blocks diagram of the system, with functional flow chart of the DAQ.

A picture of the system is shown on Fig. 3.51. The ASIC board is relatively bigbecause it includes several test features. For applications where compactness is anissue, the ASIC board could be reduced to include only the ASIC, the mentioned filtercapacitors, and I/O connectors.

3.4 Experimental Characterization

The test conducted on the ASIC have been of two different types, a functional for thetest of the overall functioning and an experimental one with a calibration radioactivesource (55Fe, widely used in X-ray spectroscopy).

The first circuit tested has been the preamplifier, that can be tested only with a SDDwith integrated JFET (the loop is closed inside the detector).

For the emulation of the input signal, the method of pulsing the R1 ring has been

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Figure 3.51: Picture with ASIC board (on the left) and (DAQ board on the right).

used. It consists in a voltage step, generated with a standard waveform generator, su-perimposed to the biasing of the first ring. This can be done pulsing the bottom of adecoupling capacitor on the bias line. The charge delivered can be easily calculatedfrom the amplitude of the step and the capacitor value.

Other tests have been done with the calibration source. Screenshots of the oscillo-scope with the most relevant waveform of the preamplifier are reported in Fig. 3.52,3.53, 3.54 and 3.55.

Figure 3.52: Integration of the leakage current in the feedback capacitance, traditional ramp like re-sponse of the preamplifier.

Figure 3.53: Signals from calibration source superimposed to the ramp.

A complete FWHM vs peaking time curve has been obtained with bench instru-ments, a discrete components shaper amplifier (Tennelec mod. Tc244) and an acquisi-tion system (Silena mod. 7423). The results in terms of noise are very similar to otherobtained with similar readout architecture, confirming the good noise performance. Thecurve obtained with a circular SDD is reported in Fig. 3.56. As comparison the bestenergy resolution reported in the datasheet is 131-132 eV FWHM at 3 µs (about 6 µspeaking time).

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Figure 3.54: Zoom of the individual signal with the voltage step.

Figure 3.55: Reset phase with overshoot, the integrated logic inhibits a second not wanted reset.

The available peaking times of the integrated shaper are not enough for a completecurve, but with the same detector the energy resolution obtained is almost the same ofsimilar peaking time of the bench instrument (the shaper can not be exactly comparedbecause the transfer function is different). For example an energy resolution of 137 eVwith the full integrated chain and dedicated acquisition has been obtained at 3.94 µ s or179 eV at 600 ns.

Outputs of the shaper are shown in Fig. 3.57 and 3.58. The measured peaking timeis very close to the one designed.

Some measurements have been conducted acquiring signals at the output of differentpoints of the elaboration chain: shaper, peak stretcher and multiplexer output (withproper bench instruments). No differences in noise measurements have been noticedconfirming that the noise contribution is mainly due to the preamplifier stage.

The multiplexer has been tested at different input frequencies, and it works up to themaximum tested frequencies of 15 MHz with both the 8:1 or 8:2 (4+4), Fig. 3.59 at 10MHz.

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Figure 3.56: FWHM at MnKα with the integrated preamplifier and external shaper amplifier and ac-quisition.

Figure 3.57: Output of the main shaper with three setting (waveforms superimposed) 600 ns (yellow),1.5 µs (red) and 3.94 µs (cyan), and the fast shaper (blue).

Figure 3.58: Output of the shaper with fixed peaking time (1.5 µs) and four gain settings.

Figure 3.59: Positive output buffer (yellow) with clock (blue, 10 MHz) and select signal (green) of onechannel in configuration 4+4. The digital signals are in LVDS standard (here the positive one).

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3.4.1 Tests with CMOS preamplifier.

Few weeks after starting the experimental characterization, the HTRS project was dis-continued (with all the IXO mission) and therefore the purpose of the tests has beenmodified in order to exploit the best performance in terms of high resolution at highinput count rates. For this reason, the ASIC is used in combination with SDD read byCMOS preamplifiers developed in our laboratory for other projects, that achieve betterperformance at short peaking times (i.e. high rates) a very promising technology forSDDs readout. The advantages have been mentioned in the Chapter 2, for example amore standard and cheaper detector technology that does not requires the integrationof the JFET. The use of SDD with integrated JFET has been discontinued for the de-velopment of the CMOS read-out and only one SDD sample has been tested with thedesigned preamplifier (results reported in the previous paragraph). No tests have beenconducted with droplet-SDD. The CMOS preamplifier ("CUBE") is totally compatiblewith the designed ASIC because its output can be connected to the input of the shaperbypassing the integrated preamplifier (the output of the integrated amplifier, i.e. theinput of the shaper, I remember is available on the board because the feedback of thepreamplifier is closed inside the detector). The only care is to switch-off the integratedpreamplifier.

The reference SDD employed here has an area of 10 mm2. The measurements areperformed at -40 °C (the SDD was cooled with a Peltier cell) in order to minimizethe noise due to the leakage current. In Fig. 3.60, the measured spectrum of the 55Fesource is shown. The energy resolution of the Mn-Kα line is 126.2 eV FWHM usingthe complete acquisition chain, with the optimum peaking time of 1.5 µs (with CUBEpreamplifier the optimum is at lower peaking time with respect to the SDD with JFET).The input count rate is 115 kcps and this resolution corresponds to 5.0 electrons rmsof noise. The measured dispersion of the channel gains within one ASIC is in theorder of 0.5% rms with a maximum deviation of about 1.5%. The measured offsetbetween channels is about 60 eV rms with a maximum offset dispersion of 135 eV.These values are small enough to guarantee that the channels have similar dynamicranges: nevertheless the spectra from the channels have to be independently calibratedbefore combining the data.

The SDD+CUBE combination offers very good performances at short shaping times.Measurements of the energy resolution has been done also with the shortest peakingtime available (600 ns), with different values of the input count rate; very good resultshas been obtained, for instance, an energy resolution of the Mn-Kαline of 130.8 eVFWHM has been measured with an input count rate of 115 kcps, or 144 eV with inputcount rate 800 kcps (Fig. 3.61).

The efficiency, calculated as the ratio between the input count rate and the outputcount rate, is reported in Fig. 3.62 for different count rates, moving the calibrationsource closer and closer to the detector. The input count rate is estimated with a com-mercial digital pulse processor with the 40 ns peaking time setting (underestimationbecause also pile-up on this channel can happen) while the output count rate is the in-tegral count of the spectrum. Longer is the peaking time, lower is the efficiency. Inparticular with 4 µs the efficiency drops to less than 5% at 325 kcps while the with 600ns is still good (40 %) at the maximum rate achievable on the single channel.

Fig. 3.63 shows a comparison between the results obtained and the theoretical lim-

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Figure 3.60: Spectrum of the 55Fe source measured with an SDD and the CMOS CUBE preamplifier(temperature of -40 °C). The best energy resolution of 126.2 eV FWHM was achieved using the 1.5µs peaking time. The input count rate is 115 kcps. The input count rate is estimated with a digitalpulse processor.

Figure 3.61: 55Fe source spectrum measured with a SDD and the CMOS preamplifier, at a temperatureof -40 °C. The peaking time of the shaper is 600 ns. The input count rate is 800 kcps, the output countrate 265 kcps.

itation. Different (more realistic) models have been used for fitting the performancewith good results, for instance a non-paralelyzable system [56] and mixed model [57].

This system is not able to distinguish pile-up on the fast channel and at very highcount rate a broadening of peaks is inevitable. With this system the results in terms ofresolution are anyway very good also at high rates (Fig. 3.64) except for the 4 µs whenthe efficiency is lower than 10%.

A test with one CUBE preamplifier connected to four inputs has been also performedand the result is a total output count rate of the system of 1.4 Mcps with an input countrate of 3 Mcps with the DAQ and ASIC multiplexer in the 4+4 configuration. The

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Figure 3.62: Efficiency as a function of the input count rate for the four peaking times settings.

Figure 3.63: Output count rate with different input count rate (dashed lines are the theoretical limita-tions).

Figure 3.64: FWHM as function of the input count rate.

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spectra are shown uncalibrated in Fig. 3.64 (in the acquisition software by XGLab) andFig. 3.64 (exported in MATLAB) and applying a gain and offset calibration to the fourchannels, Fig. 3.67. The input count rate is 250 kcps per channel.

Figure 3.65: Acquisition with the MCA software interface.

Figure 3.66: Four channels spectra exported in MATLAB.

At the end of this long list of results the effectiveness of the pile up rejector circuitis shown in Fig. 3.68 with a comparison of two acquisitions with or without the pile-uprejector circuit enabled. The pile-up rejection circuit is less efficient to reject photonsclose to the peaking time of the fast shaper. Therefore, the circuit is not able to identifythe arrival of two photons too close in time from one photon with the sum of energies.As a result, the "ghost peaks" at approximately double or triple the Mn-Kα energiesare still present in the spectrum. The double pile-up has three peaks: Kα+ Kα (mostprobable and therefore more counts), Kα + Kβ, Kβ+ Kβ.

During the test we had no the possibility to test eight SDDs at the same time. morethan one year and a half after the end of the HTRS chip test, an array of nine SDDs hasbeen developed for another project (Chapter 4). A test of this ASIC and that detector isa future (with respect to the time of the writing of this thesis, August-September 2013)

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Figure 3.67: Total spectrum with channels calibrated. The input count rate is 250 kcps at -40 °C.

Figure 3.68: Effectiveness of the pile-up rejection strategy. Comparison of the typical spectrum acquiredwith PUR disabled (red) and with PUR enabled (blue). The peaking time is 600 ns, the input countrate is 265 kcps.

development.

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CHAPTER4ESA project

Aim of this chapter is the description of the development of SDD as scintillator lightsensors for gamma ray spectroscopy. The purpose of the development is the demon-stration of the possible use of an array of SDDs for large area 1", 2" and 3" LaBr3:Cescintillator readout.The first part of the chapter introduces the project, the design of themultichannel readout ASIC required and the results obtained with a single SDD ele-ment. The second part is toward the assembly of the final module and characterizationof large area scintillators.

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Chapter 4. ESA project

4.1 Introduction to ESA project

An interesting field of research in astronomy is the study of the elemental composi-tion of planets through the analysis of the gamma-ray lines emitted by spontaneousradioactive decay or by stimulated emission from Cosmic background or highly ener-getic particles originating from the Sun [58]. A simplified schematic view of gamma-ray emission is reported in Fig. 4.1.

Figure 4.1: Nuclear radiation from planetary surface. Figure from [59].

For these planetary γ-ray observations, the research is dedicated to the evaluation oflarge volume gamma-ray detectors based on large lanthanum halide scintillators, likeLaBr3:Ce [60]. The state-of-art in large scintillator readout is usually a detector modulebased on PMT but, as seen in Chapter 2, they show some limitations, in particular thenon linearity in the wide energy range of gamma rays considered for this application,from hundreds of keV to tens of MeV. LaBr3:Ce scintillator is used instead of otherscintillators for the superior performance in terms of energy resolution. In recent years,SDDs have shown to be a valid alternative to PMT with LaBr3:Ce but only results withsmall scintillators are reported in literature [61] [62], while, for these applications, thetarget is the readout of large area (2" and 3" diameter) scintillators. In a collaborationbetween Politecnico di Milano, Fondazione Bruno Kessler (FBK) and European SpaceAgency (ESA), a readout based on arrays of silicon drift detectors has been investigatedto cover such large areas. Tab. 4.1 reports the targets of the project:.

Resolution at 662 keV 3%Count rate <10 kcps

Energy range 150 keV - 15 MeVOperating temperature -20°C

QE of SDD 80% at 380 nm

Table 4.1: Detector unit specifications.

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4.2 Detector

The SDD used for this project are produced by FBK and the readout is based on aCUBE CMOS preamplifier as seen in the second part of Chapter 3. The technology isbased on Neutron Transmutation Doping (NTD) on 450 µ m thick wafers. The completedetector is composed by multiple SDDs units assembled in order to reduce as much aspossible the dead area and therefore the light loss.

Figure 4.2: Lateral view of the SDD.

The single unit can not be round shaped as the traditional SDD, because assemblingdetectors with that shape introduces to much dead space between consecutive pixels. Inthis case the single element is square shaped (Fig. 4.3) like in a previous project [34].In this case the nine square shaped SDDs are part of a single monolithic module (Fig.4.2), assembling multiple modules it is possible to cover the proper area for the requiredscintillator (Fig. 4.4). The size of the single SDD (8 mm x 8 mm) has been chosen afterpreliminary simulations of the ballistic deficit penalization of the single SDD element.The choice of a module with nine detectors is a trade-off between the process yieldand the total dead area when more than one modules are used. The single SDD has

Figure 4.3: Single square shaped SDD element with 8 mm x 8 mm active area.

an asymmetric structure since the light entrance window (opposite to the collectingelectrode side) is realized with a uniform large junction. The n-side of the SDD is quitestandard, with the anode placed in the center of the device and the square shaped driftp-rings (with 50 µm pitch) around it. An integrated voltage divider between first and

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last ring is used for the biasing of the intermediate rings. In the matrix, the outermostcathode (last ring) is in common with all the 9 SDDs and therefore the module has nineanode contacts, nine first ring contacts, one last ring and one substrate contact.The module has 24 x 24 mm2 active area with 1 mm border, the electrons generatedin this zone (due to scintillation or thermally generated) are collected by an n+ ring(grounded) and they do not contribute to the signal. Guard Ring terminations (both onthe top and the bottom sides, standard in FBK designs) are used to smoothly reducethe voltages applied for biasing (150 V for the last ring, one V depletion more than theentrance window voltage).

Figure 4.4: Matrix made up of 3 x 3 SDDs (8 x 8 mm2). The lateral side of the matrix is 26 mm, theactive area is 24 x 24 mm2 and 1 mm of border is the dead area.

The light entrance window is optimized for UV light detection (the LaBr3:Ce emitsat 380 nm). This part of the spectrum is quite critical because the photon absorptionoccurs within the first 10 - 20 nm of the surface. A very shallow junction is required toavoid recombination of the photo-generated electrons. A special Anti-Reflecting Coat-ing (ARC) developed by FBK is also used for the minimization of the light reflected.

4.2.1 Single Side Biasing

In order to bias the back electrode (which acts as entrance window) of the SDD withoutcontact it,the technique based on punch-through between the back electrode and lastdrift ring in the opposite side is applied. A complete description of this technique canbe found in [63]. With this bias scheme is possible to avoid the bonding on the backside for the electrical connection (and therefore to reduce the dead area required for in-stance in the nine modules configuration) and to simplify the optical coupling betweenscintillator and detectors. An example of simulations by FBK on the electrostatic po-tential and current densities is shown in Fig.4.6. If the back electrode is left floating,when the voltage reached by the last ring on the opposite side of the device is more

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Figure 4.5: Sketch with the readout strategy based on multiple SDDs modules for scintillators of differentsizes.

negative than the depletion voltage characteristic of the wafer, a small current startsflowing between back electrode and last ring. This current is due to holes created in thedepletion region of the device which are collected by the back electrode and then flowto the last ring because of the punch-through mechanism. At the same time, the backelectrode potential starts following the potential of the last ring with a constant voltagedifference of Vdepletion. The detector is fully depleted and thus operative before thelast ring voltage reaches 2Vdepletion (and, consequently, the back electrode reachesVdepletion) because of the voltage applied to the first ring. In Fig. 4.6a, the equipoten-tial lines in the SDD are shown, with reference to the main electrodes involved in thebiasing. Fig. 4.6b shows the fully depletion and Fig. 4.6c the electron current density.It can be observed that the electrons created in the SDD active area defined by the firstand the last rings are driven toward the collecting anode, while the electrons createdexternally to the last ring are collected by the external substrate contact, held to 0 V inthis simulation. In Fig. 4.6d, the hole current density in the device. The large holesflow from the back electrode to last ring, because of the punch-through mechanismsupporting the bias of the floating back electrode, can be observed [64]. If the voltageis increased too much (in absolute value) a punch-through can happen also between theback and the first ring with a large current injection.The squared shape SDD has been simulated to estimate the contribution to the anode

signal given by the peripheral regions in which the drift field is not linear. When aγ-ray is absorbed inside the scintillator, light is spread and detectors are illuminatedwith a distribution related to the interaction point (a sort of cone of light). Assuming anuniform illumination, the charge is generated uniformly on the detector surface. Thedrift time is function of the distance d from the anode and it can be estimated as:

tdrift =l

µnE(d)(4.1)

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(a) Electrostatic potential. (b) Electron concentration (color scale: violet = 0, red=1e13 cm-3).

(c) Electron current density (color scale: violet = 0, red=5e-5 A/cm-3)

(d) Hole current density (color scale: violet = 0, red =5e-5

A/cm-3).

Figure 4.6: Vcathode= -180 V (below twice the full depletion voltage) of a SDD. Dimensions in the axesare microns. Dimensions do not correspond to the real SDD developed but to a device simulated toshow the principle. Courtesy of FBK.

with E(d) the drifting electric field in the device, dependent on the distance from theanode, and µn is the electron mobility of the substrate. Fig. 4.7 shows on the left the

Figure 4.7: Simulated drift time distribution (left) and anode signal(right) composed as result of chargecollected in different zones (with different drift times).

drift time for different areas of the detector, and on the right the anode signal. The

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charge collection can be divided in three different phases. In the first phase the chargecollected in the central region, is responsible for the linear rise of the signal and it endsin about 400 ns. The second and the third regions contribute with the slower drift timesand they are responsible for the long decay time of the signal that can be consideredended at 4 µs. The estimation of these parameters is fundamental for the optimal choiceof filter.

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4.2.2 Energy resolution with scintillator and SDD detector

The energy resolution dependence from the detector and scintillator parameters can beanalytically described according to [65] by a series of dependent processes: productionand collection of scintillation photons, photoelectrons generation, collection of pho-toelectrons by the detector, multiplication phenomena in the detector (for instance inPMT not in the case of SDD). The processes are stochastic and they can be describedby a probability distribution that contributes to the final mean and variance and accord-ing to [66]. The energy resolution, ∆E/E, of the full energy peak measured with ascintillator coupled to a photodetector can be written in a general form:(∆E

E

)= R =

√R2int +R2

coll +R2stat +R2

noise (4.2)

where Rint is the intrinsic resolution of the crystal, Rcoll is the transfer resolution orcollection efficiency,Rstat is the statistical contribution andRnoise is the noise contribu-tion. Supposing that photon generation inside the scintillator follows Poisson statistics,and considering negligible, compared to the other components, the transfer component(Rcoll), the energy resolution can be described for detector without multiplication [33]by:

∆E

E=

2.35σ

Epeak= 2.35

√(∆E

E

)2

int+

1

Ne(1−BD)+

ENCTOTAL(1−BD)2N2

e

(4.3)

with:

- ∆EE

is the energy resolution (%FWHM);

-(

∆EE

)int

is the intrinsic resolution of the scintillator, related to several effects: likeinhomogeneities due to the local variation of the light output in the scintillator,non-proportionality of the scintillator response, ecc... [67] [68] [69] [70];

- Ne is the total number of carriers (electrons in our case) generated in the pho-todetector. Ne = ηcηqEγY , where ηc is the collection efficiency of the crystal-photodetector, ηq is the quantum efficiency, averaged over the whole emissionspectrum of the scintillator, Y is the scintillator yield and Eγ is the energy in keV;

- BD is a parameter associated to the ballistic deficit;

- ENCTOTAL is the total equivalent noise charge, with a single SDD is the ENC,with multiple detectors, can be defined as NSDD × ENCmean whith NSDD thenumber of detectors and ENCmean is the mean value of the ENC of all the ele-ments ( noise is statistically indipendent among channels).

Equation (4.3) can be briefly commented:

-(

∆EE

)int

is a fixed contribution (in first approximation), only related to the scin-tillator composition;

- 1Ne

is the statistical spread due to scintillation-photon generation, the photon-electron conversion inside the photodetector. This term can be minimized using

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bright scintillators, high quantum efficiency detectors, covering the scintillatorwith high reflectivity materials and optimizing the optical coupling. This term isworsened by the ballistic deficit effect (see below);

- ENC2

(1−BD)2N2e

is the statistical spread due to the electronic noise of the photodetectorelectronics readout and it can be reduced with low-noise readout chains and again,in relative terms, increasing Ne.

The energy peak (centroid of the spectrum) at a given energy, measured in electrons, isaffected by the ballistic deficit, that can be estimated by:

Epeak = NeMax[y(t)]

Max[h(t)](4.4)

where h(t) is the δ response of the shaper, i.e. the output of an ideal signal, while, y(t)is the output when a real signal is collected at the detector anode (Fig. 4.8). The realsignal collected at the anode is affected by the decay time constant of the scintillatorand by the time required to collect all the charge at the anode. This last aspect for theSDDs in this project is dominated by the drift time of the electrons from the borderof the square to the center anode. The information is correlated to the amplitude ofthe pulse (sensed by the peak detector and converted by the ADC) and it is evidentthat in the real case the equivalent Ne measured is lower than the ideal one. The (4.4)expression can be rearranged:

Epeak = Ne(1−BD) (4.5)

where BD is:

BD =Max[h(t)]−Max[y(t)]

Max[h(t)]= 1− Max[y(t)]

Max[h(t)](4.6)

The ballistic deficit affects not only the the number of electrons but also the ENC,according to:

ENCreal =ENCideal1−BD

(4.7)

Both ENC and BD are function of the peaking time but their dependence is opposite,the BD is minimized with long processing times but not the ENC that increase beacuseof leakage current contribution (still relevant at the operating temperature of -20°C).

4.3 LaBr3:Ce scintillators

The scintillator used in this project is the LaBr3:Ce. This crystal is characterized by a5.29 g/cm3 density, a very high light output (64,000 ph/MeV), which is of the same or-der as that of CsI:TI, as well as by a very short decay time (16 ns), which is at the samelevel as that of LSO and better than NaI(TI). LaBr3:Ce crystals have emission peaks at360 nm and 380 nm. A comparison of the characteristics of scintillators is reported inTab. 2. The light output is constant in a wide range of temperatures as well as the decaytime (unlike for instance CsI [71]). The constant of the decay time in temperature is

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Figure 4.8: Representation of the ballistic deficit. h(t) (blue) is the ideal δ response while y(t)(red) is theoutput when a real signal is collected.

Max. emission wavelengh [nm] Light Yield [ph/keV] Decay time [ns]NaI:TI 415 38 250CsI:TI 550 54 1000CsI:Na 420 41 630

CsI 315 2 16BGO 480 10 300

BaF2(fast) 220 1.8 0.8BaF2 (slow) 310 10 630

LaCl3:Ce 350 49 28LYSO 420 32 41

LaBr3:Ce 380 64 16

Table 4.2: Comparison between emitted light wavelength, yield and decay time of some scintillators.

fundamental for a readout based on SDD because the detectors, and therefore the scin-tillator, are cooled in order to reduce the noise due to leakage current. If the decay timeremains constant the peaking time of the filter should not be increased and it possibleto have all the signal integrated within a shorter processing time, usually a conditionthat minimize the ENC. All of these features make this scintillator very attractive forspace applications. Important drawbacks to avoid cracks in the scintillator are that thecooling must be very slow (8 °C per hour) and the maximum delta temperature alongthe scintillator must be lower than 3 °C for all the temperatures. For this two reasonsthe mechanical support for the detector should be properly designed and simulated andthe cooling of the detector must be controlled by a closed loop control system. Thematerial is hygroscopic and, the for this reason, LaBr3:Ce are usually provided packedwith multiple Teflon layers as lateral reflector and a thin aluminium covering.

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4.4 Detection Unit

According to Fig. 4.5 the modules must be assembled to cover the proper area re-quired for the scinitllator readout, four modules (36 SDDs) for 2" scintillator and ninemodules for 3" scintillator (81 detectors). The SDD must be cooled to reduce leakagecurrent and the related noise and therefore the mechanical support of the single mod-ule must be designed consequently. Fig. 4.9 shows a CAD design of the module withthe SDD matrix hosted in a ceramic carrier (green) and a copper frame (brown). Theceramic (alumina) is used instead of FR4 for its higher thermal conductivity (30 vs.0.25 W m-1K-1). The nine holes in the ceramic carrier are necessary for the anodes-to-

Figure 4.9: Single module with SDD (gray with dead areas white), ceramic carrier (green) and support-ing copper frame.

preamplifiers and first rings R1 bondings, a more detailed schematic view is reportedin Fig. 4.10. The structure of the system is shown in Fig. 4.11, the cooling elements

Figure 4.10: Detailed view of the bottom side of the ceramic carrier with anodes and first rings bondings.

are four Peltier modules with the cold face thermally coupled to a common aluminiumbase where the modules are connected (Fig. 4.11 reports the case of four modules).As seen the scintillator cooling procedure is very dedicated and it must be done withcare, while the constraint of 8 °C per hour can be satisfied with a PID controller onthe Peltier current the constraint on the maximum ∆T requires a mechanical supportsalong the scintillator that help to cool it uniformly. The choice of materials, some incopper others in aluminum (materials with different thermal conductivity), have beenmade after finite elements simulations (COMSOL Multiphysics) on the structure againfor the ∆T constraint. More details on thermal simulations and mechanical design can

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be found in [72]. The structure is than enclosed in a sealed plastic black box saturatedwith nitrogen during the experiments. Real picture is reported at the end of the chapter.Fig. 4.11 reports the aluminum base and the nine modules for the 3" scinitllator read-out (other parts are in common in both cases). The signals and bias are provided with

Figure 4.11: Mechanical structure of the detection unit with four modules, the external plastic housingis not shown.

Figure 4.12: View of the solution with nine modules for the 3" scintillator.

flexible boards connected to the bottom side of the modules and than to a main boardout of the box.

4.5 ASIC

The maximum number of channels in the readout electronics is necessary for the 81 de-tectors required in the 3" scintillator. The output of each preamplifier (one per channel)needs to be connected to an ASIC that provides the analog shaping and the detectionof the peak, i.e. the measurement of the charge collected by the channel. The readoutstrategy is based on the use of three ASICs with 27 channels each. If the configurationof the detector is for the 2" scinitillator, only two ASICs are necessary and the third one

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can be switched off. The readout strategy of the channels is different in this applicationwith respect to the circuit of Chapter 3. In this case when an event is detected in onechannel, all the detectors have to be read because their charge in that instant is relatedto the same gamma that has produced the valid event. Fig. 4.13 shows the block dia-gram of the 27 channels ASIC designed for this application. The technology is standardCMOS 0.35 µm with 0-3.3 power supply.

Figure 4.13: Blocks diagram of the ESA ASIC.

The CMOS preamplifier is a special version of the CMOS preamplifier briefly ex-plained in Chapter 3 with a feedback capacitance of 25 fF and no external referencesrequired. This version has only four pads: input, output, positive power supply andground, while in the standard version two further voltage and current references are re-quired. This optimization has been done to reduce the complexity of the ceramic carrierthat hosts the preamplifiers.The filter choice has been done after preliminary numerical simulations (with MAT-LAB scripts) with the estimated anode signal (Fig. 4.7) convoluted with the impulseresponse of CR-RCn and semi-Gaussian complex poles filters of different orders [73].The filter chosen has been the 7th order semi-Gaussian with complex poles. An highorder filter with this approximation is the best choice for noise minimization and im-munity to ballistic deficit. An higher order filter (for instance 9th) would be a betterchoice for noise minimization but in this application, where the expected ENC is in theorder of 20 e-, the advantage of the noise reduction of the high order weighting functionis marginal. From simulation, the optimum peaking time for the application is between4 µs or 6 µs depending on the effective real gain (ph/keV) of the scintillator and on thereal ballistic deficit (this parameters are difficult to be exactly estimated a priori and, forthis reason, safe margins have been taken, especially for the scintillator gain). The de-signed peaking times are 2, 3, 4 and 6 µs. The first two times are not strictly required forthis application or in general for γ-ray imaging or spectroscopy (with 8 x 8 mm SDDthe ballistic deficit is to high with this times, even more if the scinitillatotr is slower

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than LaBr3:Ce) but they are the optimum when the SDD array is used for X-ray detec-tion. Unlike the circuit presented in Chapter 3, here the pile up rejector is not presentbecause with the longest peaking time designed (6 µs) the percentage of lost eventsdue to pile-up is negligible with the low input count rate of the application (<10000kcps). Also in this ASIC, internal registers (160 bits) are present for programming allthe functions. The programming and the analog to digital conversion are provided by aFPGA based DAQ board described in the following. The channel threshold is arrangedin two levels, a main threshold (generated by a 6 bits internal DAC) is in common to allthe channels (called DAC_ OFFSET) and an independent regulation of it is availablefor each channel. The structure of the in channel threshold generation is shown in Fig.4.14. Connecting or not the second feedback resistor (with R/10 value, controlled by 1SPI bit for all the channels) is possible to modify the regulation, 4 mV or 40 mV perstep (3 SPI bits for 8 steps).

The biasing currents and the voltage references for all the integrated stages are in-

Figure 4.14: In-channel threshold generation, a main level is corrected with 3 SPI bits. A properprogrammable current is used to set the independent value.

ternally generated and can be adjusted changing bits in the SPI. The multiplexer canoperate at different frequencies, 2.5MHz, 5MHz or 10MHz, selectable through theDAQ and it does not introduce in any configuration a considerable dead time for theexpected low rate. The ASIC interfaces with the DAQ with different digital I/O linesfor the programming of the ASIC itself but also and for the events acquisition . When ashaper output signal exceed a digitally selectable threshold a trigger is sent to the DAQ(TR_ OUT in Fig. 4.13, a 27-OR of the single channel trigger) that, as consequence,provides to the ASIC another signal (TR_ IN) that enables the peak stretchers to be readout (i.e., the signal amplitude in every channel is sampled and digitized). Rememberthat in an acquisition of a gamma event inside the scintillator we want to read the totalcharge distributed over all the detectors. During the acquisition phase the trigger logicis no more sensible to the overcoming of the threshold and therefore the acquisitionis disabled. After the sequential acquisition of the analog multiplexer, a reset signalis sent to the channels to discharge the peak stretchers circuits and enable again the

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acquisition. The digital logic inside the ASIC manages also the reset of the preampli-fiers, when a preamplifier output exceed another threshold voltage (digitally selectedwith an integrated DAC) a signal is sent to the DAQ (TR_ PRE in Fig. 4.13, 27-OR ofthe sinlge channel trigger): to maintain the system compact and scalable to an highernumber of channels, the reset signal is in common to all the 81 preamplifiers. All theI/O communication lines are in standard LVDS to reduce pick-ups and interferences.

4.5.1 Dynamic range

Before starting the design of the analog channel it is necessary to know the maximumand the minimum value of the input signal. Unlike applications where the channelsare independent, in this application, the maximum and the minimum signals depend onthe global configuration. The maximum signal is due to the higher energy γ-ray thatinteract just above a detector (almost all the light cone is taken by a single unit). Theminimum signal depends on the minimum charge collected by a detector when mostof the light is collected by other units. Both minimum and maximum signals requireMontecarlo simulations that consider the detector plane (dimension of the single SDD,dead area, number of channels), scintillator (yield, optical interfaces, size, ecc...) andenergy range of the γ-rays. Fig. 4.15 and Fig. 4.16 show the results of the simulationsin the case of 150 keV or 15 MeV γ-ray. The configuration simulated is the morestringent one with a 3" scintillator and 81 SDDs. In both figures on the left is reportedthe interaction points inside the scintillator, on the right the histogram of the chargecollected by a single element (Fig. 4.15 detector with less electrons, Fig. 4.16 detectorwith more electrons). From the 150 keV simulation in most of the cases the minimumcharge is in the order of 150 e- but some iterations give a lower contribution. We set100 e- as minimum detectable signal. The 15 MeV simulation imposes to set 30000 - asmaximum signal on the SDD that collect more charge with a 15 MeV simulation. The

Figure 4.15: 150 keV γ-ray simulation. Points of interaction within the crystal (left) and distribution ofthe charge inside the SDD collecting less charges for each gamma event simulated (right).

amplitude of the maximum voltage step at the output of the preamplifier can be easilycalculated:

∆OUTPREMAX =QMAX

Cf=

30000 ∗ 1.6e−19

25fF' 200mV (4.8)

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Figure 4.16: 15 MeV γ-ray simulation. Points of interaction within the crystal (left) and distribution ofthe charge inside the SDD collecting more charges for each gamma event simulated (right)

with Cf feedback capacitance of the preamplifier equal to 25 fF.The minimum signal:

∆OUTPREM IN =QMIN

Cf=

100 ∗ 1.6e−19

25fF' 0.7mV (4.9)

The detection of small signal may appear useless but it is fundamental to reconstructthe total energy associated to a γ-ray. It is also very important for the reconstruction ofthe position of interaction (imaging), an option not required for this project (pure γ-rayspectroscopy) but interesting for other applications, see Chapter 6.

4.5.2 Design: Shaper and BLH

The read-out chain is designed for high linearity and low noise in the full wide dynamicrange, according to the requirements of the application. The output dynamic range ofthe analog channel is from 500 mV (or another value not below 400 mV set by aninternal DAC) to 3 V. In this case the baseline output is not the reference voltage ofthe single shaper stage (as in Chapter 3 where the output is from 0 to 1.7 V with ± Vsupply) and therefore the shaper can work with the desired baseline value only if theBLH is connected. A DC current is always present in the shaper and in the last stage ofthe BLH. The shaper is a 7th order complex poles semi-Gaussian shaper implementedalso in this case as cascade of biquad cells. In this case the three stages are required forthe three complex conjugate poles and therefore three Rauch cells can be used. Unlikethe HTRS case, in this application, the event rate is very low and the advantages ofan higher order filter (for instance nine poles) do not justify the higher area occupancy(especially with more than 20 channels per ASIC). The voltage swing in this shaperis higher than the one of Chapter 3 and the operational amplifier has been redesignedwith extended dynamic. The following table reports theωn (normalized to the peakingtime) and the Q factor of the shaper. The description of the Rauch cell and expressionsof the components as functions of the ωn and Q have been reported in Chapter 3 andnot repeated here.

The first cell is again the same RC integrator with a coupling capacitor. The gainof the shaper is designed according to the specification calculated in the previous para-

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ωnτP Q factorFirst cell 4.970 -

Second cell 5.08 0.52Third cell 5.46 0.61Fourth cell 6.32 0.85

Table 4.3: Q and ωn(normalized to τp) for the 7th order shaper.

graph with a margin to accommodate different gains of the scintillator. The gain canbe selected in three coarse settings, 10 ke-, 20 ke- and 30 ke- with 4 fine regulations foreach coarse setting (fine regulation obtained changing the input capacitance). Fig. 4.19shows the first stage with the capacitors for the fine regulation, the feedback passivecomponents C1 and R1 are the equivalent components made by series or parallel ofresistors and capacitors to have the right time constant required by a particular peakingtime. The gain, considering the extreme coarse and fine regulations, is between 7500 e-

and 37500 e-.A simulation of the outputs of all the shaper stages is reported in Fig. 4.18. to show thedynamics of the internal nodes.

Figure 4.17: Simulation of the outputs of all the shaper stages.

The BLH is similar to the one of Chapter 3 with only few modifications, the mostrelevant one is the first stage in order to extend the output swing and a 5 pF increase ofthe pole capacitance for stability issue in the higher gain longer peaking time configura-tion. The complete shaper structure with the BLH described by functional basic blocksis shown in Fig. 4.18 where also the DC currents (green) flowing in the BLH and thenode voltages (red) are highlighted for the 500 mV baseline configuration. The outputvoltage level should not be misled because the swing is not full in intermediate stages

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(for instance in the second-last in which has high DC voltage the signal is negative).

In this BLH+shaper configuration a DC current is always present in the last stageof the preamplifier and therefore this current should be always present to close theloop. This condition is always verified except when the preamplifier is reset. Duringthe reset, in fact, the current injected has opposite polarity and without compensationit would cause the saturation of the shaper with undershoots (or overshoots) of thebaseline, compensated with the long time constant of the BLH (a signal that occursduring this phase would have a corrupted amplitude). To avoid this problem, two digitalsignals (Fig. 4.21), synchronous to the preamplifier reset, are provided to the shaperand BLH. Fig. 4.20 shows where the inhibit signals act on the circuits. The INHIBIT_SHAPER signal de-connects the coupling capacitors to the virtual ground of the firstcell and connects a dummy cell that sinks all the current from the preamplifier to holdthe voltages on the shaper that guarantee the desired output baseline. The inhibit ofthe BLH has been object of a deep optimization and, at the end, the solution adoptedhas been to disconnect the output of the differential amplifier. With this solution thesensitive nodes of the BLH (the two capacitors) are not altered and when the reset phaseis finished the deviation of the output of the shaper with respect to the value before thereset is less than 200 µV rms on 100 Montecarlo simulations with the expected range ofleakage currents. The duration of the inhibit signals must be longer than the reset (T1)and, for the best optimization, T2 should be longer that two times the peaking time ofthe shaper and T3 longer than T2.

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Figure 4.18: Shaper schematic with schematized BLH. In green the DC currents required for the outputbaseline stabilization, in red the DC voltages.

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Figure 4.19: First stage with the input capacitors that allow the fine regulations, Cac=25 pF, CacD1=10pF, CacD2=5 pF.

Figure 4.20: Simplified shaper and BLH schematics with switches used for the inhibit during the resetphase.

Figure 4.21: Inhibit signals for shaper and BLH synchronous to the preamplifier reset. T2 and shouldbe longer than two time the shaper peaking time and T3 2 µs more.

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4.5.3 Design: Peak detector

This ASIC works again with peak detection, the output of the shaper amplifier has to beread by a peak detector circuit. The new extended dynamic range and the requirementsin terms of minimum detectable signal required a complete redesign of the circuit withrespect to the solution adopted in Chapter 3, maintaining however the concept ideaof the three phases for the acquisition of the peak amplitude. Fig. 4.22 shows thepeak detector circuit with the digital signals for the phases control highlighted in green.Read signal is the inverse of the write while the track signal is used to connect theholding capacitor to a fixed current Itrack that helps the circuit to follow the inputsignal (especially for low values). In order to satisfy the error of the peak acquisition,the gain of the circuit should be as much as possible during the read phase. The circuitstability is an important issue in the design because the same circuit should work intwo different configurations, when is configured as buffer and when the p-mos currentmirror is connected at its output. Our implementation is based on an OTA designedwithout internal compensation and using in one case (read) a capacitor on the output(Cout in Fig. 4.22) and for the other two (write and read) the pole introduced by thehold capacitor. The Cout value must be chosen taking into account the settling timerequired. Assuming SR=100 V/µs a capacitor of 2 pF guarantee a settling time lowerthan 50 ns and a phase margin of the OTA loop about 75°.In the second phase the OTA has at its output the low impedance of the current mirrorand the stability must be satisfied also in this condition. The maximum current on thehold capacitor and the value of the capacitor itself must be suitable to follow the fastestshaper configuration (2 µs). We set the capacitor 3 pF and the maximum current 40µA (i.e. 200 µA at the OTA output with M equal to 5). With these configurationsthe limiting slew rate is 13 V/µs more than 10 times the limit required by the shortestpeaking time. After the read phase the hold capacitor is discharged by the current Itrackuntil the output of the voltage is the same on the + and - input of the OTA. Assuminga full voltage swing of 2.5 V, a 3 pF hold capacitor and a reasonable time of 6 µs tocomplete the discharge. The minimum current is:

Itrackmin =∆VMAX ∗ CHOLD

∆T

= 1.25µA (4.10)

Itrack is set to this minimum value because higher values have the problem to causeovershoot of the mirror gate when the circuit has the transition between track and write.This overshoot can be misinterpreted by the comparator that sense the gate and have awrong switch from write to read.When the peak detector does not go into read phase, the output voltage is connected toa voltage reference below (100 mV less) the baseline value.The circuit is based on a double input differential pairs. The internal structure of theOTA is reported in Fig. 4.23, the circuit below acts a feedback on the tail current ofthe differential pairs at the border of the dynamic. With this architecture an almostconstant gm on all the input range (from 500mV to 3V) has been obtained. A moredetailed analysis of the circuit can be found in [73]. In this ASIC the pile-up rejectoris not present, and therefore the required controlling logic is very simple and mainlycomposed by a digital circuit that gives a trigger to the external acquisition logic, dis-ables the track phase when a trigger arrive (due to an event detected by another channel

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Figure 4.22: Schematic of the three phases peak detector. Compared to the peak detector of Chapter 3,the buffer at the output of the holding capacitor has been removed to extend the dynamic range.

Figure 4.23: OTA internal structure with a feedback circuit in order to have a constant gm for all theinput dynamic.

or by another ASIC) and controls the switch from write to read phase.

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4.5.4 Design: Complete ASIC

After completing the single channel, the structure has been replicated 27 times andglobal circuits have been designed to complete the ASIC. A single ended buffer hasbeen designed and used at the output of the analog multiplexer, that here works up to10 MHz. The ASIC has the option to completely kill an unused channel (if killed notriggers from the channel) and buffer out the output of the preamplifier or the output ofthe shaper of a selectable one channel for testing purpose. The layout of the ASIC isshown in Fig. 4.24.

Figure 4.24: ASIC layout. Total size about 19 mm2 with 96 PADs.

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4.6 Testing: ASIC set-up

The complete strategy for the readout of all the ASICs is presented in Fig. 4.25. Thedetector array, that hosts also the preamplifiers very close to the SDDs anodes, is con-nected to the ASICs and than to the ADCs, the DAQ and finally to a PC. According tothe size of the scintillator, a proper number of SDDs is used.

Figure 4.25: Schematic readout strategy, on the righ the main functions of the DAQ are summarized.

The ASIC is hosted in single carrier board (Fig. 4.26a) and three of them are con-nected to a another board (Fig. 4.26b) that interfaces the boards with the DAQ system.In particular has the function to distribute the digital signals and it host a differentialbuffers that takes at its input the analog outputs of the ASICs and it drive them to theADCs. The ASIC signals are properly connected in parallel to three ADC cards, one

(a) (b)

Figure 4.26: Pictures of the ASIC boards, on the left board that hosts the single ASIC (under the met-alling box, directly bonded to the PCB) and, on the right, the main board.

per ASIC, that host the commercial analog-to-digital converters LTC2215 (16 bits, 60MSps). The three parallel bit-streams are driven into the digital processing sectionof the module, which is based on a digital Field Programmable Gate Array (XilinxSpartan-3A FPGA) device that plays the roles of main processor and control logic.The choice of a FPGA instead of a digital signal processor (DSP) device, for instance,stems from spatial computing improvements in hardware resource availability and in

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4.6. Testing: ASIC set-up

operating frequency. Digital communication interface is implemented by means of amicroprocessor Atmel AP7000. With a similar architecture very good performanceswere obtained in the readout of detector arrays [74]. The block diagram can be seenon the right of Fig. 4.25, and it shows that the architecture is physically partitionedin three different units: an analog-to-digital conversion board, a motherboard and acommunication board. The analog-to-digital conversion board is equipped with condi-tioning analog circuitry and a differential ADC for each one of the three channels. Themotherboard hosts analog-to-digital conversion and communication boards as snap-inmodules. The motherboard provides analog and digital supplies, generates the neces-sary timing signals for ASICs synchronization with the sampling process, and performstheir initialization. The FPGA device manages the conversion process and generatesdata packets to be sent to the PC for energy reconstruction. The communication boardreceives the frames from the motherboard as 81-pixel packets and forwards them to thePC through an Ethernet interface. Fig. 4.27 shows a picture of the realized DAQ sys-tem. Several and fundamental advantages stem from the partition of the architecture.First, noise reduction since a mixed signal system requires several tricks to minimizecoupling between fast digital and low-noise analog circuits: placing the analog boardaway from the digital section practically eliminates the crosstalk. The choice reducespower density that is significant considering that the analog front-end and ADCs dissi-pate a lot of power and that placing the digital processing unit on the same PCB of theanalog section would overheat the whole system. The reliability of the global systemis positively affected since, for instance, the analog front-end is directly connected tothe ASICs and to the SDD array that is biased at high voltage. In case of overvolt-age, the partition ensures that only the analog front-end boards would be damaged. Anasset of the partitioned architecture is the communication versatility, since the commu-nication standard between PC and the DAQ system is not a-priori fixed. The Ethernetboard could be substituted, for instance, with an USB controller or an optic fiber. Fromfirmware side, the FPGA device manages initialization and control of ASICs and dig-itized data transfer whereas the communication board is a complete single board PCable to run a customized Linux distribution, i.e. a true Linux 2.6 kernel and not a uC-Linux version. This means that the kernel uses the MMU to separate user from kernelmemory space. The communication board is linked to the FPGA using both externalmemory interface (EMI) and SPI bus through a custom device driver [75]. The DAQand ADC boards have been designed by "Digital Electronics Lab" of Politecnico [76].

The ASIC control and the signal acquisition is performed through a PC software,the GUI of the software is shown in Fig. 4.28. The software (VB.NET) includesthe possibility to apply filters to the data acquired and to process the data for res-olution estimation. It also includes the real-time image reconstruction in case theASIC+DAQ+Software is used in applications, for instance medical imaging, wherealso the point of interaction of the gamma event in the scintillator is important. Thealgorithm implemented for reconstruction is the centroid method, if xi and yi are thecoordinates of the center of the cells and Ni is the number of valid events collectedby the detector, then the xp and yp coordinates of the interaction point are evaluatedconsidering a weighted mean of the collected charge, according to the relations:

xp =

∑Ni=1 xi ×Ni∑N

i=1Ni

yp =

∑Ni=1 yi ×Ni∑N

i=1Ni

(4.11)

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Figure 4.27: Picture of the DAQ and three snap-in cards each one with one ADC.

Figure 4.28: Software GUI for ASIC management and signals acquisition. It is based on VB.NETframework.

4.6.1 ASIC characterization

In the first phase the tests have been focused on the characterization of the digital inter-face between the 160bits-SPI inside the ASIC and the DAQ. There were no particularproblems interfacing the two systems so we have been able to establish the right connec-tion during the first test. Fig. 4.29 shows the digital signals used for the programmingphase. The blue signal is chip select (CS), the red the serial input (SIN), the green isthe signal that select (digital lines are shared) if we are in programming or acquisitionphase (SEN) and in yellow the clock at 1.25 MHz during the programming (CK). The

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4.6. Testing: ASIC set-up

three ASICs are programmed sequentially, enabling the proper chip select signal oneafter the other. All the digital signals are LVDS standard.In order to control 3 ASICs, the DAQ provides three CS and three SEN control signals,forwarded by the board that hosts the ASIC, while SIN and CK are in common. The

Figure 4.29: Digital (LVDS standard) signals during the programming phase.

preamplifier reset is a critical phase because the analog channel requires some signals.Fig. 4.30 shows the signals that inhibits the ASIC and reset the preamplifiers. From thebottom to the top: the ramp signal from the preamplifier (brown), the trigger indicatingthe preamplifier exceed the threshold (blue, from one ASIC), the reset signal from theDAQ to all the ASICs (green), the inhibit signal of the shaper (yellow) and the inhibitsignal of the baseline holder (violet) both from the DAQ. The last three signals have aduration that can be arbitrary selectable from the controlling software. Different tests

Figure 4.30: Ramp and digital signals during the preamplifier reset.

have been carried out to estimate the characteristics of both the ASIC and the DAQ interms of gain, linearity, noise, gain spread, minimum detectable signal, ecc. One ofthe main important peculiarity of the ASIC is the extended dynamic range necessary tomatch the required input energy range, from 150 keV to 15 MeV. The measurementsare in agreement with the simulations and the analog channel is able to detect signal atits input from few tens to more than 30k equivalent electrons for all the peaking times.The gain spread between channels is below 0.4% RMS, an example of channel gaindispersion for a fixed gain and peaking time is shown in Fig. 4.31. The shaper gainspread is quite satisfactory but anyway the channels have to be calibrated to compen-

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Figure 4.31: Gain spread between all the 27 channels (analog shaper).

sate the differences of the feedback capacitances of the preamplifiers. The linearity ofthe combination of shaper, peak stretcher and multiplexer is less than 0.1% in all itsdynamic range for all the operating frequencies of the MUX (2.5, 5 and 10 MHz).In order to test the functioning of the peak detector, two signals have been emulatedwith a waveform generator and connected to the input of the shaper (Fig. 4.32). Theconclusions of this test are that the "track" operation works as expected (blue line is thevoltage on the hold capacitor), two signals very close to one another are correctly readand the overall readout strategy of the channels does not introduce a relevant dead timewith respect to the expected input rate.The DAQ single channel has been characterized in terms of noise and linearity. Sam-

Figure 4.32: Acquisition with two input signals close together, in yellow the input, in green the outputof the shaper, in blue the voltage on the hold capacitor of the peak stretcher circuit and in red theoutput of the MUX (positive of the fully differential amplifier on the board).

pling several data stream with both differential inputs shorted to ground and calculatingthe r.m.s. value of the output. Through a number of tests statistically significant, the

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4.7. Testing: Single Detector

noise has been proven be always below a few LSB, which demonstrates that the noiseadded by the input stage is negligible and the correspondent ENOB is congruent withthe expected performance of the system (more than 11 bits).

4.7 Testing: Single Detector

A picture of the 4" wafer (code name ANTARES) of the FBK production is shown inFig. 4.33, where four SDDs arrays can be easily identified. The remaining area is filledwith single SDDs of different shapes, 8x8 mm and 12x12 mm square shaped, 10 mm2

round shaped and 10 mm2 PIN diodes. The square shaped SDDs are very useful forcharacterization, especially the 8x8 mm that is the replica of the single unit of the array.The first characterization of the detectors have been conducted by FBK at wafer level

Figure 4.33: Wafer picture with the four arrays per wafer can be identified. Other detectors are presentin the remaining part of the 4" wafer, in particular 8x8 mm and 12x12 mm square shaped, 10 mm2

round shaped SDDs and 10 mm2 PIN diodes.

for the estimation of the dark current of the detectors and of the quantum efficiency(QE). The average leakage current is in the order of 2 nA/cm2 while the QE result ishigher than 80% at the emission wavelength of the LaBr3:Ce, between 360 and 380nm. The QE as function of the wavelength measured with a SDD and a test photodiodehaving the same ARC is shown in Fig. 4.34 and compared with the simulated values oftransmittivity for the particular dielectric stack composing the ARC. The agreement issatisfactory and this demonstrates that carrier recombination within the boron implantin the entrance window, which is not taken into account by the theoretical curve, isnegligible.Anode current was experimentally measured, lighting a 8x8 mm2 SDD with fast (∼

100 ns) led pulses and acquiring the voltage waveform at the output of the preamplifierwith a digital oscilloscope (the preamplifier can be considered an ideal integrator). Asa consequence the anode current can be obtained by calculating on the acquired data

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Figure 4.34: Measurements of QE for a Diode (circles) and a test SDD (squares) taken from two differentwafers having the same nominal ARC. The good correspondence of the ARC theoretical transmittivitywith the measured QE is an indication that most of the carriers generated in silicon by the opticallight are collected by the anode of the SDD, without significant loss in the entrance window of thedevice.

with a numerical derivative of the output voltage. Temperature affects the electronmobility: lower is the temperature, higher is the mobility, and therefore the collectingdrift process is faster at -5C than at room temperature, as shown in Figure 4.35. [40]In order to verify the performances with radioactive sources, the single SDDs has beentested with a set-up schematized in Fig. 4.36. The set-up is composed by a metallicbox containing the SDD cooled by a Peltier stage in a atmosphere full of nitrogen toavoid ice formation. The bias and signal lines are connected to an external electronicsboard through a flex cable. The SDD chip is placed on a ceramic board which providesgood thermal conductibility (180 W/ms K) and electric insulation. The preamplifieris placed close to the detector and connected directly to the detector by a bondingwire. Bias connections to the preamplifier pads and detector electrodes are made onthe ceramic board by bonding and from the ceramic board to the external board by aconnector and the 20 pins flex cable. The ceramic carrier is fixed on a copper framewhich is placed over a Peltier stage. The Peltier cooler allows to cool the detector toa minimum temperature of -45 °C. However, an intermediate temperature of -20 °Chas been also considered in the measurements described in the following section as areference working temperature for the project. The humidity inside the box is measuredwith a proper sensor. Fig. 4.37 shows the picture of the real set-up, the board outsidethe box contains the network for biasing the SDD and the preamplifier, a buffer for thepreamplifier output and a reset circuitry which reset the preamplifier when the outputvoltage exceed given threshold. The buffered output of the preamplifier is acquired bya standard analog acquisition chain which includes a semi-Gaussian shaping amplifierfilter (Tennelec Tc244, 7 complex poles) and a multi-channel analyzer (MCA), the sameused for Chapter 3 measurements with the preamplifier alone.

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Figure 4.35: Anode current experimentally measured, lighting a 8x8 mm2 SDD with fast (100 ns) ledpulses and acquiring the voltage waveform at the output of the preamplifier with an oscilloscope.The anode current is the derivative of the shaper output .

Figure 4.36: Sketch of the experimental set up for the single SDD characterization.

4.7.1 X-ray characterization

To evaluate the electronics noise of the SDD (in the set-up described in the previousparagraph) some devices have been irradiated with a 55Fe source and the energy reso-lutions at the reference line of Mn-Kα (5.9 keV) have been measured. The electronicsnoise has been calculated from the fitting of the Mn-Kα peak and subtracting in squarethe intrinsic Fano contribution to the energy resolution. The characterization of twodevices, has been done with or without the bonding on the back electrode. The latterone is the one desired to use in γ-ray measurements because this configuration allowsto avoid the bonding that can be damaged by the scintillator, as explained in the chapterintroduction.

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(a) (b)

Figure 4.37: Photographs of the experimental set-up with detector and electronics: a) the biasing boxoutside the box and the ceramic carrier inside. b) detection module including also the scintillator forthe gamma-ray measurements, see next sections.

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Uncollimated source.Fig. 4.38 reports the energy spectrum of the 55Fe source measured at -20 °C with theSDD with the back electrode connected by bonding and biased independently. An en-ergy resolution of 140 eV FWHM has been measured with 1 µs shaping time of thebench instrumentation filter. A corresponding electronics noise of 8.7 e- rms has beenderived. The SDD has been further cooled to -43 °C and an energy resolution of 129 eVFWHM has been measured with 1.5 µs shaping time, corresponding to an electronicsnoise of 5.9 e- rms (Fig. 4.39). We have to report that the device here characterizedexhibits a particularly good value of leakage current at room temperature, less than 1nA/cm2. In Fig. 4.40a, the measurements of the energy resolution (at the Mn-Kα

Figure 4.38: Energy spectrum of the 55Fe source measured at -20 °C at a 1 µs shaping time. The SDDwas operated with the back electrode connected by a bonding and biased independently. The ENC is8.7 e-.

Figure 4.39: Energy spectrum of the 55Fe source measured at -43 °C with 1.5 µs shaping time. Theelectronics noise is 5.9 e- rms.

line) for different shaping times of the filter are reported for the two temperatures. The

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(a) FWHM vs. Shaping Time (b) ENC vs. Shaping Time

Figure 4.40: Measurements at -20 °C and -43 °C, comparison of FWHM (left) and ENC (right) valuesmeasured using all the available shaping times. The SDD is with the back electrode connected by abonding and biased independently.

corresponding electronics noise is reported in Fig. 4.40b. The device has been charac-terized also with no electrical bonding on the back electrode with the biased obtainedthe punch-through mechanism described in section 4.2 [63]. Fig. 4.41 shows the energyspectrum of the 55Fe source with this devices cooled to -40 °C. An energy resolutionof 135 eV FWHM has been measured with 1.5 µs shaping time, corresponding to anelectronics noise of 7.5 e- rms. The resolution is not too far from the one measured withthe previous device at the same temperature. The difference may be attributed mainlyto the better leakage current of the former sample with respect to the second sample(1.7 nA/cm2), important not only at high characteristic time but also at the optimum.A slight tailing of the peaks in the spectrum shown in Fig. 13 with respect to the onemeasured with the previous device may be attributed to a not optimal biasing of thedevice using the punch-through technique. It has however to be pointed out that this as-pect has no practical impact in the scintillation detection capability of the device, whichis the application where the punch-through biasing is considered, because, differentlyfrom X-ray irradiation, in scintillation irradiation the charge is generated uniformly onthe SDD surface. In order to verify the stability of the operation of the SDD devicewhen biased with the punch-through technique, 55Fe spectrum has been recorded atfixed temperature in extended-time measurements without observing noticeable devia-tions in the peaks position. The peak position of the Mn-Kα line has been monitoredchanging the temperature of the detector from -15 °C to -25 °C. The results are re-ported in Fig. 4.42 in which the change of leakage current, measured on the slope ofthe preamplifier ramp, is reported together with the MCA position of the peak. It canbe noted that no significant variations of the peak position (<0.3%) are recorded in cor-respondence of the change of leakage current and of the biasing conditions provided bythe punch-through operation. These results provide good indications of the reliabilityof this bias scheme.Collimated source.In order to analyse the effect of the detection on the edges of the detector, the X-ray

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Figure 4.41: Energy spectrum of the 55Fe source measured at -43 °C with 1.5 µs shaping time. Backelectrode is floating and biased by punch-through. The electronics noise is 7.5 e- rms.

Figure 4.42: Mn-Kα peak stability at different temperatures using the SDD with the back electrodebiased with the punch-through technique. In the plot, the peak position expressed in terms of MCAchannels is reported for different temperatures (with the corresponding leakage current).

source has been collimated focusing the X-rays in different geometrical spots. This testshave been conducted with and without the back bonding and it is useful for the charac-terization of the detector even if it has a relative impact for the application presented inthis Chapter. The irradiating spots are shown in Fig. 4.43. All the measurements herereported have been conducted with the detector at -40 °C with discrete componentsshaper.Fig. 4.44 reports the results obtained with the detector without the back bonding andthe total number of counts in a fixed time for the horizontal and the diagonal positions.The collimator is not able to focus the X-ray with sub-millimeter precision and there-fore also at the estimated border some photons hit the detector. It is evident that due toballistic deficit the shorter times have a great deterioration moving towards the borders.For longer peaking times the effect is less evident. Same measurements have been donewith back bonded, the results are reported in Fig. 4.45. In this case the effect is less

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Figure 4.43: Positions within the SDD. The area enclosed by the blue line is the active SDD area whereasthat in between the blue and green lines is the cutting margin of the SDD. From h13 to h5 the step isabout 1 mm while the last four are 0.5 mm each.

evident, indicating that the ballistic deficit is reduced with the independent biasing ofthe back electrode.

After the measurements with X-ray the same SDD in the same set-up has been testedwith LaBr3:Ce and γ-ray source.

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(a) FWHM vs. Horizontal positions within the SDD for dif-ferent shaping times (back floating)

(b) Counts vs. Horizontal position within the SDD for dif-ferent shaping times (back floating)

(c) Counts vs. Diagonal positions within the SDD for differ-ent shaping times (back floating)

(d) Counts vs. Diagonal positions within the SDD for differ-ent shaping times (back floating)

Figure 4.44: Comparison of horizontal and diagonal positions within the SDD without the back bondingat different shaping times.

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(a) FWHM vs. Horizontal positions within the SDD for dif-ferent shaping times (back bonded)

(b) Counts vs. Horizontal position within the SDD for dif-ferent shaping times (back bonded)

(c) Counts vs. Diagonal positions within the SDD for differ-ent shaping times (back bonded)

(d) Counts vs. Diagonal positions within the SDD for differ-ent shaping times (back bonded)

Figure 4.45: Comparison of horizontal and diagonal positions within the SDD with back bonding forthree 0.5 µs, 1.5 µs and 6 µs shaping times.

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4.8. Array and Large LaBr3:Ce Scintillators

4.7.2 γ-ray characterization

The single SDD has been coupled to 9 mm diameter and 6 mm thickness LaBr3:Cescintillator. The SDD is biased with punch-through technique. Measurements herereported have been carried out at -20 °C. In Fig. 4.46, the energy spectrum of the 57Cosource measured with 3 µs shaping time is shown. The energy resolution measuredat the 122 keV peak is 5.6% FWHM, among the best results measured with LaBr3:Ceat this energy [64]. For the same scintillator module, the manufacturer quoted in thedatasheet a resolution of 7.3% FWHM measured with a photomultiplier tube. In thespectrum, a peak on the left of the 122 keV can be noted. After some investigations, weconcluded that this peak is most probably related to an imperfection of the scintillatormodule, maybe a crack in the crystal. In fact, a spectrum measured with a secondidentical module, here not reported because characterized by a worse energy resolution,did not show the secondary peak in the spectrum. In Fig. 4.47, the energy resolution

Figure 4.46: Energy spectrum of the 57Co source measured at -20 °C and 3 µs shaping time with theSDD (back floating) coupled to a LaBr3:Ce scintillator.

at 122 keV measured on the 57Co spectrum is reported versus the shaping time. Inthe same plot, also the conversion gain of the measurement (e-/keV) obtained with theSDD-LaBr3:Ce system is reported. A maximum conversion gain of 29 e-/keV has beenobtained. In Fig. 4.48, the energy spectra of a 57Co and a 137Cs sources measuredsimultaneously with the SDD LaBr3:Ce detector are reported. The shaping time is4 µs. A zoom of the 137Cs spectrum portion of the spectra is also shown, with anenergy resolution of 2.6% FHWM quoted for the 662 keV peak. Also in this spectruma secondary peak at the left of the 662 keV is visible. This can be also attributed tothe same crystal imperfection assumed to explain the secondary peak in Fig. 4.46 (stillvisible at the left of the 122 keV peak).

4.8 Array and Large LaBr3:Ce Scintillators

After the characterization of the single detector, also the array with 9 SDDs has beentested with the ASIC. Fig. 4.49 shows the pictures of the real ceramic carrier withpreamplifiers and detector (left) and also with the copper block for cooling. The X-ray

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Figure 4.47: Energy resolution @122 keV measured on the 57Co spectrum versus shaping time. In theplot, also the conversion gain of the measurement (e-/keV) is reported.

measurements with the parallel acquisition of nine channels is reported in Fig. 4.50.X-ray measurements are not usefully only for noise characterization but also becausethese data are used for the calibration of the system, based on offset and gain correctionsto the data acquired in order to align the noise peaks and the Kαpeaks. Fig. 4.51 reportsan example of nine channels aligned after gain and offset calibration. The calibrationallows also to estimate the equivalent number of electrons and therefore the e-/keVgain of the scintillator coupled to the detector. The same 9 mm diameter and 6 mmthickness LaBr3:Ce scintillator has been used coupled to the array, placing it over oneof the nine units. For this test in order to protect the array (the first tested) an optical-pad(1 mm thickness) is used as optical interface between the detector and the scintillator. Aresolution of 2.78% at 662 keV as been obtained with the complete readout composedby ASIC and DAQ. The measured gain of the scintillator is 25.5 e-/keV with 6 µspeaking time. This result is about 3 e-/keV less with respect to the one obtained with thesingle detector (Fig. 4.47, 6 µs peaking time can be compared with 3 µs shaping time);the difference can be explained with the different optical interface (optical pad insteadof only optical grease) is consistent with previous experiments of our research group.After the testing with the small scintillator the array has been tested with a 1" LaBr3:Ce(picture in Fig. 4.52). The test has been conducted in a climatic chamber because, atthat time, the mechanical structure was not yet ready. The performances obtained withthis scintillator and different sources such as 57Co ((peak at 122 keV)), 137Cs (peak at662 keV) and 60Co (peaks at 1.17 MeV and 1.33 MeV) are reported in Fig. 4.53 (only137Cs) and Fig. 4.54 (three sources). The same scintillator tested with PMT gives anenergy resolution of 3.2 % at 662 keV. The obtained results are very promising becausethe resolution at 662 keV is slower than the reference with PMT and it has been obtainedwith an array detector with an average leakage current out of specification (4 nA/cm2

vs the average 2 nA/cm2, we start testing arrays with worst performance) and the areaof the 1" diameter scintillator (1"= 2.54 cm) is not completely covered by the activearea of the detector (a square 24 mm x 24 mm). The not perfect geometrical efficiency

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Figure 4.48: Energy spectra of the 57Co and 137Cs measured simultaneously with the SDD coupled withthe LaBr3:Ce scintillator. The temperature is -20 °C and the shaping time is 4 µs. A zoom of the137Cs spectrum is included with the resolution measured at the 662 keV peak.

Figure 4.49: Real SDD module: a) SDD array mounted on the ceramic carrier and b) carrier with thecopper block (view from the bottom side).

Figure 4.50: Nine 55Fe spectra acquired with the SDDs array cooled at -20°C. The calculated averageENC is about 14.4 electrons rms with a minimum of 12.8 electrons rms. Peaking time is 2 µs.

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Figure 4.51: Spectrum in e- of the 55Fe source measured at -20°C. The calibration allow to estimate theequivalent number of electrons and therefore the e-/eV gain of the scintillator coupled to the detector.

Figure 4.52: Picture of the 1" scintillator. The material is hygroscopic and it is provided packed withTeflon (partially visible) around it (5 layers) and aluminium covering.

is also confirmed by the the equivalent number of e-/keV obtained 21 e-/keV lowerthan the one obtained previously, worsening the dominant contribution in the energyresolution, the statistical one. Also the electronics noise contribution is higher (becauseof the the out of specification leakage of this sample) but with only nine detectorsthe contribution is quite negligible (the ENC contribution depends on the square rootof the number of detectors). One of the advantages of the SDDs compared to PMTsis the good linearity versus energy. The linearity of PMTs tends to become worseat high energies due to internal saturation phenomena while an SDD based readouttake advantages at these energies (the amplification is linear). With the three sourcesmeasurements, a maximum non linearity in all the range of 0.6 % has been obtained

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Figure 4.53: Spectrum with 137Cs. Temperature is -20 °C and the peaking time of the analog shaper is6 µs.

Figure 4.54: Spectrum with three sources 57Co (peak at 122 keV), 137Cs (peak at 662 keV) and 60Co(peaks at 1.17 MeV and 1.33 MeV). Temperature is -20 °C and the peaking time of the analog shaperis 6 µs.

mainly due to the higher deviation at low energy (less than 0.1 % at the 60Co peaks).Delay in the mechanical design and realization and yield in the mounting and bondingprocedure of SDDs arrays (back windows is very thin and it can been easily damaged ifthe assembly is not done with extreme care) occur during the project, and at the momentof writing this thesis no test with larger (2" and 3") scintillators have not yet been made.The set-up anyway has been recently completed (Fig. 4.55) and spectroscopy tests withthe 2" scintillator are planned within some weeks (November-December 2013).

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Figure 4.55: Picture of the mechanical set-up that hosts the 2" scintillator under preliminary temper-ature tests. The plasic box has some holes for power supplies of Peltier stages, output signals andnitrogen input.

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CHAPTER5VERDI

VERDI is acronym of VErsatile Readout for Detector Integration, an ASIC designedfor the readout of different families of radiation detectors: SiLi, Ge, PMT, SDD, ecc...Aim of this chapter is the description of the third generation of this ASIC with emphasison the novelties in the design of the analog channel and the results obtained.

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Chapter 5. VERDI

5.1 VERDI-3 ASIC

A limitation encountered in the development of ASICs for radiation detectors is oftentheir specificity to a given detector, which makes the re-use of the same ASIC withdifferent detectors problematic if not impossible. In the last years, an integrated cir-cuit has been developed [77] to be used with a large variety of radiation detectors:Si(Li), nitrogen-cooled Germanium, Silicon Drift Detectors (SDDs), photomultipliertubes (PMT), ecc...These detectors have different characteristics, for instance the charge collected (elec-trons or holes) or the dynamic range which usually require a specific chip design.This Chapter is about the third prototype of VERDI, named VERDI-3 designed to im-prove the functionalities and the noise performance of its predecessors [78]. In particu-lar this new version is characterized by a novel analog channel that is presented in theseparagraphs. The circuit is designed again with 0.35 µm technology by AMS and thepower supply is ± 1.7 V.This project is a collaboration between Canberra Industries [79], Politecnico di Milanoand XGLab srl [80].Fig. 5.1 shows a blocks diagram of the designed ASIC.

Figure 5.1: Blocks diagram of the VERDI-3 chip.

VERDI-3, like its predecessors, implements eight complete readout channels, mainlycomposed by a charge preamplifier, a shaping amplifier, a baseline holder (BLH), apeak stretcher (PKS) and an output power buffer. Switches in the channel, provide atthe output the waveform of a specific stage: RC integrator output, output of the peakstretcher or output of the shaper. The RC output is useful for digital pulse process-ing of the signal, the peak detector output for amplitude measurements while the lastfor processing the shaper signal. The ASIC gives also the possibility to set the out-put as 8 independent channels or alternatively as multiplexed outputs on a single padfor random readout. All of these setting are controlled by the embedded SPI interfacethat allows the programming of the fundamental parameters of the electronics: gain,

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5.1. VERDI-3 ASIC

polarity of the detector (and therefore of the chain), shaping time, preamplifier com-pensation, ecc.. Two modes of operation are present: Gamma Camera mode (Fig. 5.2a) and Spectroscopy mode (Fig. 5.2b). In the first one the ASIC is used with multipledetectors at the same time providing a trigger signal on significant events on all eightchannels. This feature is useful when interfacing VERDI with segmented detectors forinstance for energy or position reconstruction of gamma events with continuous scin-tillator, as described in Chaper 4.The Spectroscopy mode uses independently the eight channels. Each channel repre-sents an independent acquisition with its individual trigger threshold. Both operationmodes can have the two possible types of outputs: eight parallel buffers or multi-plexed output. The configuration with eight parallel buffers is particularly suitable forspectroscopy mode while the multiplexed output is more indicated for gamma-cameramode. With the multiplexed output the unused buffers are switched-off for power sav-ing.

(a) Gamma Camera mode, example with a continuous scintillator readout by adetector array, all the detectors should be read.

(b) Spectroscopy mode, all the charge is collected by a single detector.

Figure 5.2: Gamma and Spectroscopy mode. In the first case (a) the outputs have to be read all together,in the second (b) the channels are rad independently.

In Fig. 5.3, an example of the custom interface with JFET to be used for a givenradiation detector. The remaining part of the preamplifier is integrated inside the ASICand it provides the low noise amplification and the programmable signal to an externalreset device.

The SPI is the same of Chaper 3 with a 128-bits register that stores all the internal

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Figure 5.3: Front-end connection. Outside the dashed box, the specific front-end for the detectors, inthis case the widespread readout with a discrete JFET with a feedback capacitance.

settings .A ROM memory is also included to use the ASIC without the SPI program-ming interface (in this case the settings are fixed).

The charge preamplifier is designed to be coupled with a large variety of exter-nal JFETs and feedback capacitors in continuous or pulsed reset regime. The JFETtransconductance and the input capacitance ranges respectively from 2 mS to 45 mSand from 0.1 pF to 39 pF. The external feedback capacitance CF ranges from 50 fF to 1pF.In order to provide stability on a such wide range of JFET and CF parameters, an in-ternal programmable compensation system has been adopted. The preamplifier canchange its gain by a factor 8 and its bandwidth by a factor 4.5, simply acting someswitches controlled, also in this ASIC, through an SPI interface. In Fig. 5.3 the hybridcharge preamplifier is shown with a simplified blank blocks for the gain and bandwidthdivider. The gain divider is made by current mirrors (with different factors) while forthe compensation, capacitors of different sizes are connected or disconnected. Thepreamplifier supports both mostly adopted readout systems: pulsed reset or continuousreset. The IN_SH pad (Fig. 5.2) allows the use of an external pole-zero network in thecontinuous reset configuration. The same pad allows also to skip the preamplifier anduse the remaining part of the ASIC with external preamplifiers, in that case the internalCSA is disconnected and switched-off.The charge amplifier is almost the same of the first two versions and only some minoroptimizations have been done. The remaining part of the analog channel, on the con-trary, has been deeply modified.

5.1.1 Design: Analog Channel

The output of the charge amplifier is connected to a first RC integrator that is the firstcell of the shaper filter. The shaper, is a CR-RC6 (see Chapter 2) with seven coincident

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Figure 5.4: Internal structure of the charge preamplifier, the input MOS are the 5 V option of the tech-nology in order to work with higher voltages of the JFET.

real poles. The choice of a filter with real poles instead of one with complex polesis because with a simple implementation based on cascade of RC cells, it is possibleto have a wide set of gains and characteristic times required for the wide range ofoperation of this ASIC. In this case of CR-RC6, it is convenient to use as reference timethe shaping time, instead of peaking used in Chaptes 3 and 4.The designed shaping times and gains are reported in Tab. 5.1 and Tab. 5.2. The gainis referred to the amplitude at the input of the shaper to have the maximum value of 1.5V at this output.The overall gain depends on the feedback capacitance of the charge amplifier or on thegain of an external preamplifier. The shaper can work with both positive and negativesignals at its input setting the polarity of the channel (one bit in the SPI). In the case ofnegative input, a further stage with -1 gain is connected within the chain. In total thereare 120 gain-shaping time combinations available for each polarity.

0.25 µs 0.5 µs 0.75 µs 1 µs 2 µs 4 µs 6 µs 8 µs

Table 5.1: Shaping times of the filter. The peaking time is six times the shaping time value (Chapter 2).

20 mV 30 mV 50 mV 75 mV 95 mV 105 mV 125 mV 175 mV195 mV 205 mV 225 mV 250 mV 270 mV 280 mV 300 mV

Table 5.2: Gains. The value corresponds to the amplitude at the input of the shaper that gives themaximum signal at the output, smaller is the value, higher is the gain.

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Fig. 5.5 shows a simplified view of the the analog channel.Shaper

Figure 5.5: Internal structure of the analog channel, the switches are necessary for the different config-urations.

In the previous versions of this ASIC the shaper was designed with a cascade of RCcells with the resistance synthesized with ICON cells [81]. This approach is very in-teresting for the design of poles at low frequency (i.e. high equivalent resistors) but itsuffers in the realization of the poles corresponding to the short shaping times (with ourtechnology < 1 µs) due to limited bandwidth of the loop. In order to extend the rangeof gains and shaping times, the new shaper is designed as cascade of RC cells whereresistors and capacitors are real passive components of the technology.

The first cell (Fig. 5.6a) is made with a T-structure similar to the one introduced inthe preamplifier of Chapter 3, here the feedback element is no more a MOS but a realresistor. This structure allows to simplify the design, changing the value of C, Cin, Rfand the ratio R2/R1. The gain is set changing the ratio Cin/C while the time constantchanging Rf and the ratio R2/R1. With this approach the first cell is very complicated,in our design 40 R and C passive components and 50 switches (some single mos, somepass transistors), but the successive stages can be very simple (Fig. 5.6a) and modifiedonly for the time constant. The high number of switches is controlled with a customdesigned digital logic. Also in this case the required value for the component is realizedwith the smart sum of series resistors and parallel capacitors in order to reduce the areaoccupancy. The area occupancy of this shaper is almost the same of the old versions.

BaseLine holder.The baseline holder circuit is a modified version of the one introduced in Chapter 3,but in this case the holding capacitor is not fully integrated. The BLH has the role to

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(a) Firt cell. All the components are modified for the synthesis ofall the time constants and gains.

(b) Successive cells, simple inverting integrator.

Figure 5.6: Shaper cells, a) first cell b) six successive stages.

compensate a very wide range of detector leakage current, from hundreds of fA to tensof nA for all the shaper gains, the required pole is therefore obtained with a structuresimilar to Chapter 3 but with a discrete 10-100 nF off chip capacitor (eight PADs arededicated to these connections). The BLH should work with both the polarities of thechannel, for this reason its output stage is modified in order to sink or source the currentin the virtual ground of the first stage (Fig. 5.7 reports the modification of the outputstage, the part not shown is the same of the BLH explained in Chapter 3). Accordingto Fig. 5.5 the output of the analog channel can be taken after the first RC stage, in thiscase the BLH input is connected to the output of the first cell and the baseline holdingoccurs on this waveform and not on the shaper output.

Figure 5.7: Schematic of the output stage of the BLH, the two switches (in red) can be opened or closedin order to modify the current direction.

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Complete ASIC.The remaining parts of the ASIC have been maintained from previous versions, thecomplete ASIC layout has been designed pin to pin compatible with old versions.

Figure 5.8: Layout of the chip. Total area 12 mm2, 103 PADs.

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5.2. Testing and Results.

5.2 Testing and Results.

The ASIC has been tested focusing on the novelties of the third version. In Fig. 5.9the boards used for the testing, on the left the designed "analog board" with the ASICin a 128 pin ceramic carrier, on the right the "digital board" for programming and dataacquisition, provided by Canberra Inc. This version of the analog board does not onlyhosts the chip but it also hosts two T-08 sockets and voltage references for directlytesting SDDs. Other versions of the analog board has been designed for different appli-cations. The analog output is connected with a MMCX compatible cable to an ADC onthe digital board for data acquisition. The digital board is connected to a host PC viaEthernet connection. A screenshot of the PC software used for programming VERDIand data acquisition is shown in Fig. 5.10.

Figure 5.9: Boards for testing and acquisition. On the left the "analog board", on the right the "dig-ital board" segmented with flexible layers. The white cable connects the output of the ASIC to onecommercial ADC.

The ASIC has not shown troubles and it has been tested with an arbitrary waveformgenerator for the characterization of the analog channel. Fig. 5.11 shows waveformsat the output of the analog channel with possible configuration, output of the shaper,output of the first stage and output of the peak detector.

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Figure 5.10: Screenshot of the software (Canberra) with ASIC setting.

(a) Output of the shaper with positive polarity, five shortestshaping times.

(b) Output of the first integrator with negative input.

(c) Output of the shaper with negative input, five longesttimes.

(d) Different gain settings with fixed shaping time.

(e) Output of the peak detector. In pink the signal"stretched", in blue the digital control signal of the peakdetection.

Figure 5.11: Output of the analog channel with different settings.

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5.2.1 Tests with detectors

The first test conducted on the ASIC with a detector has been done with a 25 mm2 SDDsample already tested with previous versions of the ASIC. This detector (provided byCanberra in a T-08 package) has a discrete component JFET as first amplifier elementand therefore the ASIC is used with the integrated charge amplifier. The VERDI con-figuration is schematized in Fig. 5.12.

Figure 5.12: VERDI configuration with an SDD+JFET.

A small Peltier inside the T-08 package is used to cool the detector. The SDD hasbeen irradiated with a 55Fe source and spectroscopy measurements have been carriedat different temperatures at all the available shaping times. The JFET transconductanceis 2 mS and the feedback capacitance value is about 50 fF. The gain is set to have 0-40keV energy range. Fig. 5.13 shows the resolution performance at the MnKα peak withSDD cooled to -25°C, measured at different shaping times of the internal shaper, andthe results obtained with the previous version with the same detector in the same con-ditions. The results is now equal to what can be achieved with the same detector and abench NIM shaper.Fig. 5.14 shows an energy spectrum collected by the same experimental set-up with the

Figure 5.13: Energy resolution at -25 °C and comparison with the first version of the ASIC. The secondversion differs from the first only for some peripheral digital circuit.

SDD kept at room temperature. Due to the high leakage the best performance has beenobtained at the shortest (0.25 µs) shaping time. The 25 mm2 SDD has been also testedwith a 241Am a digital pulse processor connected to the output of the charge amplifier(5.15a). The -1 gain stage is used to have a positive signal at the output. A resolu-tion of 436 eV FWHM has been obtained at the 13.9 keV line with a digital filter with

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Figure 5.14: Energy resolution at room temperature. The FWHM is 351.2 eV corresponding to an ENCof 39.1 e- rms (shaping time 0.25 µs).

rise time 0.4 µs at room temperature (5.15b). The feature of the ASIC to be used with

(a) VERDI configuration, the output is connected to a digital pulse processor.

(b) 241Am energy spectra at room temperature. The energy resolu-tion is 436 eV at 13.9 keV.

Figure 5.15: VERDI coupled to SDD with a different readout based on digital pulse processing of theramp.

various detectors has been evaluated with tests by the partner in the project, Canberra

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Industries. A first test with a germanium detector has been conducted with VERDIconfigured with the output of the first integrator provided to a digital pulse processor(Fig. 5.16a). The input detector has an active volume of 34.2 cm2, at the temperature of70 K and irradiated with a 57Co γ-ray source. The detector has an output capacitanceof 50 pF, the input JFET has a gm of 14 mS and the energy range is from 3 keV to 10MeV. The energy resolution as function of the digital rise time filter is reported in Fig.5.16b. In this case the block with gain -1 is not connected. A very similar readout has

(a) VERDI configuration, the RC waveform is connected to a digital pulse processor.

(b) Energy resolution as a function of the digital filter rise time forGe detector irradiated with 57Co source.

Figure 5.16: VERDI coupled to a Ge detector.

been used with Si(Li) detector irradiated with 55Fe source. The detector is at 70 K andthe area is 1.1 cm2. The output capacitance is 2 pF and the JFET has a gm of 11 mS. Inthis case the output of the first cell is buffered into a digital pulse processor.A further test has been done with a PMT (1" R11265-200 by Hamamatsu) connected toan external preamplifier and than to the input of the VERDI shaper bypassing the inte-grated charge preamplifier (Fig. 5.18a). The scintillator used is 1" cylindrical SrI2:Eu.Fig. 5.18b, the measured energy resolution is 3.7% at 662 keV (137Cs), the energyspectra with a comparison with a commercial discrete components acquisition systemis shown in Fig. 5.18b. The shaping time used is 8 µs while in the other acquisitionsystem is 12 µs. This ASIC is now used by Canberra Inc. in experimental set-ups indifferent facilities, Meriden (USA) and Olen (Belgium) and under consideration forcommercial applications, especially for portable instruments where compactness andlow power are mandatory.

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(a) VERDI configuration, the RC waveform is connected to a digital pulse processor.

(b) Energy resolution as a function of the digital filter rise time forSi(Li) detector irradiated with 55Fe source.

Figure 5.17: VERDI coupled to a Si(Li) detector.

(a) VERDI configuration bypassing the integrated preamplifier.

(b) 137Cs energy spectra with a comparison between a commercialsystem and the VERDI-3 ASIC, the energy resolution is 3.7%in both cases.

Figure 5.18: VERDI used as readout electronics for PMT coupled to a scintillator.

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CHAPTER6Other Projects and New Developments

This chapter describes other activities developed in parallel to the ones presented in theprevious chapters, in particular Chapter 4. The applications are briefly summarized justto give the idea of why these developments have been conducted and analyse with acritical approach the reported results.

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Chapter 6. Other Projects and New Developments

6.1 Introduction

This chapter reports a list of projects, with common parts with what I descried in thisthesis, in which I was involved. They are mainly applications of the new detectors (sin-gle and array) developed for the ESA project (Chapter 4) for already ongoing activities(SIDDHARTHA and GAMMA) or preliminary studies for future projects (INSERT).The activities here presented have been carried out in parallel with the main projectsduring the last year. These projects are important because their future developments aretoward an evolution of many concepts seen in this thesis included the concept idea torealize an unique ASIC that includes all the peculiarities required for the wide range ofapplications of SDDs, an end point of all the ASIC developments realized during mydoctoral thesis and in general by our research group before me.

6.2 SIDDHARTA

This section presents the application of the SDDs described in Chapter 4 for their usein the future SIDDHARTA-2 experiment. The SIDDHARTA experiment used X-rayspectroscopy of the kaonic atoms to determine the transition yields and the strong inter-action induced shift and width of the lowest experimentally accessible levels [82]. Forfuture upgrade of the actual experimental set-up and new type of experiments, calledSIDDHARTA-2, a new development of SDDs is ongoing for the replacement of theactual technology based on SDD with integrated JFET. The SIDDHARTA experimentis a collaboration of different research centres and universities: LNF-INFN (Frascati,Italia), Stefan Meyer Institute fur subatomare Physik (Vienna, Austria), University ofTokyo (Japan), Technical University of Munchen ( Germany), Politecnico di Milano,and others, that took data in 2009-2010 from the DAΦNE e --e+ collider (at LNF Lab-oratori nazionali Frascati INFN) obtaining very good results [82] [83], for instance theprecision measurement of the shift and of the width of the Kα line of kaonic hydrogen.Fig. 6.1 shows a picture of the detector plane of the first experiment (section) with thestacked readout electronics, in the complete structure the detectors are 144 with 1 cm2

area each, in monolithic arrays of 3 units. The actual set-up is planned to be upgradedduring 2014 and therefore some studies are ongoing for improving some limitationsof the first version. The electronics of the first project worked very good but it showedsome intrinsic limitations due to the presence of the input JFET inside the SDD that canbe overcome with a readout based on CMOS preamplifier. A first limitation is the im-possibility to run the set-up during injections, due to the latch-up on the JFET, inducedby the very high background during injections. The recovery time from this latch-upneeds the reset of a detector voltage and this procedure lasts seconds. This effect wasnot previewed in the design of the biasing and readout electronics since when the elec-tronics of SIDDHARTA was designed the expected background during injections wasmuch smaller. A second limitation is the working temperature of the SDDs arrays thatwith JFETs is limited to 120-130 K (in SIDDHARTA-1 they work at 160 K) while withCMOS can be extended to few tens of K. The possibility to use the detectors with lowertemperatures is very useful for physicists to improve the efficiency of the machine (forinstance moving the detectors closer to the targets that in this experiment is very cold,few K) or for new experiments that go beyond my competences. Low temperature op-erations is needed in SIDDHARTA-2 to speed-up the drift time that is important for the

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Figure 6.1: Picture the detector arrays within the SIDDHARTA-1 instruments. The readout electronicscan be seen stacked behind the detectors.

timing of the experiment in order to reject the high background. A further advantagesof SDD with CMOS readout is that the global cost is significantly lower and, with alower budget, a bigger area can be covered.

The first limitation requires tests (radiation hardness for instance) in dedicated facil-ities and their are planned for the future. The second one, on the contrary, can be testedin our laboratory using SDDs inside a vacuum chamber with a cryostat. The systemused for the test was available from old projects [84] and after some mechanical andelectrical modifications the single SDD has been tested up to the limiting temperatureof the cryostat (model RICOR K535 air cooled), 50 K. Pictures of the vacuum chamberand cryostat with a proper copper frame that hosts the SDD ceramic carrier (the sameused in Chapter 4 for single detector characterization) are shown in Fig. 6.2. The cop-per frame is directly in contact with the cryostat cold tip.

This section is mainly about measurements with X-rays (55Fe source) at cryogenictemperatures. The preamplifier version is the same used in Chapter 4 with a reducednumber of PADs. A first test at different temperatures has been done in order to un-derstand if the circuit works at that temperatures. The resolution trend function of theshaping time of the external acquisition system sweeping the temperature from 240 K to50 K (minimum possible), is reported in Fig. 6.3. The energy resolution improves dueto the expected reduction of SDD leakage current but also thanks to the increase of thefirst MOSFET transconductance. An energy resolutions below 125 eV has been mea-sured with temperature below 100 K. An example is shown in Fig. 6.4 with a FWHMof 124.7 eV at 50 K with 2 µs shaping time. The visible worsening (with respect to thenoise contribution) at short peaking time for temperature above 160 K is mainly duethe ballistic deficit occurring in this quite big area single small anode detector. At lower

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Figure 6.2: Picture of the vacuum chamber with the cryostat (black). The SDD under test is connectedto a copper frame directly on contact with the cryostat cold tip. Top left is the vacuum chamber withthe cryostat on the top, top right is the internal of the chamber with the support for the vacuum 55Fesource. Bottom left is a cryostat picture while bottom right is a detailed view of the cold tip with theSDD mounted in a proper ceramic carrier.

Figure 6.3: Energy resolution of the 64 mm2 (8 x 8 mm) SDD coupled with CUBE preamplifier at theMn-Kα line for different temperatures.

temperature the drift time of the charge in the SDD is reduced thanks to the increase ofthe electron mobility in the silicon, the effect is the reduction of the ballistic deficit and

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Figure 6.4: Energy resolution of the 64 mm2 SDD at the Mn-Kα line at 50 K, shaping time 2 µs (uncol-limated source).

the reduction of the tail in the spectra with a consequent improvement in resolution.This is also true and evident when the biasing of the detector is made with the punch-through between last ring and the back electrode in the opposite side. The concept ideafor the upgrade of the instrument is schematically depicted in Fig. 6.5. The total activearea is 200 cm2 with 36 SDDs monolithic arrays equal to the ones presented in Chapter4 for a total 324 readout channels. The array modules from Chapter 4 are available only

Figure 6.5: Drawings of the possible upgrade of the detectors for the SIDDHARTA experiment. On theleft the a section view, on the right the complete detection system. The modules here shown are thesame of Chapter 4. Courtesy of SMI-ÖAW.

without the possibility of the independent back bonding and therefore tests with singledetectors with bias made by punch-through technique have been done. As mentioned,the increase of the electron mobility in the silicon, reduces the effect of the higher col-lecting time when the SDD is biased with this method. Below 160 K the performanceof similar detectors are practically the same (160 K measurement in Fig. 6.6).

One of the main peculiarity required by the application is the stability of the peakspectra during all the data-taking (< 1), also test to verify if this new SDD satisfythis requirement have been performed. For this stability test the system has been keptworking for many days, acquiring signals for long time periods. Tab. 1 reports the

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Figure 6.6: Comparison of the measurements with SDDs biased with two techniques at 160 K. Theresults are practically the same.

results of measurements with different durations.From this results this new SDD seems matching the requirements but this test should

Measurement Time Energy Resolution Mn-Kαcentroid peak Maximum differenceMn-Kα[eV] [ADC channel]

72h 126.8 2277 0.5824h 126.7 2278 0.1520h 126.8 2280 0.73

Table 6.1: Measurment for peak stability estimation, the temperature is kept to 100 K and the rate is 1kcps.

be redone with the readout ASIC that inevitably will be redesigned for this application,(the ESA ASIC does not match the sparse readout required by this application withinformation of the channel that gives the trigger).

6.2.1 Improvements of CUBE preamplifier

In parallel to test with vacuum chamber a new generation of CUBE (with mainly anoptimization of first transistor) has been tested obtaining improvements. The measure-ments reported in Fig. 6.7 are some of the most relevant obtained in the preliminarytests with 10 mm 2 round shaped SDDs. The choice of round shaped used instead ofthe squared ones in order to reach the lowest possible overall leakage current in set-upwhere Peltier is the cooling system (more flexible set-up for an early characterization).A relevant 126.4 eV results has been obtained with the shortest shaping time available250 ns.The next step of this development is the test of the array in the vacuum chamber, the

mechanical set-up has been recently completed and tested with the same ASIC used forthe ESA project are planned for the future.

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6.3. GAMMA

(a) The best energy resolution obtained at 1 µs (b) The energy resolution obtained with a very short shaping timeof 250 ns, 6-7 equivalent ev better than the previous version.

Figure 6.7: 55Fe source spectra with an improved version of CUBE preamplifier with 10 mm2 roundshaped SDD.

6.3 GAMMA

In nuclear physics research and in gamma spectroscopy, position sensitivity at highenergies (>511 keV) could be extremely useful to reduce the Doppler broadening ef-fect, for example to study the collective properties of nuclei far from the stabilityline [85–87]. When a radioactive source moves at high or relativistic velocity or thesource-detector distance decreases, the emitted γ-rays are subject to an apparent en-ergy shift, in analogy to acoustic Doppler, as depicted in Figure 6.8 [40] [88]. TheDoppler broadening can be mathematically described as follows:

Eγ = E0γ

√1− v2

c2

1− vccos(θ)

(6.1)

where:

- v is the source velocity;

- c is the speed of light;

- θ is the angle between the particle and γ-ray trajectory;

- E0γ is the γ-ray energy;

Information about the γ-ray point of interaction inside the crystal could be used in con-junction with particle velocity to determine the angle θ and thus to reduce the Dopplerworsening effect, recovering the intrinsic performance of the detector. Particle velocityis measured with another detector in the system with best performances in terms oftiming resolution. For this challenging application an ideal detector should have thefollowing features:

• high spatial resolution (1÷ 10 mm) to detect different interaction points with highaccuracy;

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• good energy resolution;

• high detection efficiency (mainly guaranteed by thick scintillators);

• timing performances to reject the background.

Spatial resolution is worsened with high energy γ-ray sources due to the increasingweight of the Scattering absorption mechanism with respect to photoelectric compo-nent. In recent years [89], good results have been obtained with the HI-CAM gamma

Figure 6.8: When a radioactive source moves at high or relativistic velocity, the emitted γ-rays aresubject to an energy shift. In other words, at high v/c ratios γ1 and γ2 have no more the same energyand the overall spectrum has a broadening. An Anger camera could detect the position of interactionin the crystal, proving an implicit information about θ1 and θ2, opening thus the way to a possibleenergy correction.

camera coupled to CsI tick scintillator and a new development is ongoing in order tohave position sensitivity with the system presented in Chapter 4 and LaBr3:Ce scintil-lator. A first test have been conducted with a collimated (1 mm collimator) 137Cs beamirradiating the 1" LaBr3:Ce scintillator in different spots with 5 mm steps, graphicallyshown in Fig. 6.9. Unfortunately one unit was not more working after the scintilla-tor mounting (blue X in figure). The reconstructed point of interaction are shown inFig. 6.10 with, for comparison a white X in the estimated irradiating spots. The resultsare promising because obtained with one detector not working (very useful for imag-ing) and for the configuration of the scintillator. The scintillator in fact is optimized forspectroscopy with Teflon around it, that makes difficult the reconstruction at the borders(full reflections on the walls), and it has a complicated geometry for imaging, thicknessequal to the diameter and cylindrical shape. The algorithm used in the reconstruction isthe centroid method with baseline subtraction [90]. Future applications are the use of2" and 3" LaBr3:Ce and the same detector array with different scintillators.

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6.3. GAMMA

Figure 6.9: Detector plane with diameter of the 1" scintillator and in grey the irradiation spots, 5 mmstep each.

Figure 6.10: Reconstructed points and reference positions (grey). The reconstruction of the points isdone with the centroid method with baseline subtraction. Reconstructions by P. Busca.

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6.4 INSERT

The last project here reported is in the field of medical imaging and is about the de-velopment of a new multi-modality imaging tool under development in the frameworkof the INSERT (INtegrated SPECT/MRI for Enhanced Stratification in Radio-chemoTherapy) project, supported by the European Community under the FP7-HEALTH Pro-gramme. The final goal of the project, started in spring 2013, is to develop a customSPECT apparatus, that can be used couple to commercially available MRI systems, forinstance 3 TESLA medical MRI with 59 cm bore diameter or preclinical with 20 cmbore. Concept of the finals system is reported in Fig. 6.11. INSERT is expected to

Figure 6.11: Principle of the integrated MRI/SPECT instrument for the INSERT project.

offer more effective and earlier diagnosis with potentially better outcome in survivalfor the treatment of brain tumors, primarily glioma. Two SPECT prototypes will bedeveloped, one dedicated to preclinical imaging, the second one dedicated to clinicalimaging. Fig. 6.12 shows two drawings of the possible systems, the preclinical and theclinical. SPECT could be attractive as an alternative to PET in many preclinical studies

Figure 6.12: Drawings of the preclinical (left) and clinical systems (right).

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6.4. INSERT

as well as in clinical trials, with potentially better spatial resolution and the possibilityfor simultaneous use of multiple radionuclides for instance 99mTc (140 keV), 123I (159keV), 111In (171/245 keV). The basic building block of the SPECT detector ring is asmall 5 cm x 5 cm gamma camera, based on the Anger architecture [91] with a con-tinuous scintillator. The presence of very high magnetic fields imposes to replace thetraditional PMTs used in SPECT systems with monolithic silicon sensors. Two solu-tions are under study for the scintillator readout, one based on SDDs the other one basedon Silicon Photo Multiplier (Sipm). Both solutions are therefore under study (by peoplein our research group) to evaluate their performance in terms of field of view (FOV),spatial and energy resolution [92]. From preliminary simulations the performance ofSDDs seems superior (especially for energy resolution) but the use of SDD has rele-vant engineering problems to be considered, for instance they require to be cooled to-20 °C to reduce leakage noise contribution, very complicated inside an MRI whereonly some materials can be used for compatibility problems with very high magneticfields. Sipms, on the contrary, are suitable to be used at room temperature (or moder-ately cooled to +20 °C).With SDDs the 5 cm x 5 cm module can be made with 4 of the arrays of 9 SDDs eachdeveloped for the ESA project. Fig. 6.13 shows a 3D drawing of the possible singlemodule (left) and of two modules side by side (left). The energy resolution is a crucial

Figure 6.13: 3D drawings of the possible detection head module with 4 arrays each for the eventualimplementation with SDDs. On the left the single module with active area 5 cm x 5 cm, on the righttwo module side by side.

aspect because for multi-tracers identification a resolution about 10-11% is mandatoryand for this reason the scintillator choice is fundamental. In the first part of the projectexperimental characterizations are ongoing for the estimation of the energy resolutionwith different scintillators at low energy (122 keV peak available with 57Co γ calibra-tion source.) Two experimental set-ups are working in parallel for characterization forboth Sipm and SDD. In particular, the SDD set-up is the same used for the character-ization of the single 8x8 mm SDD of Chapter 4. The scintillators tested are CsI:TI,GAGG:Ce and LaBr3:Ce (used as reference, can not be used because is very expen-sive).The result of the test with 8 mm diameter 8 mm thickness cylindrical CsI(TI) scintil-lator (that most probably will be the final choice) are reported in Fig. 6.14 (-20 °Cwith 57Co source) and a key point of this and next section. The CsI scintilaltor has

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a main drawback used with detectors that are cooled to reduce noise contribution, itsdecay time constant increases decreasing the operating temperature [71]. This resultsin a very high ballistic deficit effect with our quite big area detector with single smallanode and therefore a longer integration time is required to have the maximum gain ofthe scintillator coupled with the SDD (right part of Fig. 6.14). This imposes a newASIC design to match the best peaking time for this scintillator (longer that ESA-ones,rate events should not be a problem because expected rate is less than 10 kcps on thesingle module) also with a proper number of channel (for instance 36 for the readoutof 4 arrays). Fig. 6.15 shows the energy resolution as function of the peaking time.

Figure 6.14: Measurements with SDD coupled with CsI(TI) scintillator at -20 °C with 57Co source.On the left the energy spectrum with a resolution below 8% while on the right the scintillator gain(e-/keV) function of the peaking time of the shaper filter.

In the case of the single detector the noise contribution is negligible, but this is nottrue when more detectors are used, the ENC contribution to the energy resolution de-pends on the square of the number of SDDs. For this reason measurements with the 9SDDs array are ongoing, in this case the detectors are read by the ESA ASIC, that hasa maximum peaking time of 6 µs, not the best with CsI(TI). In this case the scintilla-tor is again CsI(TI) with base 2.6 cm x 2.6 cm and 1 cm thickness. One of the main

Figure 6.15: Resolution as function of the peaking time of the filter with the 8 mm cylindrical CsI(TI)scintillator coupled with a single SDD at -20 °C. Long peaking times allow to compensate the ballisticdeficit increasing the e-/keV and reducing the Poisson contribution.

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6.5. Towards new readout ASICs

task of the INSERT project is the compatibility of the standard electronics developedfor the ESA project, in particular the ASIC, with very high magnetic fields. Prelimi-nary tests have been conducted at Ospedale San Raffaele (Milano) with a 3 T clinicalMRI and our ASIC. This preliminary test suggests that the static high static field, usingproper materials, is not a problem, but we noticed some interferences with RF signalsof the machine, probably, due the long power supply cables that act as antenna for RFsignals [93]. Future developments are scheduled with a best shielding of the systemboth in laboratory with bulk current injection tests (BCI, [94]) for the emulation of RFdisturbances both again with real MRI instruments (3 T, 7 T and 9.4 T).

6.5 Towards new readout ASICs

The three projects presented in this chapter are ongoing activities and, a new generationof ASIC should be realized in the near future taking advantages of the ASICs designedduring my doctoral activities. The SIDDHARTA-2 project requires an ASIC with adigital interface compatible to old chip versions with sparse readout logic and infor-mation on the channel that gives the trigger. This future chip requires also, as previousASIC for this project [95], a pile-up rejector circuit, because even if the number of validevents during a data taken is very low it is necessary to discard background. The projectis dedicated to X-ray detection and the analog channel should be optimized in terms ofcharacteristic time and gain of the filter for the optimum noise. The GAMMA andeventually the INSERT projects require contrariwise a readout of the events generatedin a continuous scintillator and therefore a readout that is able to read all the channelsof the detector matrix. The optimization of the analog channel should be done in agree-ment with the scintillator used because the best time of the filter in terms of electronicnoise is not (almost never) the optimum for the γ-ray energy resolution due to the ef-fect of the ballistic deficit. For instance the optimum peaking time of the shaper forγ-ray spectroscopy with CsI:TI is a trade-off of different aspects included overall noise(depending on the number of detectors) and ballistic deficit (depending on detector sizebut also on the behaviour of the scinitillator in temperature). SDDs found applicationsin very different fields with different requirements in the readout electronics, but:Why not an unique ASIC for all the applications?This can be an interesting evolution of the ASICs designed in this thesis, taking someparts from each of them:

- the pile-up rejector circuits from the HTRS project maybe with a filter with peak-ing time lower to fully exploit the advantages of the CMOS CUBE preamplifier(see last part of the section SIDDHARTHA of this chapter);

- the general structure of the ESA chip with improved dynamic range and powersupply 0-3.3 V;

- the multiple re-configurable options and the shaper concept with a wide range ofgains and times from the VERDI-3 chip;

An interesting evolution, since the preamplifier and the main ASICs are separated, tokeep the AMS 350 nm, that is characterized by a very low 1/f noise coefficient (Af),only for the preamplifier and to use a more scaled technology for the main ASIC taking

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advantages of the benefit in terms of bandwidth and power consumption. A furtheradvantage of the 350 nm technology is to be low cost, very important in systems witha high number of channels (one preamplifier per channel). Another possible evolutionof these ASICs designed is the obvious, but time consuming, design of an integratedADC, in two possible configurations, or one (after an analog multiplexer) per ASICwith quite high requirements in terms of speed (for HTRS-like applications with highrates) and high ENOB (> 11 bits for ESA-like applications) hard to be designed in350 nm technology or one per channel (with lower have lower conversion rate but withmore stringent constraints in terms of area occupancy). A concept blocks diagram ofan ASIC to be coupled with the 9 SDDs array for the realization of a compact andmodular detector and electronics system for X and γ-ray applications (from Mcps X-ray spectroscopy with Synchrotron light to basic element for gamma cameras in medialimaging) is shown in Fig. 6.16.

Figure 6.16: Block diagram of an ASIC to be coupled to the 9 SDDs array for the realization of modulardetector with electronics for different applications.

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CHAPTER7Discussion and Conclusions

The thesis is not focused on a single topic but to a wide collection of projects in whichdesigned ASICs have found applications, in the field of X and γ-spectroscopy.The first part of this dissertation describes the development of an integrated circuitdesigned for possible X-rays astronomical observations with Silicon Drift Detectors(SDD).All the designed has been conducted reducing as much as possible the dead time in thedetections and acquisition electronics chain. In particular, with respect to the reportedliterature, an innovative analog channel with high order shaping filters and high effi-ciency pile-up rejector circuit and logic has been discussed and designed in a 350 nmtechnology. The pile-up rejector takes advantages of the symmetrical shape of the out-put response of the filters but can be, in general, applied to any shaping filters becausethe working philosophy is based on programmable time windows that control differentphases of the peak detection mechanism.Results obtained have been very interesting, absolutely at the state of art for X-rayspectroscopy in terms of both energy resolutions and electronic processing efficiency.Rarely in literature the best energy resolutions obtained are reported with the indicationof the real input count rate that is instead an important parameter. The system designedwith a CMOS preamplifier (developed in parallel to the activity) allows to reach a bestenergy resolution of 126 eV on the Mn-Kα line with input count rate higher than 100kcps or 144 eV at 800 kcps in a single channel.

SDDs have demonstrated in the last decade to be competitive devices for the readoutof scintillators compared to conventional photodetectors (for instance photomultipliertubes, PMTs), due to their high quantum efficiency (> 80%) and low electronic noise(guaranteed by the single small collecting anode).

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Chapter 7. Discussion and Conclusions

In this framework of the use of SDDs as detectors of scintillation light, in collaborationwith the European Space Agency (ESA) and the Bruno Kessler Foundation (FBK), aproject has started (and still ongoing) for the investigation of an alternative to PMTsfor the readout of large (1", 2" and 3") LaBr3:Ce scintillator for future interplanetaryapplications.The system, presented in Chapter 4, has been designed with particular attention to allthe components in order to obtain modularity and compactness.The detection head is not unique for all the scintillators but it is based on the assemblyof single fundamental detector modules composed by an array of nine SDDs with ac-tive area of 24 mm x 24 mm (suitable alone for the 1" scintillator).Each SDD array is packaged in a single structure composed by the detector itself, theceramic carrier and a copper block that has the same width as the sensor chip and ce-ramic and it is screwed to a common aluminium base cooled by Peltier stages. Thedesired active area can be realized placing side by side the appropriate number of mod-ules.In case of 2" scintillator four modules are used while for 3" nine modules are required.The module is composed by squared 8 mm x 8 mm detectors that, in the single unit,has been deeply tested for noise and ballistic deficit estimation. The ASIC designed isbased on 27 analog channels with a single multiplexed output and it is characterizedby various functionalities (for instance multiple peaking times 2 µs, 3 µs, 4 µs and 6µs, or multiple gain settings) programmable with a custom designed SPI interface. TheASICs can be used alone for the readout of the 1" or in combination with another oneor other two for the readout respectively of 2" and 3". Each ASIC is directly bondedon a dedicated PCB and the required number of these board are connected to anotherboard that interfaces the ASICs with the acquisition system, that is composed by twoparts, an analog to digital conversion boards (one per ASIC) and an FPGA boards (oneper system) that manages all the ASICs and provides an interface with the PC software.The calibration of the system is carried out with a 55Fe X-rays source, absorbed in di-rect conversion by each SDD. A linear transformation in gain and offset equalizes thechannels mismatch.Test with the 1" scintillator detector have conducted obtaining an energy resolution of3% at 662 keV (and 2.1 % at 1.3 MeV) lower than the reference one obtained with aPMT (3.2 % at 622 keV) and confirming a further advantages of the readout based onSDDs arrays with respect to a photomultiplier, a superior linearity at high energy.

The Fifth Chapter is about a review and improvement of an ASIC, VERDI (VEr-satile Readout for Radiation Integration) designed for different families of radiationdetectors from SDD (with external discrete JFET or CMOS preamplifier) to Si(Li), Ge,PMT, ecc... The activities has been focused mainly on the re-design of the shaper am-plifier and baseline holder and few modifications in the peripheral circuits. The newanalog channels compensate some limitations of the previous versions especially interms of noise and available shaping times and gains. The new implementation allowsmore than 120 gain-shaping time combinations with two polarities to adapt the ASICfor detectors with electrons or holes collection. The results confirmed the simulationsand very good results have been obtained and reported in the last part of the chapter.

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The last chapter explores the use of the detectors and electronics developed for theESA-project for physics experiments: SIDDHARTHA and GAMMA. In particular, inthe framwork of the SIDDHARTHA project, preliminary results are very promising forthe upgrade of the existing instrument with the new generation of SDD with CMOSpreamplifier suitable to overcome the limitations given by the SDD with integratedJFET used previously.An SDD-based camera, thanks to the compatibility to high magnetic fields, is also asuitable option for a recently approved European project INSERT with the purpose ofthe realization of an instrument for simultaneous SPECT/MRI analysis. Preliminarytheoretical and experimental studies are ongoing with the modules developed for theChapter 4.The last part of the chapter is toward the possible evolution of all the developmentsdescribed in this thesis, the design of a new ASIC with many functionalities from herepresented project that, in combination with an SDDs array similar to the ESA one,can be the modular basic element for a wide range of applications, X-ray spectroscopyin nuclear physics experiments, X-ray spectroscopy with synchrotron light, gammacameras for nuclear medicine and γ-ray spectroscopy and imaging in nuclear physicsimproving the actual state of art.

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List of Figures

1.1 Pictures obtained with X-rays observations with the Chandra X-ray ob-servatory. Source: wikipedia.com . . . . . . . . . . . . . . . . . . . . 2

1.2 Example of XRF spectrum of an automotive catalyst. Source: www.amptek.com. 3

2.1 Blocks diagram for a generic radiation detector readout. . . . . . . . . 82.2 Electrical model of the detector with the equivalent noise generators. . . 92.3 The ENC as function of the shaping time. The series, 1/f and parallel

noises are highlighted. . . . . . . . . . . . . . . . . . . . . . . . . . . 122.4 Output of the optimum filter with only white series and white parallel

noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.5 Contellation of poles of the Semi-Gaussian filter with seven and 9 poles. 152.6 Sideward depletion idea. With respect to a conventional PIN diode de-

tector (a), the depletion of the bulk is achieved by positively biasing asmall n+ electrode with respect to p+ electrodes covering both sides ofthe wafer (b). Increasing the voltage only an undepleted region nearthe n+ contact is present (c). For each scheme, it is shown the electronpotential energy on the vertical direction. . . . . . . . . . . . . . . . . 18

2.7 SDD working principle, electrons generated in the energy potential min-imum drift to the collecting anode while holes to the p+ cathodes. . . . 19

2.8 Electron energy potential diagrams in the drifting region of the SDD (a),and in the region close to the anode where the potential valley is directedtowards the surface (b). The potential is related to the structure shownin Figure 2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.9 a) Schematic diagram of the Silicon Drift Detector for X-ray spectroscopywith continuous implant on the back side. b) Energy potential for elec-trons inside a SDD with homogeneous entrance window. A possibleelectrons path is shown. . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.10 A view of a SDD with an integrated n-channel JFET. . . . . . . . . . . 242.11 a) Schematic top view of the integrated JFET b) lateral view of the cen-

tral region of the SDD. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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List of Figures

2.12 Concept idea of the SD3, the drift field is created in order to force theelectrons to drift toward the readout anode in the lateral side. . . . . . . 25

2.13 Pulsed reset scheme for SDD with integrated n-JFET used as voltagefollower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.14 complete lateral view of a SDD with integrated JFET, most of the par-asitic capacitance are shown, in particular the junction capacitance be-tween anode and guard ring Ca-igr used as feedback element. . . . . . . 26

2.15 Voltage output with the integration of the leakage current and of thesignal (above) and the reset signals (below). . . . . . . . . . . . . . . . 27

2.16 Schematic view of CUBE connected to the SDD detector. . . . . . . . . 282.17 a) Energy resolution at the Mn −Kα line of the 55Fe source with a 25

mm2 SDD, b) comparison of energy spectrum of a sample with Zincand Gallium acquired with SDD+JFET and SDD+CUBE with 0.3 µspeaking time and input count rate of 800 kcps. . . . . . . . . . . . . . . 29

2.18 137Cs spectrum at room temperature, the same graph includes two energyscales in order to appreciate the low energy peak at 32 keV and the mainpeak at 662 keV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.19 a) Layout of the monolithic array of 19 SDDs. b) Distribution of 11points along a line, the intrinsic spatial resolution of less than 200 µm.Pictures are from [35]. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.20 a) Layout of the DRAGO camera ,with a monolithic array of 77 SDDs,the active area is 6.7 cm2. b) Irradiation spots of a 57Co source colli-mated, a spatial resolution from 0.25 to 0.5 mm was measured. Figuresfrom [36, 37]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.21 a) Detector array of the HI-CAM gamma camera, with 100 SDDs. b)Thyroid phantom acquired with the camera. Figures from [39, 40]. . . 33

3.1 Skecth of the IXO observatory (a) and view of the instruments. Figuresfrom [42] [43] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2 Example of application: study of stars or black holes (in this case) fromthe X-rays reflected by accreation disks. Figure from [43]. . . . . . . . 37

3.3 Mechanical dummy sample of the HTRS sensor, (a) detector back-sidewith entrance window,(b) top-side with contacts of the single elements. 37

3.4 Sensor readout (a) and blocks diagram with emphasis on the digital pro-cessing unit (b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.5 Output of the shaping filter in three cases: with (marked red and blue)or without (marked green) pile-up. . . . . . . . . . . . . . . . . . . . . 40

3.6 Characteristic times of the impulse response of a generic filter. . . . . . 413.7 Output response of three events without pile-up. . . . . . . . . . . . . . 413.8 Comparison of CR-RCn and semi-Gaussian with same peaking time and

different orders. With the same order, the semi-Gaussian is always thenarrowest. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.9 Poles location (a) and impulse responses (b) of semi-Gaussian filterswith seven and nine poles approximation. . . . . . . . . . . . . . . . . 43

3.10 Graphical comparison of the requirements in terms of energy resolutionand efficiency. The four reported times are the peaking times chosen forthe design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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List of Figures

3.11 HTRS chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.12 Lateral view of SDD with integrated JFET. The junction capacitance

between anode and guard ring is highlighted. . . . . . . . . . . . . . . 503.13 Pulsed reset scheme for SDD readout. . . . . . . . . . . . . . . . . . . 503.14 Proposed solution for the preamplifier. . . . . . . . . . . . . . . . . . . 513.15 Reset logic circuits (simplified with functional blocks). . . . . . . . . . 523.16 Timing diagram of control signals. . . . . . . . . . . . . . . . . . . . . 533.17 First stage with AC coupling and first (real) pole. . . . . . . . . . . . . 543.18 Low pass MFB, also called Rauch cell or infinite gain cell. . . . . . . . 553.19 Low pass Sallen Key non inverting cell. . . . . . . . . . . . . . . . . . 553.20 Response of the filter with three peaking times and different gain settings

(post-layout simulations). . . . . . . . . . . . . . . . . . . . . . . . . . 573.21 Shaper filter sketch with simulated outputs of the intermediate stages

(absolute values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.22 Fast shaper (orange) and main shaper (yellow) in the 600 ns configura-

tion peaking time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.23 Baseline holder general view. . . . . . . . . . . . . . . . . . . . . . . . 603.24 Tranfer functions: a) shaper only, b) BLH, c) shaper and BLH consider-

ing as input the current in the virtual ground (after the couplig capacitor).Figure from [51]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.25 Shift of the baseline due to the AC coupling. . . . . . . . . . . . . . . . 613.26 Equivalent model of a simple implementation of the BLH, amplifier fol-

lowed by low pass-filter. . . . . . . . . . . . . . . . . . . . . . . . . . 613.27 Simplified shaper signal for calculation. . . . . . . . . . . . . . . . . . 623.28 Voltage response at the output of the amplifier (a) and on C (b) for the

figure 3.26 with triangular input signal. . . . . . . . . . . . . . . . . . 623.29 Voltage signals including the period between two signals a) C discharge,

b) linear discharge for τ »TR, c) average baseline value during T. . . . . 623.30 Output of the amplifier with modification of saturation to VDD. . . . . 633.31 Shaper and BLH blocks diagram. Figure from [51]. . . . . . . . . . . . 633.32 Output with a non linear elements that reduce the integrated charge. . . 643.33 Equivalent model for the BLH with a non linear element, also in this

case the amplifier saturates to VDD. . . . . . . . . . . . . . . . . . . . 643.34 Output before (a) and and after (b) the non linear element. . . . . . . . 653.35 De Geronimo’s architecture with the non linear buffer and the low pass

filter made as cascade of followers with capacitive loads. . . . . . . . . 653.36 BLH circuit for the HTRS chip, current mirrors branches not shown. . . 673.37 Simulated output response of the shaper with the BLH connected. Above

zoom of the output of the shaper, below zoom of the output of the pream-plifier (ramp). The signal with 20 kcps rate starts at 300 ms. The outputof the baseline is held with a small shift. The picture is a zoom andthe part below the baseline (picture above) are undershoots of the shaperresponse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.38 PKS circuit diagram. During the "tracking phase", the switch T is closed,and the circuit works as a buffer with the input voltage reported on CH. . 69

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List of Figures

3.39 a) Example of an erroneous peak detected in a standard PKS with afixed reset time. Upon the arrival of next event, the PKS after reset isnot able to reach the correct amplitude of the second peak. b) Correctpeak detection with tracking. . . . . . . . . . . . . . . . . . . . . . . . 70

3.40 Operation of the 3-phase PKS with indication of the most significantcommand signals. In the TRACKING phase, the PKS is in the bufferconfiguration, tracking the shaper output. The WRITE and READ phasestypical of a 2-phase PKS are activated only in proximity to the peak ofthe semi-Gaussian pulse, enabled by the temporal window PKS_ PHASE. 71

3.41 Desired processing of the pulses to maximize the throughput. I) bothevents have to be discarded; II) first event has to be read, second eventis corrupted and must not to be read; III) both events have to be read. . . 72

3.42 The proposed pile-up rejection strategy. The length of the control win-dow T2 is equal to the falling tail of the semi-Gaussian pulse. If a TR_FAST occurs in this phase, the T2 windows is extended for another peak-ing time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.43 Simulation of two events close together. The signals have the same am-plitude and they are correctly read. . . . . . . . . . . . . . . . . . . . . 73

3.44 Circuit for the generation of the T2 signal. MR is the master reset of thelogic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.45 Circuit for the regeneration of the T2 signal. . . . . . . . . . . . . . . . 743.46 Control signals without pile-up. . . . . . . . . . . . . . . . . . . . . . 753.47 Control signals with pile-up. . . . . . . . . . . . . . . . . . . . . . . . 763.48 Output buffer architecture. . . . . . . . . . . . . . . . . . . . . . . . . 763.49 HTRS chip layout. Area 15 mm2. . . . . . . . . . . . . . . . . . . . . 773.50 Blocks diagram of the system, with functional flow chart of the DAQ. . 783.51 Picture with ASIC board (on the left) and (DAQ board on the right). . . 793.52 Integration of the leakage current in the feedback capacitance, traditional

ramp like response of the preamplifier. . . . . . . . . . . . . . . . . . . 793.53 Signals from calibration source superimposed to the ramp. . . . . . . . 793.54 Zoom of the individual signal with the voltage step. . . . . . . . . . . . 803.55 Reset phase with overshoot, the integrated logic inhibits a second not

wanted reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803.56 FWHM at MnKα with the integrated preamplifier and external shaper

amplifier and acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . 813.57 Output of the main shaper with three setting (waveforms superimposed)

600 ns (yellow), 1.5 µs (red) and 3.94 µs (cyan), and the fast shaper (blue). 813.58 Output of the shaper with fixed peaking time (1.5 µs) and four gain settings. 813.59 Positive output buffer (yellow) with clock (blue, 10 MHz) and select

signal (green) of one channel in configuration 4+4. The digital signalsare in LVDS standard (here the positive one). . . . . . . . . . . . . . . 81

3.60 Spectrum of the 55Fe source measured with an SDD and the CMOSCUBE preamplifier (temperature of -40 °C). The best energy resolutionof 126.2 eV FWHM was achieved using the 1.5 µs peaking time. Theinput count rate is 115 kcps. The input count rate is estimated with adigital pulse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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List of Figures

3.61 55Fe source spectrum measured with a SDD and the CMOS preamplifier,at a temperature of -40 °C. The peaking time of the shaper is 600 ns. Theinput count rate is 800 kcps, the output count rate 265 kcps. . . . . . . 83

3.62 Efficiency as a function of the input count rate for the four peaking timessettings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.63 Output count rate with different input count rate (dashed lines are thetheoretical limitations). . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.64 FWHM as function of the input count rate. . . . . . . . . . . . . . . . 843.65 Acquisition with the MCA software interface. . . . . . . . . . . . . . . 853.66 Four channels spectra exported in MATLAB. . . . . . . . . . . . . . . 853.67 Total spectrum with channels calibrated. The input count rate is 250

kcps at -40 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863.68 Effectiveness of the pile-up rejection strategy. Comparison of the typi-

cal spectrum acquired with PUR disabled (red) and with PUR enabled(blue). The peaking time is 600 ns, the input count rate is 265 kcps. . . 86

4.1 Nuclear radiation from planetary surface. Figure from [59]. . . . . . . . 884.2 Lateral view of the SDD. . . . . . . . . . . . . . . . . . . . . . . . . . 894.3 Single square shaped SDD element with 8 mm x 8 mm active area. . . . 894.4 Matrix made up of 3 x 3 SDDs (8 x 8 mm2). The lateral side of the

matrix is 26 mm, the active area is 24 x 24 mm2 and 1 mm of border isthe dead area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.5 Sketch with the readout strategy based on multiple SDDs modules forscintillators of different sizes. . . . . . . . . . . . . . . . . . . . . . . 91

4.6 Vcathode= -180 V (below twice the full depletion voltage) of a SDD.Dimensions in the axes are microns. Dimensions do not correspond tothe real SDD developed but to a device simulated to show the principle.Courtesy of FBK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.7 Simulated drift time distribution (left) and anode signal(right) composedas result of charge collected in different zones (with different drift times). 92

4.8 Representation of the ballistic deficit. h(t) (blue) is the ideal δ responsewhile y(t)(red) is the output when a real signal is collected. . . . . . . . 96

4.9 Single module with SDD (gray with dead areas white), ceramic carrier(green) and supporting copper frame. . . . . . . . . . . . . . . . . . . 97

4.10 Detailed view of the bottom side of the ceramic carrier with anodes andfirst rings bondings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.11 Mechanical structure of the detection unit with four modules, the exter-nal plastic housing is not shown. . . . . . . . . . . . . . . . . . . . . . 98

4.12 View of the solution with nine modules for the 3" scintillator. . . . . . . 984.13 Blocks diagram of the ESA ASIC. . . . . . . . . . . . . . . . . . . . . 994.14 In-channel threshold generation, a main level is corrected with 3 SPI

bits. A proper programmable current is used to set the independent value. 1004.15 150 keV γ-ray simulation. Points of interaction within the crystal (left)

and distribution of the charge inside the SDD collecting less charges foreach gamma event simulated (right). . . . . . . . . . . . . . . . . . . . 101

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4.16 15 MeV γ-ray simulation. Points of interaction within the crystal (left)and distribution of the charge inside the SDD collecting more chargesfor each gamma event simulated (right) . . . . . . . . . . . . . . . . . 102

4.17 Simulation of the outputs of all the shaper stages. . . . . . . . . . . . . 1034.18 Shaper schematic with schematized BLH. In green the DC currents re-

quired for the output baseline stabilization, in red the DC voltages. . . . 1054.19 First stage with the input capacitors that allow the fine regulations, Cac=25

pF, CacD1=10 pF, CacD2=5 pF. . . . . . . . . . . . . . . . . . . . . . . 1064.20 Simplified shaper and BLH schematics with switches used for the inhibit

during the reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . . 1064.21 Inhibit signals for shaper and BLH synchronous to the preamplifier reset.

T2 and should be longer than two time the shaper peaking time and T32 µs more. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.22 Schematic of the three phases peak detector. Compared to the peak de-tector of Chapter 3, the buffer at the output of the holding capacitor hasbeen removed to extend the dynamic range. . . . . . . . . . . . . . . . 108

4.23 OTA internal structure with a feedback circuit in order to have a constantgm for all the input dynamic. . . . . . . . . . . . . . . . . . . . . . . . 108

4.24 ASIC layout. Total size about 19 mm2 with 96 PADs. . . . . . . . . . . 1094.25 Schematic readout strategy, on the righ the main functions of the DAQ

are summarized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104.26 Pictures of the ASIC boards, on the left board that hosts the single ASIC

(under the metalling box, directly bonded to the PCB) and, on the right,the main board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.27 Picture of the DAQ and three snap-in cards each one with one ADC. . . 1124.28 Software GUI for ASIC management and signals acquisition. It is based

on VB.NET framework. . . . . . . . . . . . . . . . . . . . . . . . . . 1124.29 Digital (LVDS standard) signals during the programming phase. . . . . 1134.30 Ramp and digital signals during the preamplifier reset. . . . . . . . . . 1134.31 Gain spread between all the 27 channels (analog shaper). . . . . . . . . 1144.32 Acquisition with two input signals close together, in yellow the input, in

green the output of the shaper, in blue the voltage on the hold capacitorof the peak stretcher circuit and in red the output of the MUX (positiveof the fully differential amplifier on the board). . . . . . . . . . . . . . 114

4.33 Wafer picture with the four arrays per wafer can be identified. Otherdetectors are present in the remaining part of the 4" wafer, in particular8x8 mm and 12x12 mm square shaped, 10 mm2 round shaped SDDs and10 mm2 PIN diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

4.34 Measurements of QE for a Diode (circles) and a test SDD (squares)taken from two different wafers having the same nominal ARC. Thegood correspondence of the ARC theoretical transmittivity with the mea-sured QE is an indication that most of the carriers generated in siliconby the optical light are collected by the anode of the SDD, without sig-nificant loss in the entrance window of the device. . . . . . . . . . . . . 116

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4.35 Anode current experimentally measured, lighting a 8x8 mm2 SDD withfast (100 ns) led pulses and acquiring the voltage waveform at the out-put of the preamplifier with an oscilloscope. The anode current is thederivative of the shaper output . . . . . . . . . . . . . . . . . . . . . . 117

4.36 Sketch of the experimental set up for the single SDD characterization. . 1174.37 Photographs of the experimental set-up with detector and electronics:

a) the biasing box outside the box and the ceramic carrier inside. b)detection module including also the scintillator for the gamma-ray mea-surements, see next sections. . . . . . . . . . . . . . . . . . . . . . . . 118

4.38 Energy spectrum of the 55Fe source measured at -20 °C at a 1 µs shapingtime. The SDD was operated with the back electrode connected by abonding and biased independently. The ENC is 8.7 e-. . . . . . . . . . 119

4.39 Energy spectrum of the 55Fe source measured at -43 °C with 1.5 µs shap-ing time. The electronics noise is 5.9 e- rms. . . . . . . . . . . . . . . . 119

4.40 Measurements at -20 °C and -43 °C, comparison of FWHM (left) andENC (right) values measured using all the available shaping times. TheSDD is with the back electrode connected by a bonding and biased in-dependently. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.41 Energy spectrum of the 55Fe source measured at -43 °C with 1.5 µs shap-ing time. Back electrode is floating and biased by punch-through. Theelectronics noise is 7.5 e- rms. . . . . . . . . . . . . . . . . . . . . . . 121

4.42 Mn-Kα peak stability at different temperatures using the SDD with theback electrode biased with the punch-through technique. In the plot,the peak position expressed in terms of MCA channels is reported fordifferent temperatures (with the corresponding leakage current). . . . . 121

4.43 Positions within the SDD. The area enclosed by the blue line is the activeSDD area whereas that in between the blue and green lines is the cuttingmargin of the SDD. From h13 to h5 the step is about 1 mm while the lastfour are 0.5 mm each. . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.44 Comparison of horizontal and diagonal positions within the SDD with-out the back bonding at different shaping times. . . . . . . . . . . . . . 123

4.45 Comparison of horizontal and diagonal positions within the SDD withback bonding for three 0.5 µs, 1.5 µs and 6 µs shaping times. . . . . . . 124

4.46 Energy spectrum of the 57Co source measured at -20 °C and 3 µs shapingtime with the SDD (back floating) coupled to a LaBr3:Ce scintillator. . . 125

4.47 Energy resolution @122 keV measured on the 57Co spectrum versusshaping time. In the plot, also the conversion gain of the measurement(e-/keV) is reported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.48 Energy spectra of the 57Co and 137Cs measured simultaneously with theSDD coupled with the LaBr3:Ce scintillator. The temperature is -20 °Cand the shaping time is 4 µs. A zoom of the 137Cs spectrum is includedwith the resolution measured at the 662 keV peak. . . . . . . . . . . . . 127

4.49 Real SDD module: a) SDD array mounted on the ceramic carrier and b)carrier with the copper block (view from the bottom side). . . . . . . . 127

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4.50 Nine 55Fe spectra acquired with the SDDs array cooled at -20°C. Thecalculated average ENC is about 14.4 electrons rms with a minimum of12.8 electrons rms. Peaking time is 2 µs. . . . . . . . . . . . . . . . . . 127

4.51 Spectrum in e- of the 55Fe source measured at -20°C. The calibrationallow to estimate the equivalent number of electrons and therefore thee-/eV gain of the scintillator coupled to the detector. . . . . . . . . . . . 128

4.52 Picture of the 1" scintillator. The material is hygroscopic and it is pro-vided packed with Teflon (partially visible) around it (5 layers) and alu-minium covering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.53 Spectrum with 137Cs. Temperature is -20 °C and the peaking time of theanalog shaper is 6 µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.54 Spectrum with three sources 57Co (peak at 122 keV), 137Cs (peak at 662keV) and 60Co (peaks at 1.17 MeV and 1.33 MeV). Temperature is -20°C and the peaking time of the analog shaper is 6 µs. . . . . . . . . . . 129

4.55 Picture of the mechanical set-up that hosts the 2" scintillator under pre-liminary temperature tests. The plasic box has some holes for powersupplies of Peltier stages, output signals and nitrogen input. . . . . . . . 130

5.1 Blocks diagram of the VERDI-3 chip. . . . . . . . . . . . . . . . . . . 1325.2 Gamma and Spectroscopy mode. In the first case (a) the outputs have to

be read all together, in the second (b) the channels are rad independently. 1335.3 Front-end connection. Outside the dashed box, the specific front-end for

the detectors, in this case the widespread readout with a discrete JFETwith a feedback capacitance. . . . . . . . . . . . . . . . . . . . . . . . 134

5.4 Internal structure of the charge preamplifier, the input MOS are the 5 Voption of the technology in order to work with higher voltages of the JFET. 135

5.5 Internal structure of the analog channel, the switches are necessary forthe different configurations. . . . . . . . . . . . . . . . . . . . . . . . 136

5.6 Shaper cells, a) first cell b) six successive stages. . . . . . . . . . . . . 1375.7 Schematic of the output stage of the BLH, the two switches (in red) can

be opened or closed in order to modify the current direction. . . . . . . 1375.8 Layout of the chip. Total area 12 mm2, 103 PADs. . . . . . . . . . . . 1385.9 Boards for testing and acquisition. On the left the "analog board", on the

right the "digital board" segmented with flexible layers. The white cableconnects the output of the ASIC to one commercial ADC. . . . . . . . 139

5.10 Screenshot of the software (Canberra) with ASIC setting. . . . . . . . . 1405.11 Output of the analog channel with different settings. . . . . . . . . . . 1405.12 VERDI configuration with an SDD+JFET. . . . . . . . . . . . . . . . . 1415.13 Energy resolution at -25 °C and comparison with the first version of the

ASIC. The second version differs from the first only for some peripheraldigital circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.14 Energy resolution at room temperature. The FWHM is 351.2 eV corre-sponding to an ENC of 39.1 e- rms (shaping time 0.25 µs). . . . . . . . 142

5.15 VERDI coupled to SDD with a different readout based on digital pulseprocessing of the ramp. . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.16 VERDI coupled to a Ge detector. . . . . . . . . . . . . . . . . . . . . . 1435.17 VERDI coupled to a Si(Li) detector. . . . . . . . . . . . . . . . . . . . 144

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5.18 VERDI used as readout electronics for PMT coupled to a scintillator. . 144

6.1 Picture the detector arrays within the SIDDHARTA-1 instruments. Thereadout electronics can be seen stacked behind the detectors. . . . . . . 147

6.2 Picture of the vacuum chamber with the cryostat (black). The SDD un-der test is connected to a copper frame directly on contact with the cryo-stat cold tip. Top left is the vacuum chamber with the cryostat on thetop, top right is the internal of the chamber with the support for the vac-uum 55Fe source. Bottom left is a cryostat picture while bottom right is adetailed view of the cold tip with the SDD mounted in a proper ceramiccarrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6.3 Energy resolution of the 64 mm2 (8 x 8 mm) SDD coupled with CUBEpreamplifier at the Mn-Kα line for different temperatures. . . . . . . . 148

6.4 Energy resolution of the 64 mm2 SDD at the Mn-Kα line at 50 K, shap-ing time 2 µs (uncollimated source). . . . . . . . . . . . . . . . . . . . 149

6.5 Drawings of the possible upgrade of the detectors for the SIDDHARTAexperiment. On the left the a section view, on the right the completedetection system. The modules here shown are the same of Chapter 4.Courtesy of SMI-ÖAW. . . . . . . . . . . . . . . . . . . . . . . . . . . 149

6.6 Comparison of the measurements with SDDs biased with two techniquesat 160 K. The results are practically the same. . . . . . . . . . . . . . . 150

6.7 55Fe source spectra with an improved version of CUBE preamplifier with10 mm2 round shaped SDD. . . . . . . . . . . . . . . . . . . . . . . . 151

6.8 When a radioactive source moves at high or relativistic velocity, theemitted γ-rays are subject to an energy shift. In other words, at highv/c ratios γ1 and γ2 have no more the same energy and the overall spec-trum has a broadening. An Anger camera could detect the position ofinteraction in the crystal, proving an implicit information about θ1 andθ2, opening thus the way to a possible energy correction. . . . . . . . . 152

6.9 Detector plane with diameter of the 1" scintillator and in grey the irradi-ation spots, 5 mm step each. . . . . . . . . . . . . . . . . . . . . . . . 153

6.10 Reconstructed points and reference positions (grey). The reconstructionof the points is done with the centroid method with baseline subtraction.Reconstructions by P. Busca. . . . . . . . . . . . . . . . . . . . . . . . 153

6.11 Principle of the integrated MRI/SPECT instrument for the INSERT project. 1546.12 Drawings of the preclinical (left) and clinical systems (right). . . . . . . 1546.13 3D drawings of the possible detection head module with 4 arrays each

for the eventual implementation with SDDs. On the left the single mod-ule with active area 5 cm x 5 cm, on the right two module side by side. . 155

6.14 Measurements with SDD coupled with CsI(TI) scintillator at -20 °C with57Co source. On the left the energy spectrum with a resolution below 8%while on the right the scintillator gain (e-/keV) function of the peakingtime of the shaper filter. . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6.15 Resolution as function of the peaking time of the filter with the 8 mmcylindrical CsI(TI) scintillator coupled with a single SDD at -20 °C.Long peaking times allow to compensate the ballistic deficit increasingthe e-/keV and reducing the Poisson contribution. . . . . . . . . . . . . 156

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6.16 Block diagram of an ASIC to be coupled to the 9 SDDs array for therealization of modular detector with electronics for different applications. 158

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List of Tables

1.1 Relevant properties of the most common used scintillator materials. . . 51.2 Relevant properties of semiconductor materials included materials used

for direct conversion γ-rays detectors. . . . . . . . . . . . . . . . . . . 5

2.1 Shaping factors. Some data from [1], others calculated by hand or withMatlab simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Relevant properties of the most common photodetectors. . . . . . . . . 30

3.1 Sensor requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.2 Real and imaginary part of the poles of the semi-Gaussian filter (sev-

enth and ninth order). The pole position is normalized with an unitarypeaking time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Characteristic times and shaping factors of the two filters. . . . . . . . . 443.4 SDD parameter for noise evaluation. . . . . . . . . . . . . . . . . . . . 443.5 Poles location, ω0 and Q factor for the 600 ns peaking time. . . . . . . 46

4.1 Detector unit specifications. . . . . . . . . . . . . . . . . . . . . . . . 884.2 Comparison between emitted light wavelength, yield and decay time of

some scintillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964.3 Q andωn(normalized to τp) for the 7th order shaper. . . . . . . . . . . 103

5.1 Shaping times of the filter. The peaking time is six times the shapingtime value (Chapter 2). . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.2 Gains. The value corresponds to the amplitude at the input of the shaperthat gives the maximum signal at the output, smaller is the value, higheris the gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6.1 Measurment for peak stability estimation, the temperature is kept to 100K and the rate is 1 kcps. . . . . . . . . . . . . . . . . . . . . . . . . . 150

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