A 2-GHz Direct Sampling ӣ Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL

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A 2-GHz Direct Sampling ΔΣ Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL. T. Chalvatzis 1 , T. O. Dickson 1,2 and S. P. Voinigescu 1 1 University of Toronto, Toronto, CA 2 now with IBM T.J. Watson Research Center, NY, USA. Outline of Presentation. Motivation Circuit design - PowerPoint PPT Presentation

Transcript of A 2-GHz Direct Sampling ӣ Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL

  • A 2-GHz Direct Sampling Tunable Receiver with 40-GHz Sampling Clock and on-chip PLLT. Chalvatzis1, T. O. Dickson1,2 and S. P. Voinigescu1

    1 University of Toronto, Toronto, CA2 now with IBM T.J. Watson Research Center, NY, USA

  • Outline of PresentationMotivationCircuit designLoop filterPLLMeasurement resultsSummary

  • MotivationDirect sampling receiver for 2-GHz radio with 60 MHz BWCT BP ADC with SNDR of 55dB/60MHz [Chalvatzis et al., JSSC, May 2007]Investigation of clock jitter impact with on-chip clock source

  • System Architecture2-GHz Gm-LC BPFFourth order loop1-bit quantizer as DFFwith FCLK=40GHzRZ pulse DACs40-GHz VCO/PLL

  • System Level DesignDesign methodology in continuous-timeSystem level simulation for accurate analysis of loop delayLoop coefficients:Gm1=22mS, Gm2=15mSGfb1=50mS, Gfb2=150mSSNDR=61dB over 60 MHz in Matlab Simulink

  • SNR vs clock jitterClock jitter effect simulated for FS=40GHz, OSR=333PLL jitter < 1.4 ps (rms) for 10 bits resolution: quantizer step[Ortmanns et al., ISCAS 2003]

  • SNR vs resonator QQuantization noise integrated over BW for FS=40GHzQ >18 for 10 bits resolution

  • Loop FilterMOS-HBT cascode for high linearity and low noiseEF limit voltage headroom, current source adds noiseLoop filter with EF

  • Modified Loop FilterMOS-HBT cascode for high linearity and low noiseEF limit voltage headroom, current source adds noiseModified Loop Filter

  • D/A Converter QuantizerDAC and quantizer with MOS-HBT cascodes [Chalvatzis et al., JSSC, May 2007]MOS on clock path to improve speed with low supplyHBT on data path for high gain

    DACLatch

  • Digital Receiver PLL Blocks40-GHz PLL design from 2.5V challengingCombination of MOS-HBT transistors in PLL blocksResettable Latch

  • Digital Receiver PLL Blocks40-GHz PLL design from 2.5V challengingCombination of MOS-HBT transistors in PLL blocks

    Charge Pump

  • VCOColpitts VCO topology with HBT [Dickson et al., CSICS 2006]VCO biased for minimum phase noiseDifferential tuning with accumulation mode MOS varactors

  • Fabrication and characterization of digital receiver

  • FabricationADC with on chip VCO/PLL in STM 0.13m SiGe BiCMOSPower dissipation 2.19W from 2.5VChip size 1.59x2.39mm2

  • PLL measurementsPhase noise/jitter measured on PLL test structureRMS jitter: t=849fsJitter limited SNR for Fo=2GHz and OSR=333 -> SNR=66.7dB

  • VCO measurementsPhase noise < -103dBc/Hz at 1 MHz offset from 40-GHz carrier

  • Spectrum measurement with PLLADC tested with external and on-chip clockNo significant degradation from on-chip clockFeedthrough from 2.5GHz PLL reference does not degrade performance

  • SFDR measurementSFDR=59dB

  • SNDR measurementSNDR measured for FIN=2GHz, FS=40GHzSNDR = 59.8dB over 60 MHz

  • Dynamic RangeADC noise floor the same (-65dBm/60MHz) when external and on-chip clock employed

  • Digital Receiver Performance

  • ConclusionFirst mm-wave sampling digital receiver in any semiconductor technologyDigital receiver achieves 9.65-bit resolution over 60 MHzRemoving EF pair in filter helps to increase linearity of ADC loop filterFor 10-bits resolution, jitter from on-chip VCO/PLL not limiting performanceNoise floor set by resonator Q

  • AcknowledgementsNortel Networks for funding supportJohn Ilowski and Eric Gagnon for discussionsSTMicroelectronics for chip fabricationProf Miles Copeland for advice on the manuscriptRicardo Aroca for help with testingCMC for CAD toolsJaro Pristrupa for CAD support