360 μΩ, 5 V/60 A N-Channel MOSFET - Vicor...

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μRDS(on) FET™ Series Rev 1.0 vicorpower.com Page 1 of 10 01/2014 800 927.9474 360μ, 5 V/60 A N-Channel MOSFET μR DS(on) FET Series PI5101-01-LGIZ Product Description The PI5101μR DS (on) FET™ solution combines a high- performance 5 V, 360 μΩ lateral N-Channel MOSFET with a thermally enhanced high density 4.1mm x 8mm x 2mm land-grid-array (LGA) package to enable world class performance in the footprint area of an industry standard SO-8 package. The PI5101 offers unprecedented figure-of- merits for DC & switching applications. The PI5101 will replace up to 6 conventional “SO-8 form factor” devices for the same on-state resistance, reducing board space by ~80%. The PI5101 offers unprecedented figure-of-merit for R DS(on) x Q G , gate resistance (R G ) and package inductance (L DS ) outperforming conventional Trench MOSFETs and enabling very low loss operation. The PI5101 LGA package is fully compatible with industry standard SMT assembly processes. Product Summary Features Ultra Low “micro-Ohm” R DS(on) Extremely Low Gate Charge Very Low Gate Resistance High Density, Low Profile Very Low Package Inductance Low Thermal Resistance Applications Power Path Management Solutions Active ORing & Load Switches High Current DC-DC Converters Package Information 4.1mm x 8mm x 2mm Thermally Enhanced LGA Symbol Condition Value I D T A = 25°C 60 A DC Max V (BR)DSS I D = 5 mA 5 V Min R DS(ON) V GS = 4.5 V 360 μTyp V GS = 3.5 V 380 μTyp Q G V GS = 4.5 V 65 nC Typ R G 0.1 Typ L DS 0.1 nH Typ

Transcript of 360 μΩ, 5 V/60 A N-Channel MOSFET - Vicor...

Page 1: 360 μΩ, 5 V/60 A N-Channel MOSFET - Vicor Corporationcdn.vicorpower.com/documents/datasheets/Picor/ds_PI5101.pdf360 μΩ, 5 V/60 A N-Channel MOSFET μRDS(on) FET ™ Series PI5101-01-LGIZ

μRDS(on) FET™ Series Rev 1.0 vicorpower.comPage 1 of 10 01/2014 800 927.9474

360μΩ, 5 V/60 A N-Channel MOSFET

μRDS(on) FET™ Series

PI5101-01-LGIZ

Product Description

The PI5101μRDS(on) FET™ solution combines a high-performance 5 V, 360 μΩ lateral N-Channel MOSFET with athermally enhanced high density 4.1mm x 8mm x 2mmland-grid-array (LGA) package to enable world classperformance in the footprint area of an industry standard SO-8 package. The PI5101 offers unprecedented figure-of-merits for DC & switching applications. The PI5101 willreplace up to 6 conventional “SO-8 form factor” devices forthe same on-state resistance, reducing board space by ~80%.The PI5101 offers unprecedented figure-of-merit for RDS(on) x QG, gate resistance (RG) and package inductance (LDS)outperforming conventional Trench MOSFETs and enablingvery low loss operation.

The PI5101 LGA package is fully compatible with industrystandard SMT assembly processes.

Product Summary

Features

• Ultra Low “micro-Ohm” RDS(on)• Extremely Low Gate Charge

• Very Low Gate Resistance

• High Density, Low Profile

• Very Low Package Inductance

• Low Thermal Resistance

Applications

• Power Path Management Solutions

• Active ORing & Load Switches

• High Current DC-DC Converters

Package Information

• 4.1mm x 8mm x 2mm

Thermally Enhanced LGA

Symbol Condition Value

ID TA = 25°C 60 ADC Max

V(BR)DSS ID = 5 mA 5 V Min

RDS(ON)VGS = 4.5 V 360 μΩ Typ

VGS = 3.5 V 380 μΩ Typ

QG VGS = 4.5 V 65 nC Typ

RG 0.1 Ω Typ

LDS 0.1 nH Typ

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Maximum Rating and Thermal Characteristics

TA = 25°C unless otherwise specified.

Parameter Symbol Limit Unit

Drain-to-Source Voltage VDS 5 V

Gate-to-Source Voltage VGS ±5 V

Drain CurrentContinuous ID 60 A

Pulsed IDM 150 A

Single Pulse Avalanche Current TAV <100 μs IAS 100 A

Maximum Power DissipationTA = 25°C

PD

3.1 W

TA = 70°C 2 W

Operating Junction and Storage Temperature Range TJ, TSTG -55 to 150 °C

Thermal Resistance [1]Junction-to-Ambient RθJ-A 40 °C/W

Junction-to-PCB RθJ-PCB 6 °C/W

Lead Temperature (Soldering, 20 sec) 260 °C

[1] The thermal resistance is measured when the device is mounted on 1 inch square 4-layer 2-oz copper FR-4 PCB at 0LFM and 40A drain current

Order Information

Part Number Package Transport Media

PI5101-01-LGIZ 4.1mm x 8mm x 2mm 3-Lead LGA T&R

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Electrical Characteristics

TA = 25°C unless otherwise specified.

Parameter Symbol Conditions Min Typ Max Unit

Input SpecificationsDrain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 5 mA 5.0 V

Breakdown Voltage ∆V(BR)DSSReference to 25°C, VGS = 0 V, ID = 5 mA 3.1 mV/

Temperature Coefficient ∆TJ

Drain-to-Source Leakage Current IDSS VDS = 4.8 V, VGS = 0 V 0.2 2 μAGate-to-Source Leakage IGSS VGS = 5 V, VDS = 0 V 10 200 nA

Gate Threshold Voltage VGS(th) VDS = VGS, ID = 1 mA 0.4 0.8 V

Drain-to-Source On-State Resistance RDS(on)VGS = 4.5 V, ID = 60 A 360 450 μΩ

VGS = 3.5 V, ID = 60 A 380 475 μΩTurn-On Delay Time td(on) VGS = 4.5 V, ID = 60 A, RG = 0.1Ω 14 ns

Rise Time tr VGS = 4.5 V, ID = 60 A, RG = 0.1Ω 4.5 ns

Turn-Off Delay Time td(off) VGS = 4.5 V, ID = 60 A, RG = 0.1Ω 23 ns

Fall Time tf VGS = 4.5 V, ID = 60 A, RG = 0.1Ω 3.5 ns

Forward Transconductance gfs ID = 60 A, VDS = 4 V 620 S

Gate CapacitanceInput Capacitance Ciss VDS = 5 V, VGS = 0 V, f = 1MHz; See Figure 6 7600 pF

Output Capacitance Coss VDS = 5 V, VGS = 0 V, f = 1MHz; See Figure 6 5200 pF

Reverse Transfer Capacitance Crss VDS = 5 V, VGS = 0 V, f = 1MHz 1100 pF

Gate ChargeTotal Gate Charge Qg VGS = 4.5 V, VDD = 4.4 V, ID = 60 A; See Figure 3 65 nC

Gate-to-Source Charge Qgs VGS = 4.5 V, VDD = 4.4 V, ID = 60 A 7.7 nC

Gate-to-Drain Charge Qgd VGS = 4.5 V, VDD = 4.4 V, ID = 60 A 9.0 nC

Gate Resistance RG 0.1 Ω

Reverse DiodeSource-to-Drain Reverse

trr IS = 16 A, di⁄dt = 33 A⁄μs 300 nsRecovery Time

Diode Forward Voltage VSD IS = 16 A, VGS = 0 V (Pulse Test) 0.63 1.0 V

Package Inductance LDS 0.1 nH

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TJ, Junction Temperature (°C)

RD

S(o

n),

No

rmal

ized

on

Sta

te R

esis

tan

ce

-50 -25 0 25 50 75 100 125 1500.8

0.9

1.0

1.1

1.2

1.3

1.4VGS = 4.5 VID = 60 A

Figure 2 — On-Resistance vs. Junction Temperature

Figure 1 — Output Characteristics (Pulsed VGS)

Figure 3 — Gate Charge

VGS, Gate-to-Source (V)

I D, D

rain

Cu

rren

t (A

)

0

20

40

60

80

100

120

140

160

180

200

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

TJA = 125°C

25°C

-55°C

Figure 4 — Transfer Characteristics (Pulsed VGS)

VDS, Drain-to_Source Voltage (V)

Cap

acit

ance

(p

F)

4000

5000

6000

7000

8000

9000

0 1 2 3 4 5 6

Ciss

Coss

VGS = 0 V, f = 1 MHzCiss = Cgs + Cgd: while Cds Shorted

Figure 6 — Gate Capacitance vs. Drain-to Source Voltage

VGS, Gate-to-Source Voltage (V)

RD

S(o

n),

Dra

in-t

o-S

ou

rce

On

-Res

ista

nce

(mΩ

)

0.0

0.5

1.0

1.5

2.0

0 1 2 3 4 5

Figure 5 — On-Resistance vs. Gate Voltage

QG, Total Gate Charge (nC)

VG

S, G

ate-

to-S

ou

rce

Volt

age

(V)

0

1

2

3

4

5

0 10 20 30 40 50 60 70

ID = 60 A

VDS - Drain-to-Source Voltage (V)

I D -

Dra

in C

urr

ent

(A)

0

20

40

60

80

100

120

140

160

0.0 0.2 0.4 0.6 0.8

VGS = 1.0 V

VGS = 1.2 V

VGS = 3 V, 2 V, 1.4 V

Typical Characteristics

TA = 25°C unless otherwise specified.

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Drain-to-Source Votage (V)

Dra

in C

urr

ent

(µA

)

0.01

0.10

1.00

0 1 2 3 4 5

V G S = 0 V

Figure 8 — Drain-to-Source Leakage Current

Figure 7 — Gate Threshold Voltage vs. Temperature

Figure 9 — Maximum Safe Operation Area

VSD, Source-to-Drain Voltage (V)

I S, S

ou

rce

Cu

rren

t (A

)

1

10

100

0 0.2 0.4 0.6 0.8 1

TJ = 150°C TJ = 25°C

Figure 10 — Reverse Diode Forward Voltage (Pulsed Test)

TJ, Junction Temperature (°C)

V(B

R)D

SS N

orm

aliz

ed

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

-50 -25 0 25 50 75 100 125 150

VGS = 0 VID = 5 mA

Figure 12 — Drain-to-Source Breakdown Voltage vs. temperature

ID, Drain Current (A)

gfs

, Tra

nsc

on

du

ctan

ce (

S)

0

100

200

300

400

500

600

700

0 10 20 30 40 50 60

Figure 11 — Forward Transconductance

VDS, Drain-to-Source Voltage (V)

I D, D

rain

Cu

rren

t (A

)

0.01

0.1

1

10

100

1000

0.01 0.1 1 10

Single PulseVGS = 3.5V

100µs

DC

1µs10µs

RDS(on) Limit Package Limit Thermal Limit

TJ, Junction Temperature (°C)

VG

S(t

h),

No

rmal

ized

Gat

e T

hre

sho

ld V

olt

age

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-50 -25 0 25 50 75 100 125 150

ID = 1 mA

Typical Characteristics

TA = 25°C unless otherwise specified.

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Ambient Temperature (°C)

I D D

rain

Cu

rren

t (A

)

45 55 65 75 85 95 105 115 12520

25

30

35

40

45

50

55

60

RDS(on) =360

μΩ

RDS(on)=450 μΩ

RθJA = 40°C/W

Figure 14 — PI5101 Drain current de-rating based on the maximumTJ = 150°C vs. ambient temperature

Figure 13 — Normalized Transient Thermal Impedance, Junction-to-Ambient

PCB Temperature (°C)

I D D

rain

Cu

rren

t (A

)

100 110 120 130 140 15020

25

30

35

40

45

50

55

60

RθJPCB = 6°C/W

RD

S(on) =450

μΩR

DS

(on) =360

μΩ

Figure 15 — PI5101 Drain current de-rating vs. PCB temperature, for maximum TJ at 150°C

ton

On Time Pulse Duration (s)

No

rmal

ized

Tra

nsi

ent T

her

mal

Imp

edan

ce (

Rθ-

JA)

Single Pulse

0.02

0.05

0.1

0.2

1 = 0.5

0.01

0.10

1.00

PPK

Duty Cycle:

ontτ

τδ ont=

10-4 10-3 10-2 10-1 1 101 102 103

Typical Characteristics

TA = 25°C unless otherwise specified.

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MOSFET Power Dissipationvs. Junction Temperature

In applications such as low loss ORing Diodes or circuit breakerswhere the MOSFET is normally on during steady state operation, theMOSFET power dissipation is derived from the total Drain currentand the on-state resistance of the MOSFET.

The PI5101 power dissipation can be calculated with the followingequation:

PD = ID2 • RDS(on)

Where:

PD: MOSFET power dissipationID : Drain CurrentRDS(on): MOSFET on-state resistance

Note: For the worst case condition, calculate with maximum rated RDS(on)at the MOSFET maximum operating junction temperature because RDS(on)is temperature dependent. Refer to figure 2 for normalized RDS(on) valuesover temperature. The PI5101 maximum RDS(on) at 25°C is 450µΩ andwill increase by 24% at 125°C junction temperature.

The junction temperature rise is a function of power dissipation andthermal resistance.

Trise = RθJA • PD = RJA • ID2 • RDS(on)

Where:

RθJA : Junction-to-Ambient thermal resistance (40°C/W)

This may require iteration to get to the final junction temperature.figure 16 and figure 17 are added to aid the user to find the finaljunction temperature without the iterative calculations.

Figure 16 shows the MOSFETs final junction temperature curvesversus conducted current at maximum RDS(on), and at given ambienttemperatures at 0 LFM air flow. Figure 17 shows the MOSFETs finaljunction temperature curves versus conducted current at maximumRDS(on) at given PCB temperatures.

To find the final junction temperature for a given drain continuousDC or RMS current and a given ambient or PCB temperature; draw avertical line from the drain current at the X-axis to intersect theambient or PCB temperature line. At the intersection draw ahorizontal line towards the Y-axis (Junction Temperature).

Example:

Assume that the MOSFET maximum drain current is 50 A andmaximum operating ambient temperature is 70°C.

First use figure 16 to find the final junction temperature for 50 Adrain current at 70°C ambient temperature. In figure 16 (illustratedin figure 18) draw a vertical line from 50 A to intersect the 70°Cambient temperature line (dark blue). At the intersection draw ahorizontal line towards the Y-axis (Junction Temperature). Thetypical junction temperature with maximum RDS(on), at load currentof 50 A and 70°C ambient is 126°C.

Drain Current (A)

Jun

ctio

n T

emp

erat

ure

(°C

)

0 5 10 15 20 25 30 35 40 45 50 55 60

50

60

70

80

90

100

110

120

130

140

150

100°C

TA = 50°C

90°C

80°C

60°C

70°C

RθJA = 40°C/W

RDS(on)=450μΩ

VGS = 4.5 V

Figure 16 — Junction Temperature vs. Drain Current for a givenambient temperature (0LFM)

Drain Current (A)

Jun

ctio

n T

emp

erat

ure

(°C

)

0 5 10 15 20 25 30 35 40 45 50 55 6090

95

100

105

110

115

120

125

130

135

140

145

150

140°C

TPCB = 90°C

130°C

120°C

100°C

110°C

RDS(on)=450μΩ

RθJPCB = 6°C/W

VGS = 4.5 V

Figure 17 — Junction Temperature vs. Drain Current for a given PCB temperature

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As a check, recalculate the junction temperature to confirm the plotresults. Start from the final junction temperature, 126°C, and use thefollowing steps:

RDS(on) is 450μΩ maximum at 25°C and will increase as theJunction temperature increases. From figure 2, at 126°C RDS(on)will increase by 24%, then RDS(on) maximum at 126°C is:

RDS(on) = 450 µΩ • 1.24 = 558 µΩ

Maximum power dissipation is:

PDmax = ID2 • RDS(on) = 50 A • 558 µΩ = 1.39 W

Maximum junction temperature is:

TJmax = 70°C + 50 A2 • 558 µΩ = 125.8°C

Drain Current (A)

Jun

ctio

n T

emp

erat

ure

(°C

)

0 5 10 15 20 25 30 35 40 45 50 55 60

50

60

70

80

90

100

110

120

130

140

150

100°C

TA = 50°C

90°C

80°C

60°C

70°C

RθJA = 40°C/W RDS(on)=450μΩ

126

VGS = 4.5 V

Figure 18 — Example graphing of MOSFET junction temperature at ID = 50 A and TA = 70°C

40°CW

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Package Drawing

Layout Recommendation

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