Main activities

- PCB and FPC design and simulation

- R&D of assembly technique

- Test system

- Detector integration

- Cleanroom operational activities

Antoine JUNIQUE 1

• 10 m2 active silicon area, 12.5×109 pixels

• Based on Monolithic Active Pixel Sensors (MAPS)

• Closer to IP: 39 mm g 22 mm

• Thinner (X0 / layer for inner layer): ~1.14 % g ~0.30 %

• Smaller pixels: 50 × 425 μm2 g 27 × 29 μm2

• Granularity: 20 ch/cm3 g 2000 pixels/cm3

• Readout rate: 1 kHz g 100 kHz (Pb-Pb)

• Max. particle rate: ~100 MHz/cm2

• Spatial resolution: ~5 μm

• Low fake-hit rate: << 10-6/pixel/event

• High detection efficiency: >99%

• Radiation tolerant: > 270krad TID , 1.7×1012 1MeV/neq NIEL

ITS Upgrade Overview

Inner Tracking System Upgrade g improved resolution, less material, faster readout

1.5 ≤ h ≤ 1.5

7 Layers (22mm < r < 400mm)

Antoine JUNIQUE 2

ITS Upgrade Overview

40cm

ITS Layout

Flexible PCB

9 sensors

Cold Plate

Space Frame

Outer BarrelInner Barrel

ITS upgrade in numbers (main components)

• Pixel sensor chip: ~ 27, 000 (including spares)

• IB staves: 48 + 60

• OB HICs: 1692 + 188

• OB Staves: 90 + 10 (OL), 54 + 6 (ML)

• Readout Units: 192 + 30

• Large carbon composite structures: 24

ITS Upgrade Overview

green = spares

Antoine JUNIQUE 3

ITS Upgrade Overview

FPC conception:

506.2 mm

41.9

mm

16.1

5 m

m

A

A

The 9 silicon chips are read out in parallel: each chip sends its data stream to the end of Stave by a dedicated differential pair, 100 mm wide. Two additional differential pairs distribute the clock and configuration signals.

Large planes are used to distribute analogue and digital power and respective ground connections.

FPC and Power extension Flex connexion area

The choice of the material to be used for the metal layers of the FPC is dictated by the need to minimize the

material budget, thus Al has been preferred to the standard Cu ( the respective radiation lengths being 8.9 cm

and 1.44 cm)

Power extension Flex

Antoine JUNIQUE 4

FPC conception:

S-parameters results

S-parameters simulated with SIWAVES-parameters measured with Keysight N5225A

Power integrity, AVDD & DVDD DC Voltage drop

Cosimulation with ANSYS Designer &

simulated S-parameter

Cosimulation with ANSYS Designer &

measured S-parameter

Eye diagram from real HIC, 1.2 Gb/s

Antoine JUNIQUE 5

ALPIDE chip, 50µm thick ITS FPC, 165µm thick

15

mm

30 mm

Laser Soldering

Topview after laser soldering

Innovative laser soldering technique

50 Holes

Due to yield considerations it was decided in spring 2016 to use Al wedge wire

bonding for the interconnections of the ALICE ITS HIC.

Nevertheless the laser soldering is a promising technique to be investigated for

future use. Further tests are already foreseen within the STREAM training network.

Cross section after laser soldering

Antoine JUNIQUE 6

New concept: Wire bonding through via

Schematic view ot the FPC-Chip interconnection by wire bonding technique

Laser soldering FPC layout Wire bonding FPC layout

The challenge was to adapt the laser

soldering FPC layout to the wire

bonding technique to keep the layout

geometry advantages, in a short time

Glue

FPC

Chip

Adaptation of the FPC following detailed discussions with the wire bonding experts of EP-DT-DD to meet bonding requirement.

Antoine JUNIQUE 7

IB STAVE assembly workflow

Antoine JUNIQUE 8

IB STAVE layout and components

50 mm ALPIDE chipsAl-FPC

glue mask

space frame

Flexible PCB

9 sensors Space Frame

Connector

Fitting

Connector

coverlay 20 mmAl 25 mm (IB)/ Cu 18 mm(OB)

Al 25 mm (IB)/ Cu 18 mm(OB)coverlay 20 mmAraldite 2110 50 mmALPIDE 50 mm (IB)/ 100 mm (OB)

FPC

silicon

glue

Upilex-75S

Al bonding wire (Ø 20 mm)

1.2 mm

polyimide 75 mmHybrid Integrated Circuit(HIC)

Antoine JUNIQUE 9

ITS cleanroom area

Responsible for the ALICE cleanroom area in the DSF (Depart. Silicon Facility):

• Installation of equipment and maintenance of the area infrastructure

• Access control and cleanroom work procedures

• Supply of material and personal equipment

Class ISO 6 (1000) with locally ISO 5 (100)

Antoine JUNIQUE 10

ALICIA machine

Custom developed assembly and test machine for the

ALICE ITS:

• Pick and place of pixel chips (50 um , 100 um thick)

• Visual inspection and control of the chip

• Electrical test with a probecard

• Alignment of 1x9 or 2x14 pixel chips for HIC assembly

(<5 um alignment precision)

Production of 6 ALICIA machines to be installed in the

ALICE ITS production centers:

Antoine JUNIQUE 11

IB HIC assembly procedure

Antoine JUNIQUE 12

IB HIC assembly procedure

Components preparation• Chips: visual inspection, selected “GOLD” from electrical test• FPC: electrical characterisation, metrology, cleaning, visual inspection• Glue mask : visual inspection and cleaning

HIC assembly

Chips alignment (5 mm accuracy) and edge inspection in MAM

Araldite 2011 preparation in orbital mixer and distribution on FPC using 90 mm thick glue mask

Overlap FPC on chips in MAM using 50 mm shimming and 12 h curing

Removal from MAM and visual inspection

Wire bonding

Visual inspection

Power test and R/O test

Antoine JUNIQUE 13

IB HIC assembly procedure: after chips gluing

Antoine JUNIQUE 14

IB HIC assembly procedure: wire bonding

Antoine JUNIQUE 15

IB HIC assembly procedure: IV curve

Antoine JUNIQUE 16

IB STAVE assembly procedure

STAVE assembly

Araldite 2011 preparation in orbital mixer and distribution on FPC using 90 mm thick glue mask, overlap HIC on top and 12 h curing

Visual inspection

Power test and R/O test

Antoine JUNIQUE 17

IB STAVE assembly procedure

Antoine JUNIQUE 18

Assembly of First Inner Half-Barrel Completed

Half-layer 0 Half-layer 1 Half-layer 2

Antoine JUNIQUE 19

Inner Barrel – Half-Layer 2

A-side C-side

Antoine JUNIQUE 20

Antoine JUNIQUE 21

Production issues

ALPIDE Chip

30 mm

15

mm

0,5 µm 5 µm 1,7 µm

DGND DVDD SUBPWELL

50

µm

Antoine JUNIQUE 22

Production issues: ALPIDE short-circuit

Antoine JUNIQUE 23

IB-HIC-N005 IB-HIC-L004, before burning IB-HIC-L004, after burning

ALPIDE Chip aluminium pad

Antoine JUNIQUE 24

ALPIDE Chip physical damages

Antoine JUNIQUE 25

IB-HIC-N005_Chip7(0)

Silicon particles contamination

Antoine JUNIQUE 26

Gluing mask Contamination

Particleboard

3 mm

Gluing mask

90 µm

Aluminum plate

160 µm

Aluminum flakes

Drill bit

Aluminum plate

Gluing mask

Particleboard

Antoine JUNIQUE 27

Glue filler

Silicon oxide : SiO2

Antoine JUNIQUE 28

Chip broken edge

Antoine JUNIQUE 29

Antoine JUNIQUE 30

Glass ball contamination

Element Line Type Apparent Concentration k Ratio Wt% Wt% SigmaAtomic % Standard Label

O K series 8,42 0,05739 35,82 0,16 48,11 Al2O3

Na K series 5,93 0,05078 24,04 0,17 22,47 NaCl

Mg K series 0,45 0,00379 1,85 0,04 1,63 MgO

Al K series 0,16 0,00133 0,6 0,04 0,48 Al2O3

Si K series 7,63 0,07626 31,13 0,13 23,82 Si

K K series 0,07 0,00071 0,28 0,06 0,15 KBr

Ca K series 1,58 0,01511 5,89 0,1 3,16 CaF2

Ti K series 0,09 0,00093 0,4 0,08 0,18 Ti

Total: 100 100

Glass ball contamination

Antoine JUNIQUE 31

Gripper

Mirror

At 45°

Antoine JUNIQUE 32

ALICIA machine, Chip Gripper

Antoine JUNIQUE 33

Chip Gripper : silicon particles

Antoine JUNIQUE 34

Chip Gripper: glass ball

T715399_W02T_A6

Antoine JUNIQUE 35

ZS x200 – x 2000, x200 light: Full coaxial ZS x200 – x 2000, x200 light: Mix

ZS x20 – x 200, x200 light: Full coaxial ZS x20 – x 200, x200 light: Mix

FPC plating default: Same PAD with different light tuning and Lens

Antoine JUNIQUE 36

IB-HIC-D003 Chip2(1) C9 IB-HIC-D003 Chip3(1) C9

IB-HIC-D003 Chip2(1) C10 IB-HIC-D003 Chip3(1) C10

Antoine JUNIQUE 37

FPC plating default

Antoine JUNIQUE 38

FPC plating default: IB-HIC-R004

IB-HIC-N005_chip1_D04IB-HIC-N005_chip1_D04

IB-HIC-N005_chip1_D04 Wire bond foot from IB-HIC-N005_chip1_D04

Antoine JUNIQUE 39

FPC plating default: IB-HIC-N005

MERCI DE VOTRE ATTENTION

QUESTIONS ?

Antoine JUNIQUE 40