Post on 16-Nov-2021
Enhancement Mode Strained (1.3%) Germanium Quantum Well FinFET (WFin=20nm) with High Mobility (μHole=700 cm2/Vs), Low EOT (~0.7nm) on
Bulk Silicon Substrate
A. Agrawal1, M. Barth1, G. B. Rayner Jr.2, Arun V. T.1, C. Eichfeld1, G. Lavallee1, S-Y. Yu1, X. Sang3, S. Brookes3 , Y. Zheng1, Y-J. Lee4, Y-R. Lin4, C-H. Wu4, C-H. Ko4, J. LeBeau3,
R. Engel-Herbert1, S. E. Mohney1, Y-C. Yeo4 and S. Datta1 1The Pennsylvania State University, University Park, PA, USA;
2Kurt J. Lesker Company, Pittsburgh, PA, USA; 3North Carolina State University, Raleigh, NC, USA
4Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan Email: ashish@psu.edu
Abstract
Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si0.3Ge0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm WFin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO2/Al2O3/GeOx gate stack achieving ultrathin EOT of 0.7nm with low DIT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si0.3Ge0.7 buffer on bulk Si substrate exhibiting peak μh=700 cm2/Vs, μh=220 cm2/Vs at 1013 /cm2 hole density. The s-Ge FinFETs achieve the highest μ*Cmax of 3.1x10-4 F/Vs resulting in 5x higher ION over unstrained Ge FinFETs.
Introduction
Ge pMOSFETs on bulk silicon substrate are a promising solution for improving the p-channel FET performance [1]. It is imperative to optimize the relaxed SiGe buffer counter doping with Phosphorus to achieve reliable isolation, maximize the uniaxial compressive strain in extremely scaled s-Ge fin to enhance μh, incorporate a gate stack with low EOT and DIT, and mitigate the sidewall roughness to prevent μh reduction. In this work, we investigate the optimum depth of location of the buffer Phos doping, tri-layer optimization of an ultrathin EOT gate stack without Si interlayer (IL) (Fig. 1), residual uniaxial strain retention in scaled fins of a s-Ge QW heterostructure (Fig. 2), and temperature dependent μh characterization in s-Ge fins to quantify the effective mobility degradation. We experimentally evaluate enhancement mode, scaled s-Ge QW FinFETs with WFin=20nm and 80nm fin pitch to demonstrate record μ*Cmax product of 3.1x10-4 F/Vs which is 2X higher than best reported till date.
Tri-layer Gate Stack
The tri-layer gate stack design and fabrication is shown in Fig. 3. GeOx is used to ensure low DIT at high-κ/Ge interface, Al2O3 cap layer mitigates HfO2-GeOx intermixing while HfO2 alleviates gate leakage. The oxide layer thicknesses have been systematically optimized using in-situ spectroscopic ellipsometry (Fig. 4) to enable ultimate EOT scaling whilst preserving functionality of each layer as confirmed using TEM and EDX (Fig. 5). Direct correlation of the Al2O3 and HfO2 thicknesses was established with the MOS capacitor C-V characteristics (Fig. 6). Excellent C-V response with ultrathin EOT of 0.72nm exhibiting the lowest gate leakage (Fig. 7, 8) was obtained with 17A HfO2/5A Al2O3/6A GeOx/p-Ge gate stack. The DIT analysis of these gate stacks (Fig. 9, 10) exhibited 4X better interface quality with thicker Al2O3 indicating more stable GeOx. Further, bulk trap density was reduced with Al2O3 thickness preventing HfO2-GeOx intermixing (Fig. 11).
s-Ge FinFETs
Fig. 12 shows the schematic of s-Ge QW heterostructure on 300mm bulk Si substrate along with the fabrication process for scaled FinFETs with scaled and tight fin pitch using SIT process. Optimization of chlorine-based dry etch resulted in vertical fin sidewall profile with WFin=20nm and fin pitch of 80nm as seen under high resolution cross section TEM (Fig. 13)
Phos Doped Buffer Design
s-Ge QW MOSFETs with Phos doping placed at 150nm and 250nm depth in the Si0.3Ge0.7 buffer were characterized to identify the optimum depth of buffer counter doping. Four
16.4.1 IEDM14-414978-1-4799-8001-7/14/$31.00 ©2014 IEEE
orders of magnitude lower IOFF was obtained for 250nm deep Phos doping compared to no Phos in buffer, with no degradation in ION (Fig. 14). This indicated effective counter doping of acceptor defects in relaxed Si0.3Ge0.7 buffer that otherwise result in parallel conduction and affect device isolation.
Si cap vs. GeOx passivation
The incorporation of an ultrathin Si interlayer to passivate high-κ/Ge interface results in high EOT and is further incompatible with 3D FinFET manufacturing process flow. Hence, the tri-layer gate stack with GeOx passivation after Si cap removal was deposited on s-Ge QW MOSFET and FinFET (Fig. 15). 2X higher ION was obtained with tri-layer gate stack at VDS=-0.5V, LG=5μm compared to with Si cap on s-Ge QW MOSFET. This can be attributed to 2.3X higher capacitance as measured using split-CV along with excellent modulation from accumulation to depletion. Hence, Si cap removal and tri-layer dielectric with GeOx passivation was key in realizing low EOT with low DIT on s-Ge QW.
E-Mode s-Ge QW FinFET
Excellent transfer characteristics with ION/IOFF=2x104 were observed on s-Ge QW FinFETs with WFin=70nm, 45nm and 20nm fabricated with SIT process after Si cap removal and deposition of tri-layer gate stack (Fig. 16(a)) showing advantage of Phos doping in buffer in addition to ultrathin EOT gate stack on high mobility s-Ge channel. The combined effect of confinement due to quantization from QW and fin patterning resulted in enhancement mode operation for WFin=45nm and 20nm s-Ge QW FinFETs (Fig. 16(b)). Experimental effective hole mobility (μeff) for s-Ge QW MOSFETs and FinFETs extracted from split-CV is summarized in Fig. 17. Highest peak μeff of 700 cm2/Vs obtained for s-Ge FinFET with WFin=20nm shows 2.6X improvement compared to unstrained Ge [2] which is attributed to the residual asymmetric uniaxial strain in the fin as a result of patterning. In addition, 2X degradation in μeff at Ns=1013 /cm2 from planar to Wfin=20nm indicated increased scattering in FinFET compared to planar which was investigated using temperature dependent measurements.
Sidewall Scattering
Temperature dependent transfer characteristics for s-Ge QW FinFET with WFin=20nm showed higher modulation with temperature in the subthreshold region compared to s-Ge QW MOSFET for the same gate stack (Fig. 17, 18). Low subthreshold slope of 96 mV/dec for planar MOSFET indicates low DIT at the high-κ/Ge top surface. In contrast, a degraded subthreshold slope of 150 mV/dec for s-Ge FinFET
is indicative of higher DIT response from the high-κ/Ge interface at the sidewall due to higher density of dangling bonds as a result of fin etch. Temperature dependent hole mobility as a function of hole density for planar MOSFET (Fig. 19) revealed Ns-1 dependence at 300K and 77K, which is characteristic of phonon scattering limited mobility. For s-Ge QW FinFETs, a much stronger Ns-2 dependence and temperature independent mobility with varying fin width (Fig. 20) revealed sidewall roughness as the dominant scattering mechanism. Optimization of fin etch to reduce the sidewall roughness is key to achieving even higher hole mobility in s-Ge QW FinFET.
Benchmarking and Conclusions
In conclusion, optimized tri-layer high-κ gate stack exhibiting ultrathin EOT=0.72nm and low gate leakage on Ge was developed. Uniaxially s-Ge QW FinFETs with WFin=20nm was demonstrated with high μPeak=700 cm2/Vs and 220 cm2/Vs at 1013 /cm2 with ultrathin EOT (Fig. 21). The high mobility s-Ge channel FinFET in conjunction with scaled gate stack resulted in the highest μ*Cmax product of 3.1x10-4 F/Vs (Table I) among high performance Ge FinFETs. The aforementioned enhancements in transport and gate stack resulted in 5X higher ION (Fig. 23) for s-Ge QW FinFET indicating promise for future alternate channel p-FinFET device technology.
Acknowledgement
This work was supported by the Pennsylvania State University Materials Research Institute Materials Characterization and Nanofabrication Laboratories and the National Science Foundation Cooperative Agreement No. ECS-0335765.
References
[1] S. Takagi et. al., IEDM 2003
[2] R. Zhang et. al., IEDM 2013
[3] R. Zhang et. al., IEDM 2012
[4] C. Choi et. al., EDL 2004
[5] R. Zhang et. al., IEDM 2011
[6] W. Bai et. al., VLSI 2003
[7] R. Xie et. al., IEDM 2008
[8] P. Hashemi et. al., EDL 2012
[9] K. Ikeda et. al., VLSI 2013
[10] Y. Kamata et. al., VLSI 2009
[11] B. Liu et. al., IEDM 2012
[12] P. Zimmerman et. al., IEDM 2006
[13] J. Mitard et. al., IEDM 2008
[14] R. Xie et. al., IEDM 2008
16.4.2IEDM14-415
s-Ge
SiGe Buffer
Phos Doping
Gate Metal
SiGe Buffer OptimizationPhosphorus doping;
→ Eliminate parallel channel
Channel StrainAsymmetric Uniaxial
strain; → μHole Enhancement
Ge-PassivationIn-situ H-Plasma clean Controlled sub-nm GeOx;
→ Low DIT Ultrathin EOT
Scaled FinFET20nm Fin Width;
→ Superior Electrostatics
Fig. 1: (a) Schematic showing device parameters critically optimized and enhanced for high performance p-channel 1.3% compressively strained Ge QW FinFET grown on Si0.3Ge0.7 buffer on 300mm bulk Si substrate.
εXX [%]0.5
-2
Phos DopingSiGe Buffer
TransverseX
YZ
(100)
Phos DopingSiGe Buffer
s-Ge QW
20 40-2
-1
0
1
Stra
in, ε
xx [%
]
Fin Width [nm]
Tran
sver
se
-2.5
-2.0
-1.5
Strain, εYY [%]
Longitudinal-3 -2 -1 00
200400600800
1000
Si(100)
(110)
(110)
Hol
e M
obili
ty [c
m2 /V
s]
Uniaxial Stress
(100)
Ge
[GPa]Fig. 2: Simulated transverse strain (εxx) profile for WFin=20nm Ge QW FinFET; color scale is in % strain, (b) Simulated transverse and longitudinal strain in channel as a function of fin width, (c) simulated hole effective mobility as function of uniaxial stress in channel for (100) and (110) orientated Ge and Si substrate.
p-GeMetal
HfO2 Al2O3 GeOx
1.5eV
2.5eV
Reduce DITLow temperature
process prevent Si-Ge interdiffusion
PreventHfO2-GeOxintermixing
Reduce gate leakage
EV
EC
EF
High-κ/Ge EOT Scaling Approach
PrecleanHydrogen Plasma Clean –250C, 100W, 30secOxygen Plasma GeOx– 250C, 125W, 2sec pulse50 cycle DI H2O PrepulseAl2O3/HfO2 250C ALDThermal Ni GateForming Gas Anneal, 300C, 10mins
Fig. 3: (a) Schematic showing band alignment for HfO2/Al2O3/GeOx/p-Ge gate stack, (b) MOS capacitor fabrication flow
0 1 205
1015202530
GeO
x Th
ickn
ess
[A]
Time [mins.]
Native GeOx
30 sec, 100W H-Plasma
T=250C0 2 4 60
2
4
6
5 10 15
Plasma-OFF
T=250C
GeO
x Th
ickn
ess
[A]
Time [mins.]
O-Plasma 125W, 2 sec Pulse
Plasma-ON
Cycle #
0 2 4 6 8 100
2
4
6
T=250C
Al2O
3 Thi
ckne
ss [A
]
Cycle #
Thermal ALDTMA Precursor + H2O
Nucleation delay
0 5 10 15 200
5
10
15
20
No Nucleationdelay
HfO
2 Thi
ckne
ss [A
]
Cycle #
Thermal ALDTDMAH Precursor + H2OT=250C
Fig. 4: In-situ spectroscopic ellipsometry data for (a) GeOx thickness showing native oxide etch with H-Plasma, (b) controlled GeOx formation with pulsed Oxygen Plasma, (c) Al2O3 cap layer deposition for diffusion barrier and nucleation layer and (d) HfO2 deposition by thermal ALD at 250C
2nm
17A HfO2
Ge
6A GeOx/5A Al2O3 0 1 2 3 4 5 6 7 8
Cou
nt [a
.u.]
Depth [nm]
Ge Al O Hf
Fig. 5: (a) High resolution cross-section TEM of HfO2/Al2O3/GeOx/Ge gate stack, (b) EDX line scan across the Ge gate stack
-2 -1 0 1 20
1
2
3
Cap
acita
nce
[μF/
cm2 ]
Gate Voltage [V]
75kHz to 2MHz
Al2O3
2A6A4A
20A HfO2/ Al2O3/ 6A GeOx/p-Ge
T=300KThickness
-2 -1 0 1 20
1
2
3
Thickness
17AHfO2/ 5A Al2O3/ 6A GeOx/p-Ge
T=300K
Cap
acita
nce
[μF/
cm2 ]
Gate Voltage [V]
75kHz to 2MHz
HfO2
30A
22A20A
Fig. 6: C-V characteristics of MOS capacitors on p-Ge with varying Al2O3 cap layer thickness and HfO2 thickness after in-situ H-Plasma clean and O-Plasma GeOx passivation. Low EOT of 0.72nm demonstrated.
-1 0 110-8
10-6
10-4
10-2
100
102
17A
30A
22A
J G [A
/cm
2 ]
Gate Voltage [V]
20A
HfO2
[3] 22A HfO2/2A Al2O3/3A GeOx
Thickness
103X
HfO2/5A Al2O3/6A GeOx/p-Ge
T=300K
Fig. 7: Gate leakage density vs. voltage for HfO2/Al2O3/GeOx/p-Ge MOS capacitors with varying HfO2 thickness indicating 103X reduction
0.0 0.5 1.0 1.5 2.010-7
10-510-310-1101103105
HfO2/Al2O3/GeOx
[2]
J G
[A/c
m2 ] @
VFB
-1V
EOT [nm]
Poly Si/SiO2
[5] Al2O3/GeOx
[6] HfO2 (w/ IL)
[4] HfO2 (no IL)
4XThis work
HfO2/Al2O3/GeO
x
Fig. 8: Gate leakage vs EOT benchmarking of HfO2/Al2O3/GeOx/p-Ge gate stack fabricated after H-Plasma clean with literature.
0.0 0.1 0.2 0.31012
1013
1014
17A 20A 22A 30A
DIT
[/cm
2 /eV]
Energy [E-EV]
EV
HfO2 Thickness
0.0 0.1 0.2 0.31012
1013
1014
4A 6AD
IT [/
cm2 /e
V]
Energy [E-EV]
EV
Al2O3 Thickness
4X
2 3 4 5 680
100
120
140
20 25 30HfO2 [A]
Hys
tere
sis
[mV]
Al2O3 [A] 0.7 0.8 0.9 1.0 1.10
2
4
6
DIT [x
1013
/cm
2 /eV]
EOT [nm]
DIT @ EV+0.27eV
Fig. 9: Extracted density of interface states using equivalent circuit method as function of energy in the bandgap for varying Al2O3 and HfO2 thickness.
Fig. 11: Hysteresis vs Al2O3 and HfO2 thickness with H-Plasma clean and Oxygen plasma oxidation indicating strong dependence on Al2O3 cap layer.
Fig. 10: Extracted density of interface states using equivalent circuit method vs. EOT at midgap
(a) (b) (c)
(a) (b)
(a) (b)
(c) (d)
(a) (b)
16.4.3 IEDM14-416
PrecleanS/D Pattern and Contact
Fin Patterning and RIE Etch
Gate Stack:In-situ H-Plasma Clean
Gate Pattern and Contact
Forming Gas Anneal, 300C, 10mins
O-Plasma GeOxAl2O3/HfO2 250C ALD
Si Substrate
500 nm Si0.7Ge0.3 Buffer
3nm Boron Modulation doping5 nm Si0.3Ge0.7 Spacer
10 nm Ge QW1 nm Si Cap
20nm 5E18 /cm3 Phos Doping
Si0.3Ge0.7 Buffer
2 μm Si0.3Ge0.7 Buffer
Depth=150nm, 250nm
10nm Ge QW
Si Substrate
500 nm Si0.7Ge0.3 Buffer
20nm 5E18 /cm3 Phos Doping
Gate Metal
Si0.3Ge0.7 Buffer
GeOx
Al2O3
HfO2
B-doping
Sour
ce
Dra
in
Gate FinWfin=20nm
200 nm Ge
Si0.3Ge0.7
Buffer
Wfin=20nmHfO2
Al2O3
/GeOx
10nm20 nm
Fin Pitch=80nm
Wfin=20nm
Ge Ge
Si0.3Ge0.7 Si0.3Ge0.7
-1 0 110-4
10-310-210-1100101102
Depth=250nm
Depth=150nm
I D [μ
A/μ
m]
Gate Voltage [V]
VDS=-0.5VLG=5μm
No PhosPhos Doping Depth
Planarw/ Si cap
Fig. 12: (a) Schematic of 1.3% s-Ge QW heterostructure with Boron modulation doped SiGe buffer in addition to Phos doping to reduce parallel conduction in the buffer, (b) fabrication process flow for s-Ge QW MOSFET and FinFET with varying fin width, (c) schematic of s-Ge QW FinFET with in-situ H-Plasma clean, oxygen plasma GeOx formation prior to high-κ deposition.
Fig. 13: (a) SEM showing long channel multi-fin device with WFin=20nm and fin pitch of 60nm, (b) cross section TEM showing s-Ge QW FinFET with 60nm fin pitch(c) HR-TEM showing vertical fin profile for 20nm WFin device
Fig. 14: Impact of Phosphorus doping depth in SiGe buffer on Id-Vg characteristics of s-Ge QW MOSFETs showing reducing IOFF with increasing Phos doping depth.
-1 0 110-5
10-3
10-1
101
103
Planar
I D [μ
A/μ
m]
Gate Voltage [V]
VDS
=-0.05V, -0.5VL
G=5μm
w/o Si cap
w/ Si cap
-2 -1 0 10.00.51.01.52.02.53.0
w/ Si cap
Cap
acita
nce
[μF/
cm2 ]
Gate Voltage [V]
w/o Si capf=1MHz
Planar
5A Al2O
3/22A HfO
2
125W O-Plasma,
2.3X
-2 -1 0 1
10-310-210-1100101102103
-0.5VLG=5μm
I D [μ
A/μ m
]
Gate Voltage [V]
Planar 70nm 45nm 20nm
VDS
=-0.05V
WFin
w/o Si cap
50 100-0.8-0.6-0.4-0.20.00.20.4 Depletion
Mode
V T,SA
T [V]
Fin Width [nm]
EnhancementMode
LG=5μmVDS=-0.5V
Fig. 15: (a) Id-Vg characteristic showing impact of Si cap removal prior to high-κ deposition indicating 2X increase in ION (b) Split CV measured at 1MHz on planar QW MOSFET showing 2.3X higher Cmax with Si cap removal and GeOx passivation.
Fig. 16: (a) Id-Vg characteristics w/o Si cap for high-κ/s-Ge QW MOSFET and FinFET at VDS=-0.05V, -0.5V showing high ION and excellent ION/IOFF=2x104, (b) VT,SAT vs WFin indicating enhancement mode operation due to confinement for QW FinFETs. A conservative WEff=No. of fins *(WFin+2TQW) was used
1012 1013
100
1000
2.6X
Planar WFin=70nm WFin=45nm WFin=20nm
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
Si UniversalUnstrained Ge [2]
2X
T=300K
-1 0 110-8
10-610-410-2100102104
-2 -1 0 1
I D [μ
A/μ
m]
Gate Voltage [V]
PlanarFinFETW
FIN=20nm
VDS=-0.5VL
G=5μm
300K, 150K, 77K
300K, 150K, 77K
VDS=-0.5VLG=5μm
100 200 30050
100
150
Planar FinFET
Subt
hres
hold
Sw
ing
Temperature [K]
WFin=20nm
[mV/
dec]
1012 1013
100
1000
1012 1013
N-1S
N-1S
77K 150K 300K
Hol
e M
obili
ty [c
m2 /V
s]
Hole Density [/cm2]
NS
Planar
N-1S
FinFET (WFin
=20nm)
N-2SNS
Fig. 17: Effective hole mobility of s-Ge QW MOSFET and FinFET with HfO2/Al2O3/GeOx gate stack showing 2.6X improvement compared to unstrained Ge
Fig. 18: (a) Id-Vg characteristics at VDS=-0.5V, LG=5um for high-κ/Ge QW MOSFET and FinFET with reducing temperature, (b) Subthreshold swing vs. temperature for planar MOSFET and FinFET
Fig. 19: Temperature dependent hole effective mobility vs hole sheet density for planar QW MOSFET and FinFET indicating Ns dependence.
100 200 300100
1000
T0
Planar WFin=70nm
Hol
e M
obili
ty [c
m2 /V
s]
Temperature [K]
WFin=45nm WFin=20nm
Ns=1013 /cm2
T-1
Wfin(nm)
μPeak(cm2/Vs)
εXX(%)
EOT (nm)
μPeak*Cox(x10-4)
This work 20 700 1.3 0.72 3.1
W. ChernIEDM,2012 18 850 2.5 1.5 1.9
R. Zhang IEDM,2013 800 380 2.5 0.8 1.6
J. MitardVLSI,2014 15 600 1.3 1.7 1.6
0.7 0.8 0.9 1.0 1.1
100
200300400500
WFin=20nmWFin=45nmW
Fin=70nm
[2]
[9]
[8]
[7]
μ Eff@
Ns=1
013/c
m2 [c
m2 /V
s]
EOT [nm]
[2]
This WorkBulk
Thick
Unstrained-Ge
0.1 1 10 100
1
10
100
1000
[2] s-GePPO GeO
|VGS
-VT| = 1V
[14]
[10][11] w/InAlP cap
[12][10]
I ON [μ
A/μ
m]
Gate Length [μm]
[13]
[11] w/Si cap
This work
|VDS
| = 1V
PlanarFinFET (WFIN=20nm
Fig. 20: Hole effective mobility vs. temperature for high-κ/s-Ge QW MOSFET and FinFET at Ns=1013 /cm2.
Table I: Benchmarking of key device parameters demonstrated in this work with other high performance s-Ge FinFETs till date.
Fig. 23: Benchmarking of ION of the s-Ge MOSFET and FinFETs with in-situ oxidation achieved in this work with other devices from literature.
Fig. 21: High field mobility of high-κ/s-Ge QW MOSFET and FinFET in this work vs. EOT, compared with s-Ge pMOSFETs w/o Si cap to date
(a) (b) (c)
(a)
(b) (c)
(a) (b) (a) (b)
(a) (b)
16.4.4IEDM14-417