Switched capacitor

– 1 –

Data Converters Switched-Capacitor CircuitsProfessor Y. Chiu

EECT 7327Fall 2014

Switched-Capacitor Circuits

Continuous-Time Integrator

– 2 –

EECT 7327Fall 2014

Vi VoSC

o in1 2 -∞

1v t =- v ξ dξ

V 1 1H s = s =-

V R C s

Approach: emulating resistors with switched capacitors

1 2=R C

Concept of Switched Capacitor

– 3 –

EECT 7327Fall 2014

q Ci = = V -V

1i= V -V

• A switched capacitor is a discrete-time “resistor”

• RC time constant set by capacitor ratio C2/C1 (match considerably better than R and C) and clock period T (flexibility)

RVA VB

C Ф2Ф2

Ф1Ф1

2eq,1 2 2

CT=R C = C =T

Non-overlappingtwo-phase clock

Switched Capacitors

– 4 –

EECT 7327Fall 2014

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

• Shunt- and series-type SCs are simple and cheap to implement

• Stray-insensitive SC requires 2 more switches, what’s the advantage besides being more flexible (i.e., w/ or w/o the T/2 delay)?

2-phase clock

Ф2Ф1

Series-typeShunt-type

C Ф2Ф2(Ф1)

Ф1Ф1(Ф2)

VA VB Stray-insensitive

Discrete-Time Integrator (DTI)

– 5 –

EECT 7327Fall 2014

2-phase clock

Ф2Ф1

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

What are the VTFs (z-domain) of these DTIs, assuming no parasitic capacitance is present?

Shunt-Type DTI

– 6 –

EECT 7327Fall 2014

Ф1(sample)

Charge conservation law (ideal):

Total charge on C1 and C2 during Ф1→ Ф2 transition must remain unchanged!

Ф2(update)

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

(n-1)(n)

(n)(n+1)

Shunt-Type DTI

– 7 –

EECT 7327Fall 2014

Ф1(sample)

Ф2(update)

1 i 1 o 2Q φ =V n C -V n C 2 1 o 2Q φ =0 C -V n+1 C

1 2 i 1 o 2 1 o 2Q φ = Q φ ⇒ V n C -V n C =0 C -V n+1 C

i 1 o 2 o 2V z C -V z C =-z V z C

-1 -1/2o 1 1

-1 -1i 2 2

V z C Cz zH z = =- or -

V z C 1-z C 1-z

Series-Type DTI

– 8 –

EECT 7327Fall 2014

Ф1(sample/update)

Ф2(reset C1)

V z C 1H z = =-

V z C 1-zVTF:

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

(n-1)(n)

Stray Capacitance

– 9 –

EECT 7327Fall 2014

• Strays derive from D/S diodes and wiring capacitance

• VTF is modified due to strays

• Strays at the summing node is of no significance (virtual ground)

Ф1 Ф2

Stray-Insensitive SC Integrator

– 10 –

EECT 7327Fall 2014

C 1H z =-

C 1-zVTF:

C zH z =+

• Capacitors can be significantly sized down to save power/area

• Sizes are eventually limited by kT/C noise, mismatch, etc.

C1 Ф2Ф2(Ф1)

Ф1Ф1(Ф2)

“Inverting” “Non-inverting”

SC Amplifier

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EECT 7327Fall 2014

CH z =+ z

• Non-integrating, memoryless (less the delay)

• Used in many applications of parametric amplification

VTF:Vi

– 12 –

EECT 7327Fall 2014

SC Applications

CT Filter

– 13 –

EECT 7327Fall 2014

CVi Vo

RLC prototype

Active-RC Tow-Thomas

CT biquad

SC DT Filter

– 14 –

EECT 7327Fall 2014

SC DTbiquad

C1 Ф2Ф2

Ф1Ф1

C4 Ф2

C3 Ф2Ф1

Ф1Ф2

Active-RC Tow-Thomas

CT biquad

Sigma-Delta (ΣΔ) Modulator

– 15 –

EECT 7327Fall 2014

Ф2Ф1

Ф1Ф2

+VR 1-b DAC-VR

DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC

Pipelined ADC

– 16 –

EECT 7327Fall 2014

SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC

1.5-bDAC

Φ1 C1

Φ1 C2

SC Common-Mode Feedback

– 17 –

EECT 7327Fall 2014

VBias Vcm

Vcm-VBias

CM sense amp can be replaced by a floating voltage source since the gain through the main op-amp is high enough.

SC Common-Mode Feedback

– 18 –

EECT 7327Fall 2014

Vcm-VBias

– 19 –

EECT 7327Fall 2014

Noise in SC Circuits

Noise of CT Integrator

– 20 –

EECT 7327Fall 2014

Noise in CT circuits can be simulated with SPICE (.noise)

2 22 N1 N2oN 1 2

V VV = f H f df+ f H f df+...

Δf Δf

Noise of SC Integrator

– 21 –

EECT 7327Fall 2014

SC circuits are NOT noise-free! Switches and op-amps introduce noise.

Ф1 Ф2 Ф1 Ф2 Ф1 Ф2

C1 Ф2Ф1

Ф1Ф2

Sampling (Ф1) Ideal Voltage Source

– 22 –

EECT 7327Fall 2014

• Noise is indistinguishable from signal after sampling• The noise acquired by C1 will be amplified in Ф2 just like signal

2 2∞ 22 N1 N2N 10

1 201 2

V VV φ1 = f + f H f df

Δf Δf

1= 4kTR +4kTR df

1+j2πf R +R C

VN12 VN2

Integration (Ф2)

– 23 –

EECT 7327Fall 2014

No simulator can directly simulate the aggregated output noise!

2 22 N3 N5N4N 34 5

V VVV φ2 = f + f H f df+ f H f df+...

Δf Δf Δf

2 2 21oN N N

CV = V φ1 +V φ2

H34(f)

R4VN42

Sampling (Ф1) Noise – Cascaded Stages

– 24 –

EECT 7327Fall 2014

VN12 VN2

R4VN42

• Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise (noise filtering).

• But parasitic loop delay may introduce peaking in freq. response, resulting in more integrated noise (noise peaking).

C2 C2'

C1 Ф1Ф2

Ф2Ф1

C1' Ф2Ф1

Ф1Ф2

Sampled Noise Spectrum

– 25 –

EECT 7327Fall 2014

• Total integrated noise power remains constant

• SNR remains constant

fs/2 fs 3/2fs0

fs 2fs0

– 26 –

EECT 7327Fall 2014

Non-ideal Effects inSC Circuits

Non-ideal Effects in SC Circuits

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EECT 7327Fall 2014

• Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap, accumulation-mode gate cap, etc.)– PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage

coefficients negligible for most applications)– Gate caps are typically good for up to 8-10 bits

• Switches (MOS transistors)– Nonzero on-resistance (voltage dependent)– (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb)– Switch-induced sampling errors (charge injection, clock feedthrough,

junction leakage, drain-source leakage, and gate leakage)

• Operational amplifiers– Offset– Finite-gain effects (voltage dependent)– Finite bandwidth and slew rate (measured by settling speed)

– 28 –

EECT 7327Fall 2014

Non-ideal Effects ofSwitches

Nonzero On-Resistance

– 29 –

EECT 7327Fall 2014

• FET channel resistance (thus tracking bandwidth) depends on signal level

• Usually (RonCS)-1 ≥ (3-5)·ω-3dB of closed-loop op-amp for settling purpose

0 VDDVout

VTnVTp

-1on ox DD th out

WR =μC V -V -V

Clock Bootstrapping

– 30 –

EECT 7327Fall 2014

• Small on-resistance leads to large switches → large parasitic caps and large clock buffers

• Clock bootstrapping keeps VGS of the switch constant → constant on-resistance (body effect?) and less parasitics w/o the PMOS

OutInM1

Ф1 Ф2

CMOS Bootstrapped NMOS

Simplified Clock Bootstrapper

– 31 –

EECT 7327Fall 2014

Pros• Linearity• Bandwidth

Cons• Device reliability• Complexity

OutInM1

Ф1 Ф2

Ф1Ф1

Switch-Induced Errors

– 32 –

EECT 7327Fall 2014

Channel charge injection and clock feedthrough (on drain side) result in charge trapped on CS after switch is turned off.

CgdCgs

• Clock feedthrough

• Charge injection

Clock Feedthrough and Charge Injection

– 33 –

EECT 7327Fall 2014

• Both phenomena sensitive to Zi, CS, and clock rise/fall time

• Offset, gain error, and nonlinearity introduced to the sampling

• Clock feedthrough can be simulated by SPICE, but charge injection cannot be simulated with lumped transistor models

Vin+Vth

Switch on Switch off

CgdCgs

Clock Rise/Fall-Time Dependence

– 34 –

EECT 7327Fall 2014

Vin+Vth

Switch on Switch off

CgdCgs

Clock feedthrough Charge injection

Fast turn-off

Slow turn-off

CΔV=- V

ox DD th in

C WL V -V -VΔV=-

2 C +C

gsin th

CΔV=- V +V

C +CΔV=0

Dummy Switch

– 35 –

EECT 7327Fall 2014

• Difficult to achieve precise cancellation due to the nonlinear dependence of ΔV on Zi, CS, and clock rise/fall time

• Sensitive to the phase alignment between Ф and Ф_

CMOS Switch

– 36 –

EECT 7327Fall 2014

• Very sensitive to phase alignment between Ф and Ф_

• Subject to threshold mismatch between PMOS and NMOS

• Exact cancellation occurs only for one specific Vin (which one?)

Same size for

P and N FETs

Differential Signaling

– 37 –

EECT 7327Fall 2014

• Signal-independent errors (offset) and even-order distortions cancelled

• Gain error and odd-order nonlinearities remain

Balanced diff. input

Switch Performance

– 38 –

EECT 7327Fall 2014

ithDDox

on μQ

VVVWLμC

1ΔV Charge injection:

Bandwidth:S

Son CL

Q L CΔV 1 L≈ =

BW 2 C μQ 2μPerformance FoM:

Technology scaling improves switch performance!

On-resistance:

Leakage in SC Circuits

– 39 –

EECT 7327Fall 2014

• I1 – diode leakage (existing in the old days too)• I2 – sub-threshold drain-source leakage of summing-node switch• I3 – gate leakage (FN tunneling) of amplifier input transistors• Leakage currents are highly temperature- and process-dependent; the

lower limit of clock frequency is often determined by leakage

Ф1 Ф1Ф2 Ф2

Φ1 = “high”, Φ2 = “low”

Ф2 Ф2

Ф1 Ф1

I2 I1I3

DS Leakage

– 40 –

EECT 7327Fall 2014

Vi+ Vo

Ф1 Ф1e

• 0.13-μm CMOS• A0 = Gm·Ro = 90dB

• Ro ≈ 2MΩ

• Rleak ≈ 0.6V/3μA

≈ 0.2MΩ• A0 = Gm·(Rleak//Ro)

≈ 70dB

OutInM1

VDD = 1.2V

VSS = 0V

Gate Leakage

– 41 –

EECT 7327Fall 2014

• Direct tunneling through the thin gate oxide

• Short-channel MOSFET behaves increasingly like BJT’s

• Violates the high-impedance assumption of the summing node

GS ox GSI ∝WL exp -t exp V

Switch Size Optimization

– 42 –

EECT 7327Fall 2014

• To minimize switch-induced error voltages, small transistor size,slow turn-off, low source impedance should be used.

• For fast settling (high-speed design), large W/L should be used, and errors will be inevitably large as well.

Guidelines

• Always use minimum channel length for switches as long as leakage allows.

• For a given speed, switch sizes can be optimized w/ simulation.

• Be aware of the limitations of simulators (SPICE etc.) usinglumped device models.

– 43 –

EECT 7327Fall 2014

Non-ideal Effects ofOp-Amps

Non-ideal Effects of Op-Amps

– 44 –

EECT 7327Fall 2014

• Offset

• Finite-gain effects (voltage dependent)

• Finite bandwidth and slew rate (measured by settling speed)

Offset Voltage

– 45 –

EECT 7327Fall 2014

1 i 1 o os 2Q φ =V n C + V n -V C

2 os 1 o os 2Q φ =-V C + V n+1 -V C

1o i-1

C zV z = V z

Ф1 Vos

Ф1 Ф1Ф2 Ф2

Vi = 0

1i o o os

CV =0 ⇒ V n+1 -V n = V

Autozeroing

– 46 –

EECT 7327Fall 2014

1 i os 1 os 2Q φ = V n -V C -V C

2 os 1 o os 2Q φ =-V C + V n -V C

V z CH z = =

• Also eliminates low-frequency noise, e.g., 1/f noise

• A.k.a. correlated double sampling (CDS)

Chopper Stabilization

– 47 –

EECT 7327Fall 2014

Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise chopper-stabilized differential switched-capacitor filtering technique,” IEEE Journal of Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981.

Vi VoA1

Chopper Stabilization

– 48 –

EECT 7327Fall 2014

Also eliminates DC offset

voltage of A1

Vi VoA1

Chopper-Stabilized Differential Op-Amp

– 49 –

EECT 7327Fall 2014

• Integrators/amplifiers can be built using these op-amps

• Some oversampling is useful to facilitate the implementation

Ideal SC Amplifier

– 50 –

EECT 7327Fall 2014

• Closed-loop gain is determined by the capacitor ratio by design

• But this is assuming X is an ideal summing node (the op-amp is ideal)

Vi ∞

Finite-Gain Effect in SC Amplifier

– 51 –

EECT 7327Fall 2014

o 1 1 1 2

CL1 2i 2 2 2

V C C C +C1A = = ≈ 1-

C +CV C C C A1+C AVi A

1 i 1 x 1 1 2

x 1 o 1 x 1

Q φ = V φ -V φ C +0 C

V φ =V φ =-V φ A

1 2 i 1 x 1 o x 2Q φ = Q φ ⇒ V C =-V C + V -V C

2 x 2 1 o 2 x 2 2

o 2 x 2

Q φ =-V φ C + V φ -V φ C

V φ =-V φ A

o xV =-V A

– 52 –

EECT 7327Fall 2014

Practical Issues

Analog vs. Digital Supply Lines

– 53 –

EECT 7327Fall 2014

Sharing sensitive analog supplies with digital ones is a very bad idea.

Analogcircuits

Digitalcircuits

VDD CBP

diΔV =L

dt R dΔV =i RA DD L RV =V -ΔV -ΔV

Analog vs. Digital Supply Lines

– 54 –

EECT 7327Fall 2014

• Dedicated pads for analog and digital supplies

• On-chip bypass capacitors help (watch ringing)

• Off-chip chokes (large inductors) can stop noise propagation at board level

Analogcircuits

Digitalcircuits

VDD CBP

“Supply” Capacitance

– 55 –

EECT 7327Fall 2014

• Any summing-node stray capacitance can be a potential coupling path.

• VDD, VSS, substrate, clock line, and digital noises, body effect, etc.

• Fully differential circuits help to reject common-mode noise and coupling.

…VDD

strayo

CΔV =ΔV

“Supply” Capacitance

– 56 –

EECT 7327Fall 2014

• Avoid connecting bottom-plate parasitics to the summing node

• Avoid crossing other signal lines with the summing node

• Shielding can mitigate substrate noise coupling

n substrate

p+p well

Clock Generation

– 57 –

EECT 7327Fall 2014

• Clock-gated ring structure

• Non-overlapping time determined by inverter delays, sensitive to process, voltage, and temperature (PVT) variations

• DLL is an alternative, often used in high-speed designs

CLK Ф2

Switched capacitor

Engineering

Transcript of Switched capacitor

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