Lecture 1 - introduction

(p4)

(roughly half the length of the smallest transistor,say 0.2µm IC with λ=0.1 µm )n λ or

(p5)

(p6)

(p7)

(p8)

(p9)

(p10)

(p11)

Factors affecting variable costs: wafer size ; wafer cost ; Moore’s Law(Gordon

(p12)

Lecture 2 – CMOS Logic & layout Revisited

(p1)

(p2)

(p3)

• If Vds > Vgs-Vt, then Vgd< Vt and no inversion layer can exist at the drain terminal. The channel is said to be ‘pinched-off ’. The transistor is operating in saturation.

(p4)

Second-Order Effects

Comparison Between with/without Body Effect

(p5)

Channel Length Modulation

Example

(p6)

(p7)

Subthreshold Conduction

(p8)

MOS SPICE Model

• Is it possible to achieve an arbitrary high gm by increasing Wwhile maintaining ID constant ? ⇒ gm = ID/(ζVT)

(p9)

(p10)

(p11)

CMOS Design Rules

•Design rules, also referred to as layout rules, can be considered as

a prescription for preparing the photomasks that are used in the

fabrication of integrated circuits.

•The rules provide a necessary communication link between circuit

designer and process engineer during the manufacturing phase.

•The principal objective associated with the rules is to obtain the

circuit with optimum yield in as small a geometry as possible

without compromising reliability of the circuit.

(p12)

(p13)

(p14)

(p15)

I/O Cells

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(p18)

(p19)

(p20)

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(p24)

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(p26)

n+

source.

(p27)

Latch-Up Precaution & Guard-Ring

• Let us take a look at the following figure to get more insight.

n+ n+ n+ n+ n+ n+p+ p+ p+ p+ p+ p+

n-well n-well

PIN

ND PD

where p-substrate and n-wells are connected to GND and VDD, respectively.

Now, let us assume 2V positive trigger voltage on the PIN ( it means that we

give VDD+2 volts on the PIN ). In other words, V(ND) = VDD+2 which also

means that the voltage increases the reverse bias of the junction of N+-Psub

only and it will not lead to any current injection. However, since the voltage of

PD over VDD+0.7V which means that the junction of p+- n-well is forward-

biased ( because N-well is connected to VDD ), which means there are a lot of

holes flowing into the well from p+ and the holes then flowing into the substrate

since the junction of well and substrate is reverse-biased. Notice that the

resistance of the substrate is very high which also means that the ‘real’ ground-

volt place is where there is a substrate contact only. Referring to the figure, we

know that before the holes flowing to the substrate contact, they can flow

underneath other junctions such as grounded N+-Psub as shown in the figure.

p-sub

++ +

---- + +-

(p28)

If the current is large enough, the junction can be forward-biased and form a

PNP+NPN SCR latch-up circuit.

So, how can we prevent latch-up ? Firstly, we shall know that it is inevitable

that the voltage on a pin will be over VDD since the behaviour of a bondwire is

like a inductor. It also means that the latch-up problem only results from I/O

cells and it also means that the forward bias is inevitable for the junction of P+ -

N-well and it indicates that there will be a lot of holes flowing into the substrate.

Our problem now becomes how can we collect the holes efficiently ? Obviously,

the solution is going to be putting substrate contacts between the right n-well

and the right NMOS. Since these substrate contacts always form a ring shape,

we can call it as “guard-ring”.

Notice that the same analysis can be applied for the case of negative

trigger voltage.

Guide lines –

We can now classify a device into 2 categories :

1. Latch device: all NMOS’s , PMOS’s are latch devices.

2. Trigger device: NMOS’s, PMOS’s connected to pin, and N+ on the substrate

and P+ on a well. Thus, a trigger device must be a latch device.

Therefore, the guide lines to prevent latch-up are :

( I ). Trigger devices of PMOS or P+ on a well must be surrounded with

1. Substrate (well) contacts to prevent the positive trigger voltage to

NMOS’s.

2. Pseudo collectors to prevent nearby NMOS trigger devices be latched

by a negative trigger voltage.

(p29)

( II ). Trigger device of NMOS or N+ on P-sub must be surrounded with

1. Pseudo collectors to prevent the negative trigger voltage to PMOS’s.

2. Substrate (well) contacts to prevent nearby PMOS trigger devices be

latched by a positive trigger voltage.

( III ). PMOS latch devices must be surrounded with pseudo collector to prevent

nearby NMOS trigger devices be latched by a negative trigger voltage.

( see ( I )-2 )

( IV ). NMOS latch devices must be surrounded with substrate contact to prevent

nearby PMOS trigger devices be latched by a positive trigger voltage.

( see ( II )-2 )

Summary for Latch-Up & Guard-Ring

(p30)

Lecture 3 – Low-Level Design Entry & Cell Library Design

(p1)

Design entry, Schematic entry, and Netlist• Design entry – describe a microelectronic system to a set of electronic

design automation ( EDA ) tools.

• Schematic entry ( schematic capture ) – A type of design entry process

involves schematics which show how all the components are connected

together, the connectivity of an ASIC.

• Netlist – an ASCII or binary version of the schematic that describes the

design.

• Design entry can also be with text files, such as hardware description language ( HDL ).

Schematic Entry • The recommendations can lead to problem since the corner points of the

shapes do not always lie on a grid point.

(p2)

Terms employed in circuit schematics

Hierarchical Design

(p3)

Cell Library

• Problems with cell library –1. There are no naming conventions.

2. There are no standards for cell behaviour.

• Hard-macro – includes placement information.

• Soft-macro – only gives connection information.

Names

• Each of the cells that you place on an ASIC schematic has

a cell name.

• Each use of a cell is a different instance of that cell, and we

give each instance a unique instance name.

• We represent each cell instance by a picture or icon, also

known as a symbol.

(p4)

Schematic Icons and Symbols

(p5)

Vectored Instances and Buses

Netlist Screener ( schematic screener )- A program that analyzes a schematic netlist for simple errors including:

1. Unconnected cell inputs.

2. Unconnected cell outputs.

3. Nets not driven by any cells.

4. Too many nets driven by one cell.

5. Nets driven by more than one cell.

(p6)

Netlist Screener ( cont. )

• Most schematic-entry programs work on a grid.

• This simplifies the internal mechanics of the schematic-entry

program.

• It also makes the transfer of schematics between different EDA

systems more manageable.

• Most schematic-entry programs allow you to find components by

instance name or cell name.

• Some schematic editors can complete automatic naming of

reference designators or instance names.

• A schematic-entry program can use a terminal attribute to

determine which cell terminals are output terminals and which

terminals are input terminals.

Schematic-entry Tools

• Normally the primitive cells in a library are locked and cannot be

edited. ( You may edit it whereas you have to make a copy and edit

the copy and also rename it )

• Some design-entry tools are more sophisticated and allow users to

create their own libraries as they complete an ASIC design.

(p7)

Back-Annotation

• After you enter a schematic you simulate the design to make sure it

works as expected. This completes the logic design. Next you move

to ASIC physical design and complete the layout. Only after you

complete the layout do you know the parasitic capacitance and

therefore the delay associated with the interconnect.

• The post-route delay information must be returned to the

schematic in a process known as back-annotation.

Low-Level Design Languages

• Two major problems with schematic entry –

1.Making changes to a schematic can be difficult.

2.There were no standards on how symbols should be drawn or

how the schematic information should be stored in a netlist.

⇒ Design-entry tools based on TEXT are better than on graphics ??

• Some common low-level design languages –

1. ABEL – a PLD programming language from Data I/O.

2. CUPL – a PLD design language from Logical Devices.

3. PALASM – a PLD design language from AMD/MMI.

(p8)

An example of ABEL

(p9)

An example of ABEL ( cont. )

An example of CUPL

(p10)

An example of CUPL ( cont. )

(p11)

An example of CUPL ( cont. )

(p12)

An example of PALASM

(p13)

EDIF ( Electronic Design Interchange Format )

• The structure of EDIF is similar to the Lisp programming language or the

Postscript printer language( a very hard language to read and almost

impossible to write by hand )

An EDIF Schematic Icon

• EDIF is capable of handling many different representations. The example is

another view of an inverter that describes how to draw the icon.

(p14)

Bounding Box Problem

• Icons with large bounding boxes create 2 problems in Cadence Composer –

1. Highlighting all or part of a complex design consisting of many closely spaced

cells results in a confusion of overlapped highlight boxes.

2. Large boxes force strange wiring patterns between cells that are placed too

closely together when Composer’s automatic routing algorithm is employed.

CFI Design Representation( CAD Framework Initiative )

• CFI is working on the definition of standards for design representation ( DR ).

• The CFI 1.0 standard has tackled the problems in the area of definitions and

terms for schematics by defining an information model ( IM ) for electrical

connectivity information.

(p15)

CFI Connectivity Model using EXPRESS-G

(p16)

CFI 1.0.0 Base Connectivity Model ( BCM )

Cell Library Design -

(p17)

A Typical Standard Cell Library Includes

• Core cells ( for random logic )

- combinational circuits, sequential circuits

• I/O cells

- input, output, inout, power

• Hard-macro ( Soft-macro ?! )

- RAM, ROM

Design Flow for Standard Cell

• Cell specification

• Circuit design

• Layout design

• Circuit and RC extraction

• Parameter extraction

• Views generation

• Test key design and fabrication

• Parameter measurement

(p18)

Design Under Constraints

• Constrained W/L values for transistors

• Constrained layout parameters

- Minimum pin grid

- Cell boundary

- Power line width, power line location

- Available metal layouts

- Equal cell height

• Constrained driving capabilities

Cell versus Models

• There will be many models for a cell

• Useful cell models include

- Synthesis model

- Simulation model

(p19)

Common Core Cells• Combinational cells

- Buffers : buffer, inverted buffer, balanced buffer,

tri-state buffer, clock buffer

- Gates : AND, OR, NAND, NOR, XOR, AOIs, OAIs

- Adders / Subtractors

- Multiplexers

• Sequential cells

- Flip-flops : D-type, T-type…..

- Latches

• Misc. cells

- Schmitt trigger ( inverted / non-inverted )

Common I/O Cells• I/O pads

- CMOS, TTL

- Input only, output only, bi-directional

- Pull-up / pull-down resistor, tri-state

• Power pads

- for analog blocks, for digital blocks

• Special pads - crystal oscillator pads.

(p20)

Important Parameters of a Cell• DC characteristics

• AC characteristics

• Function table

• Cell information

• Pin description table

• Propagation delay

• Timing information

DC Characteristics

Parameters Minimum Maximum ConditionsPower Supply 2.7V 3.3V

Low level input voltage

-0.33V 0.2xVDD Guaranteed input low voltage

High level input voltage

0.7xVDD VDD+0.5V Guaranteed input high

voltageJunction

temperature00C 1000C

(p21)

AC Characteristics• Timing measurement conditions

VDD = 5.0V, Temperature = 250C, Process = typical case.

• AC timing definitions

1. Setup time – The time a signal must be maintained at a

specified input before a transition occurs at another specified input.

The value given is the necessary minimum.

2. Hold time – The time a signal must be retained at a specified

input after a transition occurs at another specified input. The value

given is the necessary minimum.

Data

Clk

Tsetup

Data

Clk

Thold

3. Minimum signal width – The time interval between the 50%

points of the leading and trailing edges of the HIGH or LOW pulse

of a pulse waveform.

4. Release time for clear / set – The minimum time Clear or Set is

released before the clock transitions active.

• Propagation Delay Time

When the input directly affects the output, the propagation delay

time is the time in ns from 50% point of the input to the 50% of the

output.

input

output

Tplh

50%

50%10%

90%

Tr

Tphl

50%

50%10%

90%

Tf

Data

ClkTwh

Twl

Clk

SetTrel

(p22)

(p23)

Cell Information• Driving capability

• Gate Equivalents

• Cell width

• Power

Function Table

(p24)

Propagation Delay• Performance equations ( linear model )

• Propagation delays for sample loads

Pin Description Table• Pin name

• Pin capacitance

• Pin usage

(p25)

VDD / VSS Pad Combinations

Timing Information

(p26)

Cell Library Design Guide-Line

• Delay equation -

Tpd = Krf * Ta * Va * ( A0 +Ac * Cload )

Trf = Krfoutput * Ta’ * Va’ * ( Trf0 +Trfc * Cload )

where

Tpd : Propagation delay.Trf : Output transition time ( rising / falling ).Krf : Input transition time coefficient ( derating factor ) for delay.Ta : Temperature coefficient for delay. ( Ta = 1 when T = 250C,

and Ta = Tpd ( T0C ) / Tpd ( 250C ) ).Va : Power voltage coefficient for delay. ( Va = 1 when VDD=5V,

and Va = Tpd ( VDD ) / Tpd ( 5V ) ).A0 : Cell pin to pin intrinsic delay ( ns )Ac : Load coefficient ( ns / load )Krfoutput : Input transition time coefficient.Ta’ : Temperature coefficient for output transition time.Va’ : Power voltage coefficient for output transition time.Trf0 : Intrinsic output transition time ( ns )Trfc : Load coefficient for output transition time.( ns / load )Cload : cell output load.

• Typical case for the cell simulation is defined as : VDD=5V, Ta = 250C, Process = typical case.

• Common simulation condition :Process : High current, Typical current , Low current.VDD : 4.5V, 5.0V, 5.5V.Temp : 00C, 250C, 700C.

• Output load of a cell includes :1. Device load – the input capacitance of the following device. 2. Routing wire load – corresponding to chip size.

Lecture 9 – Design for Testability &Synopsys Test Compiler

(p1)

Facts for Testability

• To achieve the highest fault coverage results in the shortest period of time, select full scan.

• Full scan influences your design more than partial scan in terms of area and performance.

• Full scan provides improved diagnostic capabilities during manufacturing test compared with partial scan.

Selection Criteria

• How large is my design ?

• What are my testability requirements ?

• What is my performance constraint ?

• What is my area constraint ?

(p2)

Test Compiler Streamlined Methodology –Design Considerations

Outline

1. Synchronous Designs

2. Latches

3. Internal Three-State Nets

4. Bidirectional Ports

5. Clock Configuration

(p3)

I. Synchronous Designs

II. Latches

• Well suited to the internal scan test

• Generally achieve high fault coverage

Test compiler supports two modes

1. Sequential cell mode ( default )

2. Pseudo-combinational cell mode( transparent latch )

( dc_shell > set_scan false –transparent cell )

can be design, cell or instance

(p4)

Sequential Latch Mode- for full-scan, a latch cell must have a scan equivalent

Pseudo-Combinational Latch Model( Transparent )

• Scannable Latches

• Valid Nonscan Latches

- Fully testable in partial scan designs only.

- All of the faults can be detected during sequential pattern generation.

- The enable pin must be defined as a clock.

1. The enable pin and the driving network are not testable.

2. The enable must not be defined as a clock.

3. The transparent latch is considered to be a combinational element.

(p5)

III. Internal Three-State Nets

Examples

• Bus contention

• Bus floating

Scan Insertion – add three-state disabling logic to each internal three-state net.

u3

u2

u1

d3

d2

d1

c3

c2

c1

o1

Internal Three-State Net

u3d3

d1

d2

e3

e1

e2

o1

Internal Three-State Net with Disabling Logic

u1

u2test_se

(p6)

• The pins of the gating logic that is driven by the scan enable signal are untested.

• If the design already contain logic that prevents bus floating / contention during scan shift, you can usedc_shell > insert_test –no_disable

III. Internal Three-State Nets ( cont. )

ATPG Conflicts

1. Invalid bus decoding logic

2. Parallel drivers

3. Combinational feedback loop

(p7)

Examples

d3

d2

d1

enable

o1

Invalid bus decoding logic

enable

in1

outb

Parallel drivers

outa

d2

Combinational feedback loop

out1

e2

en

d1

tm

(p8)

Maximizing Fault Coverage

1. Avoid unreachable drivers- be ware of one and only one driver is active in

the circuits.

2. Use pull-up / pull-down resistors- in order to avoid bus floating

a0

b1

a1

a0

b1

a1

en_b

en_a

out1

Design with Unreachable Three-State Driver

c0

b0

c0

b0

en_c

out0

(p9)

IV. Bidirectional Ports

d

e

clk

q

io

clk

d

e io

o

Bidirectional port driving a sequential cell

Sequential cell controlling birectional enable

• Bidirectional ports as clock ports ?- Synopsys does not support.

• Bidirectional ports as scan input ports ?- complexity involved in configuration and

timing issues.⇒ Synopsys does not encourage.⇒ If it is necessary for your design, note that

1. Guarantee that the bidirectional cell is always in input mode during scan shift. By

(p10)

i. Gating the bidirectional enable signal with the scan enable signal.

ii. dc_shell > set_test_hold …

2. Ensure that data is applied to the bidirectional port prior to the active edge of the clock.

• Bidirectional ports as scan output ports ?- Synopsys does not encourage. However, if

you have to do that, make sure the above two points.

• Combinational Feedback Loops- If you use bidirectional pad cells in your

design, you can cause combinational feedback loops to occur.

d io

Combinational feedback loop through bidirectional pad cell

(p11)

V. Clock Configuration• Clocks that are employed during scan testing

must be generated from a single top-level port.

• Clocks that are employed during scan testing must be generated in a single tester cycle.

• Clocks that are employed during scan testing must not be bidirectional ports.

• Clocks that are employed during scan testing cannot be the result of multiple clock inputs.

Combinational Clock Gating

dc_shell > set_signal_type test_scan_enable IN3ORdc_shell > set_test_hold 1 IN3

out2

out1

in2

in1

clkIN3

(p12)

Sequential Clock Gating

- sequential generated clocks ( divided clocks... ) must be added test mode logic to bypass.

out2

out1

in2

in1

clk

out2

out1

in2

in1

clk

tm

⇓