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Lecture 3: Layout

•  CMOS Enhancements •  Scalable rules •  Poly ordering •  Design Partitioning •  Floorplanning

Layout

•  Min. feature size expressed in terms of λ = f/2 –  E.g. λ = 0.3 µm in 0.6 µm process

•  Lambda λ rules are conservative –  All dimensions rounded to integer multiple of λ –  Industry employs micron (vendor) rules instead (more compact)

Area=money •  Why use λ rules

–  Easy scaling –  Same layout can be resized by scaling λ

•  MOSIS (www.mosis.org) –  Low cost (relative) fabrication service –  Services Academia, industry and government –  Shared masks

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Simplified Design Rules

•  Conservative rules to get you started

Gate Layout

•  Layout can be very time consuming –  Design gates to fit together nicely –  Build a library of standard cells

•  Standard cell design methodology –  VDD and GND should abut (standard height) –  Adjacent gates should satisfy design rules –  nMOS at bottom and pMOS at top –  All gates include well and substrate contacts

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Example: NAND3

•  Horizontal N-diffusion and p-diffusion strips •  Vertical polysilicon gates •  Metal1 VDD rail at top •  Metal1 GND rail at bottom •  32 λ by 40 λ

Standard Cells

•  Uniform cell height •  Uniform well height •  M1 VDD and GND rails •  M2 Access to I/Os •  Well / substrate taps •  Exploits regularity

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Wiring Tracks •  A wiring track is the space required for a wire

–  4 λ width, 4 λ spacing from neighbor = 8 λ pitch •  Transistors also consume one wiring track •  Estimate area by counting wiring tracks

Stick Diagrams •  Stick diagrams help plan layout quickly

–  Need not be to scale –  Draw with color pencils or dry-erase markers

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Example: O3AI

•  Sketch a stick diagram for O3AI and estimate area – 

( )Y A B C D= + + g

Optimal POLY Ordering

•  Define Euler path –  Uninterrupted path that traverses each edge of the graph EXACTLY ONCE

•  Find Euler path in PDN and PUN graph below starting at x. .

x

What is the order of inputs for the common Euler paths?

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Example

•  Determine the graph for the PDN and PUN for •  Find the Euler path .

A B

C D

E F

F = (A + BC + D)(E + F)

C B A E F D

GND

VDD

F

C B D F E A

GND

VDD

F

Stick Diagram

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Y-Diagram: Design Partitioning

Physical Design

datapath

controlleralucontrol

ph1

ph2

reset

memdata[7:0]

writedata[7:0]

adr[7:0]

memread

memwrite

op[5:0]

zero

pcen

regwrite

irwrite[3:0]

memtoreg

iord

pcsource[1:0]

alusrcb[1:0]

alusrca

aluop[1:0]

regdst

funct[5:0]

alucontrol[2:0]

Example: 8-bit processor

PCMux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction[15: 11]

Mux

0

1

Mux

0

1

1

Instruction[7: 0]

Instruction[25 : 21]

Instruction[20 : 16]

Instruction[15 : 0]

Instructionregister

ALUcontrol

ALUresult

ALUZero

Memorydataregister

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite[3:0]

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWriteControl

Outputs

Op[5 : 0]

Instruction[31:26]

Instruction [5 : 0]

Mux

0

2

JumpaddressInstruction [5 : 0] 6 8

Shiftleft 2

1

1 Mux

0

32

Mux

0

1ALUOut

MemoryMemData

Writedata

Address

PCEn

ALUControl

•  Divide and Conquer –  Create Hierarchy –  Organize system recursively into

modules •  Regularity

–  Reuse modules wherever possible

–  Ex: Standard cell library •  Modularity:

–  Create well-formed interfaces –  Allows modules to be treated as

black boxes •  Locality

–  Physical and temporal

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MIPS Floorplan and Layout

datapath2700 λ x 1050 λ

(2.8 Mλ2)

alucontrol200 λ x 100 λ

(20 kλ2)

zipper 2700 λ x 250 λ

2700 λ

1690 λ

wiring channel: 30 tracks = 240 λ

mips(4.6 Mλ2)

bitslice 2700 λ x 100 λ

control1500 λ x 400 λ

(0.6 Mλ2)

3500 λ

3500 λ

5000λ

5000 λ

10 I/O pads

10 I/O pads

10 I/O pads

10 I/O pads

Pitch Matching

•  Synthesized controller area is mostly wires –  Design is smaller if wires run through/over cells –  Smaller = faster, lower power as well!

•  Design snap-together cells for datapaths and arrays –  Plan wires into cells –  Connect by abutment

•  Exploits locality •  Takes lots of effort

A A A A

A A A A

A A A A

A A A A

B

B

B

B

C C D

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MIPS Datapath

•  8-bit datapath built from 8 bitslices (regularity) •  Logic at top drives control signals to datapath

Slice Plans •  Slice plan for bitslice

–  Cell ordering, dimensions, wiring tracks, arrange cells for wiring locality

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Summary

•  Process Enhancements •  Lambda rules overview •  Stick diagrams and Poly ordering •  Hierarchical design •  Floorplanning