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Experiment-3 enhancement load inverter

Schematic

Layout

(W/L) Driver = (W/L) Load =2.5

Wnd = Wnl= 5 λ, Lnd = Lnl = 2 λ.

Vdd=Vgg=1.2V. 

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Experiment-3 enhancement load inverter

wavform

Vtc characteristic

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Experiment-3 enhancement load inverter

  Noteworthy Observation:

  In general we consider K R = ((W/L) Driver / (W/L) Load) =1 thus no effect is seen when we

vary both simultaneously. But when we keep (W/L) Driver =2.5 and vary (W/L) Load= 1.67

then the rise and fall time increases but on doing opposite i.e. when we keep ((W/L) Load

=2.5 and vary (W/L) Driver = 1.67 then the rise and fall time of the output voltage

decreases.

  The effect of varying the supply voltage can be marginally seen only the current drawn

from the circuit increases which in turn increases power consumed.

  5. Conclusion/Learning Outcome:

  An exact inverted input at the output is not observed as for high input the output obtained

is not zero but VOL =0.410V while for low input voltage the output is not high but VOH

=0.680V.

 

Current only flows when the driver transistor is in ‘linear or saturation mode’. But the

effect of the leakage current can be seen as when the driver transistor is in off state the

output should be high(vdd) but we see that some voltage drop occurs within the circuit

through nmos driver thus the output voltage is VOH =0.787V when input voltage is zero.