DC DC converters for energyharvesting

Shouri Chatterjee

Department of Electrical Engineering,IIT Delhi

June 15, 2017

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DC-DC boost converter

+−

Rs

Vin

L

T1

T2

Cbatt

T1

T2

+

-

Vout+−

Rs

Vin

L

T1 T2

Cbatt+

-

Vout

te tc

Vout/Vin =

√L/CRs

tanh(te/τe/2)tan(ω0tc/2)

tc has to be very small to get voltage boost.Overlapped clocking leads to shoot-through losses.

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DC-DC converter for scavenging

RF or piezo energy converted to DC. This DC powerneeds to be pushed into a battery.A 300 nW sensitive, DC-DC converter for energyscavenging applications.Not constant frequency, constant duty cycle. Timingis optimized for minimum switching and minimumresistive losses.

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Chip overview

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Core DC-DC converter

−

+

Transducer

vB L vS VD

RLCD

S1

S0CBVR

Delay(TD)

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Core DC-DC converter

−

+

Transducer

vB L vS VD

RLCD

S1

S0CBVR

Delay(TD)

vB

VR

S0 control

Inductor current (iL)

TD

Vmax

Vmin

VRTD/L

slope = VR/L

slope = −VD/L

time

‘Wait’ Phase

‘Energize’ Phase‘Dump’ Phase

TW

S1 control

TS

TD

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Design optimizationThe switching period:

TS ≈ TW ≈RST 2

D2L

(1)

Resistive losses and switching losses:

Pres = ATD

L(2)

Psw = BL

T 2D

(3)

Optimal comparator delay:

TDopt ≈3

√6L2Ceff

V 2D

V 2R

1Ren

=3

√6L2Ceff

V 2D

PinRS

1Ren

(4)

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Harvest mode

L VSW

−

+

VREF

VBUCKET

MN0MP0

VDET

CD

ET

INPUT DC

Driver

DriverNDRIVE

PD

RIV

E

−+

CB

UC

KE

T

time

VBUCKET VREF

NDRIVE

S3

Zero current detector

Over voltage comparator

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Zero-current detector

S5

MN1

PDRIVE

-+

Monoshoton falling

RS

Latch Q

PDRIVE

NDRIVE

Zero current detector

edge

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Overall architecture

VDET VSTORE

LCBUCKET

INPUT DC

VBUCKET

RS

AM

PLE

CS

AM

PLE

VSW

Controller

Load

VCOINVDDSW

CDET CSTORE

VCORE

VBG

comparator

VSTOREOK

ND

RIV

E

PDRIVE

MN0MP0

MP1

S6

VREF

VCORE

Load-enable

Power monitor,

and oscillatorpre charge, Power

Management

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Designed current consumption

BlockCurrent Supply Voltage

(nA) domain range

Power management, power monitor(Skewed comparator†, ‘detach-OK’ comparator†, 12 Vdd 1-2

band-gap and current reference generator)

Oscillator† and frequency divider 7 Vcore 1

‘OV-comp’† 12 Vcore 0.9-1.3

‘ZCD’ <2 VD 1.5

‘Load-enable’ comparator† 5 VD 1-2

† Constant bias current is used.

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Measured efficiency

10−10

10

2030

40

5060

70

80

Effi

cien

cy[%

]

90

100

Available Power [µW]102101100

Overallefficiency

Extraction efficiency

‘OV-Comp’bias = 0.5 nA

‘OV-Comp’bias = 5 nA

efficiencyOverall

Extraction efficiency

‘OV-Comp’bias = 5 nA

‘OV-Comp’bias = 0.5 nA

10−1 100 101 102

Available Power [µW]

0

10

20

30

40

5060

70

80

Effi

cien

cy[%

]

90100

Vstore = 1.8 VVstore = 1.5 V RS= 20 kΩ

RS= 5 kΩ

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Efficiency

RS= 5 kΩ

RS= 20 kΩRS= 10 kΩ

Load current [µA]10−1 100 101 10210−2

0

10

20

30

40

50

60

70

80E

ffici

ency

[%]

100

‘OV-Comp’bias = 0.5 nA

‘OV-Comp’bias = 5 nA

Extraction efficiency

Harvesterefficiency

90

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Measured power consumption

0 0.5 1 1.5 2 2.50

10

20

30

40

50

60

VCOIN

or VDET

[V]

Curr

ent consum

ption [nA

]

Sleep mode

Harvest mode

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Load duty cycling

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How good are we?

ISSCC 2010 JSSC 2010 TI ISSCC 2012 ThisRamadasa Carlson bq25504 J.-P. Im work

Process 0.35 µm 0.13 µm - 0.13 µm 0.18 µmOutput 1.8 V 1 V 1.8-5.5 V 2 V 1-2 V

Power needed - - > 1 µW - > 300 nWCurrent - - 330 nA - 60 nA

Minimum input 20 mV 20 mV 80 mV 40 mV 70 mVη at 2 µW - - 38% - > 50%

η at 10 µW - - 78% - 75%Peak η 58% 75% 93% 62% 78%Startup Mechanical External Self Noise External

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Oscillator controlled buck-boost

LS0 S3

S1 S2

CD

VD

Transducer

Oscillator Mono-shotEnergize

TE = KvB

vB

Mono-shotDump

TD = KVD

S0 and S2 controlS1 and S3 control

CB

Rising Edge

Oscillator triggers all activities. No comparator needed.

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Arriving at the f0 for MPPTSearch

N=9, Sample open circuit voltage, enable U1, BC = N-1

Skip 2 cycles of U1, enable SAR, reset oscillator

Set code = max(COSC)/2, span = max(COSC)/4

At U1

o/p rising edge

is VOSC = 0 ?

BC = 0 ?

NoYes

No

Yes

C02C02NC0

B0B1BN

SearchU1VD

IBIAS

Monoshot

COSC

VOSC

code = code+span

span = span/2

and reset oscillator

BC = BC-1

Disable U1, enable energize/dump from oscillator, wait for search phase

COSC

Oscillator

output

0 4 8 12

100

200

300

Comparator output cycle

Search start,

Previous

codeSearch finished

Capacitorcode

MSB is set to one

code = code-span

span = span/2

and reset oscillator

S5S6

BC = BC-1(a)

(c) (b)

50

150

250

2 6 10

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Managing multiple power sources

L S3

S1 S2

CD

VD

Transducer PV

Oscillator PV

Mono-shot

Energize

TE = KvB

Mono-shot

Dump

TD = KVD

Oscillator PZ

Oscillator RF

Arbiter

Transducer PZ

CB PZ

vB PZ

Transducer RF vB RF

CB RF

Rectifier

RectifierM.N and

CB PV

vB PV

Logic

Logic

S0 PV

S0 PZ

S0 RF

S0 PV, S0 PZ, S0 RFand S2 control

S1, S3

controlMPPT

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Constant peak inductor current

C

RCVMvB

vBV-to-I

Monoshot

IOUT = VDR

kVD

C

‘Energize’

S0, S2 control

IOUT = vBR

V-to-I

S1, S3 control

( From oscillator or comparator )

slope = vBL

slope = VDL

Inductor currentS1, S3 control

S0, S2 control

RCVMVD

VX

VX

U2

U3

(a)

(b) (c)

Energizephase

Dump phase

Wait phase‘Dump’

Monoshot

Energize and dump pulse generation

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Voltage to current conversion

VX

VD

VX

VX + VG

VG R

VG

IOUT

+

−

+

−

+

−M1

M2

M3 M4

VD

vB VR

starvedCurrent

(a) (b)

En-RF

En-PVEn-PZ

Schematics for monoshot generation and V-I

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Harvesting efficiency

10−2

10−1

100

101

102

20

30

40

50

60

70

80

90

Eff

icie

ncy [

%]

Power [µW]

High efficiency over a very wide range of input powerlevels.Not achieved in our earlier work.Not achieved by any of our competitors.

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PV Start-up circuit

PV input

Charge pump

B

L

VD

VDDCP

CD

Cp

Oscillator

PPb

P Pb

B

Level shifter

B

Regulator

Bb

Bb

Dickson charge pump clocked by a ring oscillator

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Power management architecture

CBPZ

vBPZ

CBRF

CBPV

vBPV

VPV

L

VPZ

VRF

Vstore

CD Cstore

VD

CDD

VDD

LDO

VLDO

0.5 hour clock

Vstore-OK

Vstore-OKVD IR1

vBRF

Switches & Sampler

−+

vB

U1

VR

Oscillator PV

Start-up

VPV ,VRF

Energize/dump

pulse gen. References

IR1 to IR5Vbg

Comparator

Digital controller

with SAR

vB ,VD ,VDD

vBPV,vBPZ

,vBRF,VDD

VDD ,Vbg

Gates of power switches

IR2,3,4

CR

E1 to E3

E1

E2

E3

Voltage doubler

& driver

VD

VD-OK

Oscillator piezo

Oscillator RF

En

clock

S0 PV

S0 PZ

S0 RF

S1 S2

S3

En-VDD

Rectifier

RectifierRF

VPV ,VPZ ,VRF ,Vbg

+

−Piezo

IR5

IIN

LP LN

S4

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Complete system with WSN

Controller DC-DC Core

Start-up

Sampler Oscillator bank

with MPPT

Wake up PLL

PA

OOK

Sensor ADC MemoryLF oscillator

51.5 MHz 2.47 GHzLCB CD Cstore

Cs

Rext

Data

RF PZ PV

Transducers

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Designed integrated circuit

1.5 mm×3 mm chip contains three energy harvesterswith MPPT, wireless sensor node with memory,wake-up radio, frequency synthesizer, transmitter.

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Measured power consumption

1 2 3 4 5 6 7 8

10

30

50

70

90

Pow

erco

nsum

ptio

n[n

W]

1 Digital controller

2 Oscillator

3 Comparator

4 References

5 VD-OK comparator

6 Vstore-OK comparator

7 Energize/dump generation

Voltage doubler & gate driver

8 Resistive and other losses

2.26

0.154 0.3 0.3

62

85

Most of the power is wasted as resistive and switching losses.

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Efficiency

0.2 0.4 0.6 0.8 1

20

40

60

80

100

Input voltage (VPV ) [V]

IIN = 12 µA

IIN = 1.2 µA

IIN = 0.12 µA

Extraction efficiency

Harvester efficiency

20

40

60

80

100

Available Power [µW]10010.01

Extraction efficiency

Harvester

RF

Piezo

0.1

Available Power [µW]100101

20

40

60

80

100

Combined

Individual

Extraction efficiencyHarvester efficiency

-40 0 40 80

Temperature ( C)

Extraction efficiency

Harvester efficiency

PIN = 0.1 µW

PIN = 1 µW

PIN = 10 µW

efficiency

RS

=160

kΩ

RS

=13.

9kΩ

RS=4 kΩ

RS=20 kΩ

20

40

60

80

100

%%

%% Measured

with piezo

Harvester and extraction efficiency. Overall η > 80%.

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Performance improvement becauseof oscillator

0

200

400

600

Available Power [µW]

1 1000.01

Comparator

Oscillator

Freq

uenc

y[H

z]

0

20

40

60

80

Available Power [µW]

1 1000.01

With comparator

With oscillator

Effi

cien

cy[%

]

Oscillator tracks the comparator frequency!

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Conclusions

Developed state-of-the-art DC-DC converters thatcan scavenge energy from energy sources as weakas 300 nW.Modified energy harvesting architecture allows us toharvest from powers as low as 10 nW.

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More reading

G. Chowdhary, S. Chatterjee, “A 300-nW sensitive,50-nA DC-DC converter for energy harvestingapplications”, IEEE Transactions on Circuits andSystems - I, vol. 62, no. 11, Nov. 2015, pp.2674-2684.G. Chowdhary, A. Singh, S. Chatterjee, “An 18-nA,87% efficient solar, vibration and RFenergy-harvesting power management system with asingle shared inductor”, IEEE Journal of Solid StateCircuits, in press.

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