SIDDHARTH INSTITUTE OF ENGINEERING &TECHNOLOGY: PUTTURELECTRONICS & COMMUNICATON ENGINEERING

LESSON PLAN

Academic Year/Sem: B. Tech III-II Sem. Ref: A. Pucknell, Wayne Wolf, K. Lal Kishore

Subject: VLSI Design Subject code: 15A04604

Branch: E.C.E.

Module Topics coveredHours

Name of the book Page NoL T

UNIT I

Module 1

Introduction: Basic steps of IC fabrication, MOS transistors – MOS transistor switches- Basic gates using switches, working polar transistor Resistors and Capacitors transistor

8 1 A. Pucknell,K. Lal Kishore

1-20, 5,

37-39.

Module 2

Basic Electrical Properties of MOS and Bi-CMOS: threshold voltage; MOS design equations: Ids–Vds, Threshold Voltage, Body effect, Channel length gm, gds, figure of merit ω0; Pass transistor,

6 A. Pucknell,K. Lal Kishore

45,25,28,

31-34.

Module 3NMOS, CMOS Inverter analysis and design Various pull ups loads, Bi-CMOS Inverters. 4 A. Pucknell 43,

40, 48.

UNIT II

Module 1

Basic Circuit Concepts: Capacitance, resistance estimations, Sheet Resistance Rs, MOS Device Capacitances, routing Capacitance, Analytic Inverter Delays, Driving large Capacitive Loads, Fan-in and fan-out.

5 1 A. Pucknell

85-11286-90,94,98108.

Module 2

VLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout2μm CMOS Design rules for wires, Contacts and Transistors

5 1 A. Pucknell, K. Lal Kishore

82,55-71.

Module 3Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling.

5 A. Pucknell76,

113-132.

UNIT III

Module 1Gate level Design: Logic gates and other complex gates, Switch logic, Alternate gate circuits.

5 A. Pucknell, K. Lal Kishore

137,135-137.

Module 2Physical Design: Floor-Planning, Placement routing, Power delay estimation, Clock and Power routing.

5 1 Wayne Wolf240, 243,

260, 265,286

UNIT IV:

Module 1

Subsystem Design: Shifters, AddersALUs, Multipliers, Parity generators, Comparators, Counters, High Density Memory Elements Arrays,

8 2 A. Pucknell, K. Lal Kishore

229,221,193

151,232.

Module 2

VLSI Design styles: Full-custom, Standard Cells, Gate-arrays, FPGAs, CPLDs, Design Approach for Full-custom and Semi-custom devices.

7 K. Lal Kishore 179-201

UNIT V

Module 1

VHDL Synthesis: VHDL Synthesis, Circuit Design Flow Circuit Synthesis, Simulation Layout, Design capture toolsDesign Verification Tools.

7 1 A. Pucknell, K. Lal Kishore

262,267,299,302.

Module 2Test and Testability: Fault-modeling and simulation test generation, design for testability, Built-in self-test.

5 1 K. Lal Kishore 291,295,300.

TOTAL 70 8

S.No Name of the book Author1. “Essentials of VLSI circuits and systems”, PHI, 2013 Edition. Kamran Eshraghian, Eshraghian

Douglas and A. Pucknell

2. “VLSI Design”, IK Publishers K. Lal Kishore and V.S.V. Prabhakar 2002.

3. “Modern VLSI Design”, Pearson Education, 3rd Edition, 1997. Wayne Wolf

SIDDHARTH INSTITUTE OF ENGINEERING & TECHNOLOGY:: PUTTUR

ELECTRONICS & COMMUNICATON ENGINEERING

VLSI DESIGN

UNIT I

Module 1IMPORTANT QUESTIONS

1. Explain the fabrication of a CMOS transistor 2. i). Give the steps of NMOS fabrication along with neat diagrams. ii) What are the thermal aspects of processing NMOS and CMOS devices 3. Explain the MOS Transistor operation with the help of neat sketches in the following modes i) Enhancement mode . ii) Depletion mode. 4. i) Explain the operation of Bi-CMOS inverter? Clearly specify its Characteristics. ii) Describe how the Bi-CMOS inverter performance can be improved. 5. i). Derive Ids & Vds relation. ii). An-MOS Transistor is operated in the Active region with the following parameters Vgs= 3.9V; Vtn = 1V; W/L = 100; μnCox = 90 μA/V2. Find its drain current and drain source resistance. 6. a). List the advantages of IC. b). State Body effect. c). State the different types of CMOS process

BITS

1. _______ present VLSI circuits use MOSFETs instead of BJTs.2. _________ type of process used for CMOS. 3. The basic processing steps involved in BICMOS process is _____4. _____ condition satisfies to operate NMOS in resistive region. 5. ______ is scaling factor for thickness of the dioxide 6. The typical area capacitance value between gate to channel in 5µm technology pf x 10-4/µm is ___________ 7. _____ layer is having large capacitance value 8. ______ device has high speed 9. In ______ model logic levels are degraded by Vt 10. Peripheral capacitance is also called as ___________ capacitance11. Total wire capacitance is ______________.12. _______ device has high output driving current

13. Permittivity of free space ε0 is __________.

ASSIGNMENTS1. i). With neat diagrams, explain the different steps in p-well fabrication of CMOS transistors. ii). Draw a twin tub structure and explain. 2. i). With neat sketches explain how NPN transistor is fabricated in Bipolar process.

ii). Describe the two commonly used methods for obtaining integrated capacitor.

Module 2

IMPORTANT QUESTIONS

1. i). Explain the operation of Bi-CMOS inverter? Clearly specify its characteristics. ii). Describe how the Bi-CMOS inverter performance can be improved.

2. a). Explain pass transistor. b). Define Latch up. c). Discuss the four generations of Integration Circuits. d). Illustrate the additional steps involved in twin-tub process e). Give the basic process steps for IC fabrications. f). State Moore’s law.

BITS

1. BJT is a _________ controlled device 2. _____ type of process used for CMOS? 2. For NMOS fabrication ______ substrate is used 3. For saturation region Ids is ______4. BICMOS inverter has ___________ noise margin5. In Ion lithography the total number of ions entering into the target is called____________6. _______ device has high input impedance7. ______ layer is having large capacitance value8. For saturation region Ids is __________________9. For PMOS fabrication __________________substrate is used10. Total diffusion capacitance is___________11. The thickness of the thick oxide (sio2) layer in fabrication of MOS is____µ12. In Ion lithography the total number of ions entering into the target is called__13. In n-well process for the fabrication of CMOS the substrate used is ______type14. The speed power product of any MOS technology is measured in__________

ASSIGNMENTS

1. i). Derive Ids & Vds relation. ii). An-MOS Transistor is operated in the Active region with the following parameters Vgs= 3.9V; Vtn = 1V; W/L = 100; μnCox = 90 μA/V2. Find its drain current and drain source resistance.

Module 3IMPORTANT QUESTIONS

1. i) What are the different forms of pull ups? ii) Derive an equation for Trans-conductance of an n channel enhancement MOSFET operating in active

region. 2. a) State why NMOS technology is preferred more than PMOS technology.

BITS1.For depletion mode MOSFET threshold voltage _________2.The technology which is characterized by high speed _______3.Latch up in CMOS device can be avoided by _________4. Material used for metallization is ____________5.Material used for Gate oxide in MOS technology ___________6.Poly silicon is ___________ material7. Silicide is combination of ______________8.In modern CMOS fabrication the pattern on each layer is created by __________9.The advantage of twin tub process____________10. VLSI stands for _____________11. Implant is used in ____

12. One advantage of FET is _______________________

ASSIGNMENTS

1. Derive an equation for Trans-conductance of an n channel enhancement MOSFET operating in active region.

2. State why NMOS technology is preferred more than PMOS technology.

UNIT IIModule 1

IMPORTANT QUESTIONS1. Define and explain the following i). Sheet resistance concept applied to MOS transistors and inverters. ii). Standard unit of capacitance. 2. i) Explain about driving large capacitive loads?

ii). Derive an equation for o in MOS transistor. 3. a). Define sheet resistance model b). Give the names of different types of routing capacitance.

BITS

1. High packing density exist in _______________ technology

2. _________ is in yellow color

3. Switch logic circuits are _____

4. Resistance of metal layer is ____________

5. The minimum possible channel length in MOS device is _________µm

6. The sheet resistance value of metal in 1.2 µm technology is ________Ω

7. The total number of gate inputs that are driven by a gate output is called as_

8. The length to width (L/W) ratio of the channel of an MOS device is called as

9. The pull up to pull down ratio for an NMOS inverter driven by another inverter is______

10. Stick diagrams are used to convey the ______information through the color code

11. _________ colour is used to represent the poly silicon in stick diagram

12. ________ colour is used to represent VDD and VSS

ASSIGNMENTS

1. Sheet resistance concept applied to MOS transistors and inverters. 2. Standard unit of capacitance. 3. Explain about driving large capacitive loads?

Module 2

IMPORTANT QUESTIONS

1. i). Explain the VLSI Design flow. ii). What is a stick diagram? Draw the stick diagram of a three input CMOS NAND gate. 3. i). What is lambda based design rules? Explain design rules for wires and MOS transistors ii). Explain 2µm-based design rules for wires with neat sketches.3. i). Explain about rules for drawing Stick's Diagram. ii). Draw the schematic and layout for 2-input NAND gate 4. Giving explanation i). Draw the stick diagram for CMOS inverter? ii). Design a stick diagram for CMOS xor gate. 5. i). Sketch a stick diagram for CMOS inverter. ii). Give the various colour coding used in stick diagrams iii). What is rise time estimation? iv). Sketch stick diagram for NMOS inverter. v). What is stick diagram. vi). List the types of design rules.

BITS

1. _____rules are proposed by Mead and Conway used to design multi project.1. In Scaling, gate area is scaled by the factor of _________

2._______ are the wiring capacitances3.For 1:1 NMOS inverter Rs is 1000Ω channel resistance is _____________4.Orange colour is used in stick diagrams NMOS design for ____________5.For 4:1 NMOS inverter Rs is 1000Ω channel resistance is _____________6.Aspect ratio Z is___________7._________ is in yellow colour8.Implant is used in___________________ 9.To form N type transistor ____________layers used

11.For λ based design rule, minimum separation of metal 1 layers are_______ 12. __________ is not a MOS layers

13. __________is Stick Diagram

ASSIGNMENTS1. i) Explain Lambda -based design rules with neat figures. ii) Draw a stick diagram and mask layout of 8:1 NMOS inverter circuit. Both Input and Output points should be Poly silicon layer. 2. i) Explain about rules for drawing Stick's Diagram.

ii) Draw the stick diagram for CMOS inverter?

Module 3IMPORTANT QUESTIONS

1. i). Derive the expression for CMOS inverter rise time and fall time ii). Draw the layout diagram for CMOS inverter? 2. i). Calculate the rise Calculate the rise time and fall time of the CMOS Inverter (W/L)n=6 and (W/L)p=8, VDD=3.3v.total output Capacitance =150Pf. ii). Calculate on resistance of circuit shown in fig 1 from Vdd to gnd if n channel sheet resistance Rsn=104per square and p-channel sheet resistance Rsp =3.5x104 per square.

3. i). List the limitations of scaling. ii). Describe Scaling.

BITS

1. To form P type transistor _______________layers used2. Implant is indicated in the colour of _____________3. In NMOS inverter buried contact used in____________4. _____________ is in brown colour5. For λ based design rule, minimum separation of metal 2 layers are_____6. Channel resistance R is___________7. The max length of communication wire for poly silicon in 5µm technology is __λ8. ___________ scaling factor for VDD.9. __________ following layer is not used to form transistor.10. The colour of a poly silicon gate is ____________11. A stick diagram is schematic representation of circuit at ________ level.12. Minimum spacing between well-well is ___________.13. The delay unit ι =

ASSIGNMENTS 1. Design a layout diagram for the NMOS logic shown below y= [(a+b).c]’. 2. Derive the expression for CMOS inverter rise time and fall time

UNIT IIIModule 1

IMPORTANT QUESTIONS

1. i). Draw the CMOS implementation of 4X1 mux using transmission gates? ii) Write short notes on switch logic?

2. Design a 2 input multiplexer using CMOS transmission gate and explain it. 3. i). Explain pseudo NMOS logic gate? ii). Give its advantages & disadvantages? 4. i) Explain dynamic CMOS logic gate? ii) Give its advantages & disadvantages? 5. Write short notes on

i) Domino CMOS logic. ii) NORA logic.

6. a). Give the different symbols for transmission gate? b). What is the purpose of alternate gate circuits? c). Draw the structure of NORA CMOS cascaded gates? d). Draw the basic structure of dynamic CMOS gate? e). What is basic transmission gate? f). Define Domino CMOS logic?

BITS

1. In ______ logic PMOS net is in dual topology with NMOS net2. Pass transistor logic uses transistors as _______ to carry logic signals3. _______ logic requires clock signal4. The two phases in dynamic CMOS are_______5. CMOS static complementary gate have two transistor nets____6. _______ is an electronic element 7. Transmission gate is also known as ______ gate8. A tri state gate consists______ states9. Tristate gates are used in ______10. Static CMOS design based on______11. Dynamic CMOS logic uses _____ transistors12. Dynamic CMOS logic has_______ switching speed13. _______ CMOS logic has high performance14. Dynamic CMOS logic circuits are more sensitive to_______15. In Domino CMOS logic ______ transistor used16. Full form of NORA_______17. _____ CMOS logic is alternative to Domino CMOS logic18. Dynamic CMOS circuits have _____ distribution problem19. The extension of the Domino logic is______20. The major drawbacks of DCVS logic are______

ASSIGNMENTS

1. i). Clearly explain the AOI implementation using CMOS design style with neat sketches? ii). Explain about DCVS logic?

2. Design a 2 input multiplexer using CMOS transmission gate and explain it.

3. Explain pseudo NMOS logic gate?

Module 2

IMPORTANT QUESTIONS

1. Discuss in detail about floor planning in VLSI? 2. Mention different types of alternate gate circuits available. Explain CMOS domino logic in detail using an

example. 3. a). What is meant by clock distribution? b). List the different routing techniques? 4. a) What is floor planning? b) What is placement?

BITS

1. The arrangement of blocks of the net list on the chip is known as_____2. Standard cells are placed within each block to implement function of the block is ___________3. The wired connections are made between cells & blocks is known as____4. CLB stands for_______5. The steps in physical design flow in order is

(i) Floor planning (ii) placement (iii) Partioning (iv) Routing6. Expand ASIC _____7. LUTs present in _____8. The geometric representation of a circuit is called______9. A poor placement design uses _____ area10. _______ are the types of placement techniques11. In the floor planning phase, the _____ cells are positioned on the layout12. The routing space is partitioned into rectangular regions called_______.13. point-to- point connections between pins on the blocks is made in _______routing14. __specifies the loose route of a wire through different regions in the routing space 15. ___________ routing includes channel routing and switchbox routing. 16. A _____ gate is an idealized or physical device implementing a Boolean function. The simplest family

of logic gates using bipolar transistors is called_____17. ________ Capacitors across the power supply pins are used in PCB design to reduce the power supply

noise. 18. The job of clock routing design is to control _____ from the clock pad to all memory elements.19. The major obstacle to clock distribution is ____________

ASSIGNMENTS

1. i). What is routing? Explain about different routing techniques? ii). Explain the concept of clock distribution and power distribution?

UNIT IVModule 1

IMPORTANT QUESTIONS1. Design and explain the working of the following circuits using CMOS transistors.

i) Two bit counter ii) zero/one cross detector

2. With relevant circuit diagram explain the operation of i). Content addressable memory

ii). Flash memory 3. Write short notes on

a) Comparatorsb) Multipliers & Counters

4. a).What is a shifter? b). Draw the circuit of comparator. c). What is parity generator.

BITS

1. The level of any particular design can be measured by ____________ 2. Any bit shifted out at one end of data word will be shifted in at the other end of the word is called ____________ 3. The subsystem design is classified as ________ 4. The larger system design must be partition into a sub systems design such that _______5. To simplify the subsystem design, we generally used the ____ 6. System design is generally in the manner of ___7. Structured design begins with the concept of ____ 8. Any general purpose n-bit shifter should be able to shift incoming data by up to no. of places are ___9. For a four bit word, a one-bit shift right is equivalent to a ___10. The type of switch used in shifters is ___________11. The carry chain in adder is consist with _______________12. VLSI design of adder element basically requires __________ 13. The heart of the ALU is _________ 14. For fast arithmetic operations, the multipliers & dividers are to use architecture of _____________

15. The number of bits increases in comparator then the 16. The standard cell for an n-bit parity generator is 17. The parity information is passed from one cell to the next and is modified or not by a cell depending on the state of the ______ 18. The two output signals of comparator remain at zero as long as the two bits being compared are _________ 19. In the comparator the two inputs if A>B then the outputs are _____ 20. In the comparator the two inputs if A<B then the outputs are _______

ASSIGNMENTS

1. With neat circuit diagram explain the operation of i). Barrel shifterii). Carry look ahead adder

2. a) Draw the circuit diagram for 4x4 barrel shifter. b) Implement ALU functions with adder.

Module 2IMPORTANT QUESTIONS

1. a). What is FPGA .Draw and explain basic structure of FPGA. b). Implement the following functions using PAL.

i). f(a,b,c,d)=ab+bc & f(a,b,c,d)=ab+cd2. i). Implement a 3 bit synchronous counter using PAL? ii). Write briefly about:

a). Channel led gate arrays b). Channel less gate arrays with neat sketches3. i) Differentiate between PROM, PAL, and PLA? 4. a). List the steps in ASIC design flow? b). Draw the 6 –transistor SRAM cell? c). Explain the principle of DRAM? d). Define data path subsystem? e). Give the Xilinx FPGA architecture? f). Draw the one transistor DRAM cell? g). What is FPGA? h). What is standard cell based ASIC design?

BITS

1. The width of n bit comparator is ___, Where w is the width of leaf cell 2. ONE/ZERO detection circuits for word width of less than 32 bits is the 3. Detecting all ones or all zeros on wide words require ______ 4. In zero/one detector, the delay to the output is proportional to (N- width of the word) ____5. Binary counters are used to cycle through a sequence of _____ 6. The clocking of each stage of ripple counter is carried out by the___ 7. A design that requires high density memory is usually__8. The main characteristics of on chip memory is ____ 9. DRAM has a ______10. SRAM has a ___ 11. On chip memory is comes under the category of ____ 12. On chip memory usually in the order of ____13. Where the design is of moderate complexity and time to silicon is of paramount importance then the

probably suitable approach is _____14. A single time programmable FPGA is the type of ______ 15. FPGA can be programmed as per the ___ 16. The logic cells in FPGA contains _________ 17. The individual cells of FPGA are interconnected by _______ 18. The programming in fuse-based FPGAS is done by ______ 19. A slow rate control is used in the I/O block of CPLD because of ___

20. A macro cell in CPLD is composed of _____________

ASSIGNMENTS1. a). What is CPLD? Draw its basic structure & give its applications?

b). Explain the working of SRAM cell? 2. a). Draw the typical standard – cell structure and explain it?

b). Explain the working of DRAM cell?

UNIT VModule 1

IMPORTANT QUESTIONS

1. a). What is meant by signature analysis in testing? Explain with an example? b). What are the different types of DFT techniques? Explain? 2. Write notes on any two

i) BISTii) Boundary scan testing iii) BILBO

3. a). What is ATPG? Explain a method of a generation of test vector? b). Explain the terms controllability, observability & fault coverage?

4. Explain the following with respect to CMOS testing: i) Fault simulation ii) Statistical fault analysis iii) Compare the circuit level & logic level simulations5. a). What is the need for testing? b). Give some examples of fault models? c). Define BILBO & IDDQ testing? d). Define VHDL synthesis? e).What is fault sampling?

BITS

1. VHDL was developed for the VHSIC components to _____ 2. The primary abstraction in VHDL is called _____ 3. Each port declaration of design entity in VHDL includes a ____ 4. The component declarations in VHDL include an in face description for each of _____5. VHDL provides high-level definition and simulation of ______ 6. The design is commenced with a _________ 7. Logic optimization is used to improve the logic to meat ______ 8. Logic synthesis systems are very useful for _____ 9. Which of the following synthesis converts RTL description to a set of registers and combinational logic

______ 10. RTL description are captured using _______ 11. The most detailed and accurate simulation technique is ______ 12. Circuit level simulators are characterized by ______ 13. Switch level simulators merge logic simulators techniques with some circuit simulation techniques by

modeling transistors as _____ 14. Switch - level simulators are combination of ____ 15. Interactive graphic editors are used to capture the ______ 16. In layout synthesis generally two phases are required they are _____ 17. The traditional method of capturing a digital system design is ____ 18. Many design systems generally used HDL because of _____ 19. A layout editor might interface to a design rule checking program to ____ 20. Simulations with delays are used to check the ____ 21. The last step in the design process is ______ 22. For MOS circuits the dominant faults are due to____ 23. During testing of VLSI system (Indicate the false statement___ )

ASSIGNMENTS

1. a). Discuss any two system techniques used for system level testing? b). What is the need for testing?

2. a) What are the different design capture tools & explain them briefly?

Module 2

IMPORTANT QUESTIONS

1. Discuss a technique of testing a VLSI circuit under these levels. i). System level ii). Chip level

2. a). What is BILBO? Draw the logic diagram of BILBO & explain its operation in different modes? b). What are the designs styles of VHDL & Explain them with suitable examples?3. a). Draw the circuit design flow for VHDL? b). What is meant by controllability & observability? c). Mention the levels at which testing of a chip can be done? d). What are the design capture tools? e). What is circuit synthesis?

BITS

1. The advantage of a reset facility in the design is _________ 2. A 20 bit counter is split into four five bit section, the required steps for testing are ________3. Manufacturing tests are used to verify that ______ 4. VHDL, Verilog hardware description languages are used for testing of ___ 5. Functionality tests seek to verify the _____ 6. A measure of goodness of a test program is the amount of ____ 7. Generally the system is partitioned for testing because __________ 8. The two key concepts underlying all considerations for testability are __ 9. Being able to generate all states to fully excise all combinations of circuit states is called _______10. The faults occur due to thin-oxide shorts or metal-to metal shorts are called 11. On chip testing is obtained by using _____ 12. Signature analysis techniques are _______ 13. The manufacturing cost is low by detecting the malfunctioning of chip at a level of _______14. The tests that are usually carried after chip is manufactured are called____ 15. Generally memories are tested by _________ 16. In the structured testing technique, LSSD means _________

17. The IEEE 1149 boundary scan is used for _____________

ASSIGNMENTS1. Explain the method of switch level & timing simulation for CMOS circuits. 2. What is the difference between design capture tools & design verification tools?