UNIT - I BASIC ELECTRICAL PROPERTIES

Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT

P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)

https://potharajuvidyasagar.wordpress.com

Subject Code : EC702PC

Subject Name : VLSI DESIGN

UNIT - I

BASIC ELECTRICAL PROPERTIES

https://potharajuvidyasagar.wordpress.com/

Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT

Contents

BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits:

Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ωo ; Pass transistor,

NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.

VIDYA SAGAR P2

Department of Electronics and Communication Engineering, VBIT

Channel Charge

➢ MOS structure looks like parallel plate capacitor while operating in inversion

➢ Gate – oxide – channel

➢ Qchannel =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

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Channel Charge



➢ Qchannel = CV

➢ C =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

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Channel Charge



➢ Qchannel = CV

➢ C = Cg = oxWL/tox = CoxWL

➢ V =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

Cox = ox / tox

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Channel Charge



➢ Qchannel = CV

➢ C = Cg = oxWL/tox = CoxWL

➢ V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

Cox = ox / tox

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Carrier velocity

– Charge is carried by e-

– Carrier velocity v proportional to lateral E-field between source and drain

– v =

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Carrier velocity

➢ Charge is carried by e-

➢ Carrier velocity v proportional to lateral E-field between source and drain

➢ v = mE m called mobility

➢ E =

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Carrier velocity




➢ E = Vds/L

➢ Time for carrier to cross channel:

➢ t =

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Carrier velocity




➢ E = Vds/L

➢ Time for carrier to cross channel:

➢ t = L / v

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nMOS Linear I-V

➢ Now we know

➢ How much charge Qchannel is in the channel

➢ How much time t each carrier takes to cross

dsI =

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nMOS Linear I-V

➢ Now we know



channelds

QI

t=

=

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nMOS Linear I-V

➢ Now we know



channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

t

W VC V V V

L

VV V V

m

=

= − −

= − −

ox = W

CL

m

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nMOS Saturation I-V

➢ If Vgd < Vt, channel pinches off near drain

➢ When Vds > Vdsat = Vgs – Vt

➢ Now drain voltage no longer increases current

dsI =

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nMOS Saturation I-V




2dsat

ds gs t dsat

VI V V V = − −

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nMOS Saturation I-V




( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

= − −

= −

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nMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

= − −

−

➢ Shockley 1st order transistor models

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MOS Transistor Threshold Voltage Vt

The threshold voltage Vt may be expressed as:

➢ where QB = the charge per unit area in the depletion layer below the oxide

➢ Qss = charge density at Si: SiO2 interface

➢ Co =Capacitance per unit area.

➢ Φms = work function difference between gate and Si

➢ ΦfN = Fermi level potential between inverted surface and bulk Si

VIDYA SAGAR P18


Body effect

➢ The body effect is the change in the threshold voltage by an amount approximately equal to the

change in the source-bulk voltage, , because the body influences the threshold voltage (when it

is not tied to the source).

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Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT VIDYA SAGAR P20


PASS TRANSISTOR:

The nMOS transistors pass '0's well but ‘1’ s poorly. Figure(a) shows an nMOS transistor with the gate

and drain tied to VDD. Imagine that the source is initially at Vs = 0.

Vgs > Vtn, so the transistor is ON and current flows. If the voltage on the source rises to Vs = VDD -

Vtn, Vgs falls to Vtn and the transistor cuts itself OFF. Therefore, nMOS transistors attempting to pass

a '1' never pull thesource above VDD - Vtn. This loss is sometimes called a threshold drop

As the source can rise to within a

threshold voltage of the gate, the output of

several transistors in series is no more

degraded than that of a single transistor

(Figure (c)). However, if a degraded output

drives the gate of another transistor, the

second transistor can produce an even

further degraded output (Figure d).


nMOS INVERTER:

VIDYA SAGAR P25

The salient features of the n-MOS inverter are :

For the depletion mode transistor, the gate is connected to the source so it is always on.

In this configuration the depletion mode device is called the pull-up (P.U) and the enhancement mode

device the pull-down (P.D) transistor.

With no current drawn from the output, the currents Ids for both transistors must be equal.


CMOS Inverter Analysis:

VIDYA SAGAR P26

Region 3 is the region in which the inverter exhibits gain

and in which both transistors are in saturation. The currents

in each device must be the same, since the transistors are in

series. So, we can write that

Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P27

Region-1

In this region the input is in the range of (0,Vtn). Since the input voltage is less than Vtn, the NMOS is

in cutoff region. No current flows from Vdd to Vss, The entire Vdd will appear at the Output terminal.

•NMOS is in cutoff as Vgs < Vtn

•PMOS is in linear as Vgsp < Vtp and Vdsp > Vgsp -Vtp.

•Zero current flows from supply voltage and the power dissipation is zero.

Region-2

In this region the input is in the range of (Vtn,Vdd/2). Since the input voltage is greater than Vtn the

NMOS is conducting and it jumps to saturation as it has large Vds across it(Vout is high). PMOS still

remains in the linear region.

•NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

•PMOS is in linear region as Vdsp > Vgsp -Vtp.

•since both the transistors are conducting some amount of current flows from supply in this region.


Region-3

In this region the input voltage is Vdd/2. At this point the output voltage is also Vdd/2 as one can

see in figure-2. At this voltage both the NMOS and PMOS are in saturation and the output drops

drastically from Vdd to Vdd/2. At this point a large amount of current flows from the supply. Most

of the power consumed in CMOS inverter is at this point. So care should be taken that the Input

should not stay at Vdd/2 for more amount of time.

•NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

•PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

•Large amount of current is drawn from supply and hence large power dissipation.


Region-4

In this region the input voltage is in the range of (Vdd/2 , Vdd-Vtp). Here the PMOS remains in saturation

as Vout < Vin - Vtp and Vgsp < Vtp. But the NMOS moves from saturation to linear region since the drain

to source voltage now is less than Vgsn-Vtn.

•NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

•PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

•A medium amount of current is drawn as NMOS is in linear region and power dissipation is low.

Region-5

In this region the input voltage is in the range of (Vdd-Vtp,Vdd). Here the PMOS moves from saturation to

cutoff as the Vgsp is so high that Vgsp > Vtp. The NMOS still remains in linear as the drain to source

voltage now is less than Vgsn-Vtn.

•NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

•PMOS is in cutoff as Vgsp > Vtp.

•Zero current flows from the supply and so the power dissipation is zero.

Now that we have clearly understood the voltage transfer characteristics and operation of an NMOS, we

will discuss how to alter the transfer characteristics of any CMOS gate in the next article.


ALTERMTIVE FORMS OF PULL –UP:

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Determination of Pull-up to Pull –Down Ratio (Zp.u}Zp.d.)for an

nMOS Inverter driven by another nMOS Inverter:

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Pull -Up to Pull-Down ratio for an nMOS Inverter driven through

one or more Pass Transistors

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BiCMOS Inverter:

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Latch-up in CMOS circuits :

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A phenomenon called latch up can occur when

(1) both BJT's conduct, creating a low resistance path between Vdd and GND and

(2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than

one. The result of latch up is at the minimum a circuit malfunction, and in the worst case, the

destruction of the device.


nMOS Fabrication

VIDYA SAGAR P37


Thank you………………

UNIT - I BASIC ELECTRICAL PROPERTIES

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